Prosecution Insights
Last updated: August 17, 2026
Application No. 18/312,399

DEVICES AND SYSTEMS FOR SAMPLING PULSE AMPLITUDE MODULATION SIGNALS WITH REDUCED KICKBACK NOISE

Non-Final OA §102§103
Filed
May 04, 2023
Examiner
NGUYEN, LONG T
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices Inc.
OA Round
4 (Non-Final)
89%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
839 granted / 940 resolved
+21.3% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
22 currently pending
Career history
973
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
19.0%
-21.0% vs TC avg
§102
37.2%
-2.8% vs TC avg
§112
32.9%
-7.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 940 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/20/26 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Henmi et al. (US 2013/0162294). For claim 1, Figure 4 of Henmi et al. teaches a dual-tail sampler comprising: a first stage (100) comprising: an input pair of transistors (N1-N2) having inputs (DI, DIB) connected to gates of the input pair of transistors (N1-N2); a cross-coupled load circuit (P1-P2) having gates (gates of P1-P2) directly connected to drain nodes (NUB, NU) of the input pair of transistors (drains of N1-N2); and at least one pass-gate switch (P5-P6) between the input pair of transistors (N1-N2) and the cross-coupled load circuit (P1-P2). For claim 2, Figure 4 of Henmi et al. teaches wherein the at least one pass-gate switch (P5, P6) comprises a pair of complementary pass-gate switches (P5-P6, because transistors P5 and P6 turns on/off complementary to each other since they receive complementary signal from each other). For claim 3, Figure 4 of Henmi et al. teaches wherein the gates of the cross-coupled load circuit (P1-P2) are connected to the drain nodes (NUB, NU) of the input pair of transistors (N1, N2) rather than to output nodes (NDB, ND) of the first stage (100). For claim 4, Figure 4 of Henmi et al. teaches wherein the first stage (100) comprises an amplification stage (100). For claim 5, Figure 4 of Henmi et al. teaches further comprising a precharge device (N3-N4) connected between the drain nodes (NUB, NU) of the input pair of transistors. For claim 6, Figure 4 of Henmi et al. teaches comprises a second stage (200) coupled to the first stage (100). For claim 7, Figure 4 of Henmi et al. teaches wherein the second stage (200) comprises an amplification stage (200). Claims 1 and 4-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shiratake (USP 6,147,514). For claim 1, Figure 11 of Shiratake teaches a dual-tail sampler comprising: a first stage (Mp1-Mp3, Mn1-Mn3, MX1-MX2) comprising: an input pair of transistors (Mn1-Mn2) having inputs (Q, /Q) connected to gates of the input pair of transistors (Mn1-Mn2); a cross-coupled load circuit (MX1-MX2) having gates (gates of MX1-MX2) directly connected to drain nodes of the input pair of transistors (drains of Mn1-Mn2); and at least one pass-gate switch (Mp3) between the input pair of transistors (Mn1-Mn2) and the cross-coupled load circuit (MX1-MX2). For claim 4, Figure 11 of Shiratake teaches wherein the first stage (Mp1-Mp3, Mn1-Mn3, MX1-MX2) comprises an amplification stage (Mp1-Mp3, Mn1-Mn3, MX1-MX2). For claim 5, Figure 11 of Shiratake teaches a precharge device (Mp1-Mp2) connected between the drain nodes of the input pair of the transistors (drains of Mn1-Mn2). For claim 6, Figure 11 of Shiratake teaches a second stage (Mp4-Mp5, Mn4-Mn6) coupled to the first stage (Mp1-Mp3, Mn1-Mn3, MX1-MX2). For claim 7, Figure 11 of Shiratake teaches wherein the second stage (Mp4-Mp5, Mn4-Mn6) comprises an amplification stage (Mp4-Mp5, Mn4-Mn6). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over either Henmi et al. (US 2013/0162294) or Shiratake (USP 6,147,514) in view of Mohan (USP 7,800,411). For claim 8, each of Henmi et al. (Figure 4) and Shiratake (Figure 11) teaches a dual-tail sampler includes all the limitations of this claim as discussed in the 102 rejection above except for “the dual-tail sampler further comprising a set-reset latch that encodes a sampled signal from the second stage as a bit”. However, Figure 4 of Mohan teaches a set-reset latch (420, 430) that encodes a sampled signal from the second stage (410, 430) as a bit. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the dual-tail sampler in each of Henmi et al. (Figure 4) and Shiratake (Figure 11) to include a set-reset latch (420, 430), as taught in Figure 4 of Mohan, that encodes a sampled signal from the second stage as a bit for the purpose to hold the output values during reset for improve the performance of the dual-tail sampler circuitry (Mohan, Col. 1, lines 25-33; and Col. 4, lines 19-35). Allowable Subject Matter Claims 9-20 are allowed. Response to Arguments Applicant's arguments filed on 05/20/26 have been fully considered but are moot in view of the new ground of rejection(s). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /Long Nguyen/ Primary Examiner Art Unit 2836
Read full office action

Prosecution Timeline

Show 2 earlier events
Feb 24, 2025
Non-Final Rejection mailed — §102, §103
May 13, 2025
Response Filed
Aug 22, 2025
Non-Final Rejection mailed — §102, §103
Nov 14, 2025
Response Filed
Mar 02, 2026
Final Rejection mailed — §102, §103
May 20, 2026
Request for Continued Examination
May 22, 2026
Response after Non-Final Action
Jun 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.3%)
1y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 940 resolved cases by this examiner. Grant probability derived from career allowance rate.

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