DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mohan (USP 7,800,411).
For claim 1, Figures 3-4 of Mohan teaches a dual-tail sampler comprising: a first stage (300) comprising: an input pair of transistors (Q40-Q41); a cross-coupled load circuit (Q20-Q21) having gates (Q20-Q21) connected to drain nodes of the input pair of transistors (Q40-Q41, by way of Q30-Q31); and at least one pass-gate switch (Q30-Q31) between the input pair of transistors(Q40-Q41) and the cross-coupled load circuit (Q20-Q21).
For claim 4, Figures 3-4 of Mohan teaches wherein the first stage (300) comprises an amplification stage (300).
For claim 5, Figures 3-4 of Mohan teaches a precharge device (Q10-Q11) connected between the drain nodes of the input pair of the transistors (Q40-Q41, by way of Q30-Q31).
For claim 6, Figure 4 of Mohan teaches a second stage (410, 430) coupled to the first stage (300).
For claim 7, Figure 4 of Mohan teaches wherein the second stage (410, 430) comprises an amplification stage (410, 430).
For claim 8, Figure 4 of Mohan teaches a set-reset latch (420, 440) that encodes a sampled signal (outputs of 410 and 430) from the second stage (410, 430) as a bit.
Claims 1-2 and 4-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ainspan et al. (USP 9,699,009).
For claim 1, Figure 9 of Ainspan et al. teaches a dual-tail sampler (Figure 9) comprising a first stage (the left side stage in Figure 9 which includes all transistors in Figure 9 except for transistors 910, 912, and 914) comprising: an input pair of transistors (906, 908); a cross-coupled load circuit (920, 924) having gates (920, 924) connected to drain nodes of input pair of transistors (906, 908; by way of 922 and 926, respectively); and at least one pass-gate switch (922, 926) between the input pair of transistors (906, 908) and the cross-coupled load circuit (920, 924).
For claim 2, Figure 9 of Ainspan et al. teaches wherein the at least one pass-gate switch (922, 926) comprises a pair of complementary pass-gate switches (922 and 926, because transistors 922 and 926 turn on/off complementary to each other since they receive complementary signal from each other).
For claim 4, Figure 9 of Ainspan et al. teaches wherein the first stage (the left side stage in Figure 9) comprises an amplification stage (the left side stage in Figure 9).
For claim 5, Figure 9 of Ainspan et al. teaches further comprising a precharge device (904, 916, 918) connected between the drain nodes of the input pair of transistors (906, 908).
For claim 6, Figure 9 of Ainspan et al. teaches comprises a second stage (910, 912, 914) coupled to the first stage (the left side stage in Figure 9 which includes all transistors in Figure 9 except for transistors 910, 912, and 914).
For claim 7, Figure 9 of Ainspan et al. teaches wherein the second stage (910, 912, 914) comprises an amplification stage (910, 912, 914).
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shahi (USP 11,626,863).
For claim 1, Figure 7 of Shahi teaches a dual-tail sampler comprising a first stage (all of 700 excepted for the 2 cross-coupled transistors connected to AVSS) comprising: an input pair of transistors (the 2 transistors receiving D and D-b); a cross-coupled load circuit (the 2 cross-coupled transistors receiving AVDD) having gates connected to drain nodes of input pair of transistors (the 2 transistors receiving D and D-b); and at least one pass-gate switch (the two transmission gates connected to L1 and L2) between the input pair of transistors (the 2 transistors receiving D and D-b) and the cross-coupled load circuit (the 2 cross-coupled transistors receiving AVDD).
For claim 2, Figure 7 of Shahi teaches wherein the at least one pass-gate switch (the two transmission gates connected to L1 and L2) comprises a pair of complementary pass-gate switches (the two transmission gates connected to L1 and L2 each comprise a pair of complementary transistors).
For claim 3, Figure 7 of Shahi teaches wherein the gates of the cross-coupled load circuit (the 2 cross-coupled transistors receiving AVDD) are connected to the drain nodes of the input pair of transistors (the 2 transistors receiving D and D-b) rather than to output nodes (Q, Q-b) of the first stage (all of 700 excepted for the 2 cross-coupled transistors connected to AVSS).
For claim 4, Figure 7 of Shahi teaches wherein the first stage (all of 700 excepted for the 2 cross-coupled transistors connected to AVSS) comprises an amplification stage (700).
For claim 6, Figure 7 of Shahi teaches comprises a second stage (the 2 cross-coupled transistors connected to AVSS) coupled to the first stage (all of 700 excepted for the 2 cross-coupled transistors connected to AVSS).
For claim 7, Figure 7 of Shahi teaches wherein the second stage (the 2 cross-coupled transistors connected to AVSS) comprises an amplification stage (the 2 cross-coupled transistors connected to AVSS).
Allowable Subject Matter
Claims 9-20 are allowed.
Response to Arguments
Applicant's arguments filed on 11/14/25 have been fully considered but they are not persuasive.
Applicant argues that “independent claim 1 is amended herein to recite, inter alia, "a cross-coupled load circuit having gates connected to drain nodes of the input pair of transistors," which is supported by at least paragraphs [0043]-[0045] and FIG. 7 of the originally filed specification. Turning to FIG. 3 of Mohan, assuming, ad arguendo, that Q40 and Q41 discloses "an input pair of transistors" recited in independent claim 1 and that Q20 and Q21 discloses "a cross-coupled load circuit" recited in independent claim 1, as asserted in the Office Action, Mohan fails to disclose or suggest the gates of Q20 and Q21 are connected to the drain nodes of Q40 and Q41. Accordingly, Mohan fails to disclose or suggest at least "a cross-coupled load circuit having gates connected to drain nodes of the input pair of transistors" as recited in currently amended independent claim 1. The other cited references are not seen to cure these deficiencies of Mohan (see, e.g., FIG. 9 of Ainspan and FIG. 5B of Dong). Thus, currently amended independent claim 1 is patentably distinguishable over the cited references”. However, the arguments are not found persuasive because the claim 1 broadly recites “a cross-coupled load circuit having gates connected to drain nodes of the input pair of transistors” and does not specifically recite the directly connection, so for broadest reasonable interpretation, both Mohan and Ainspan still read on the claim as discussed above (in Mohan, Figure 3 teaches “a cross-coupled load circuit (Q20-Q21) having gates (Q20-Q21) connected to drain nodes of the input pair of transistors (Q40-Q41, by way of Q30-Q31)”; and in Ainspan, Figure 9 teaches “a cross-coupled load circuit (920, 924) having gates (920, 924) connected to drain nodes of input pair of transistors (906, 908; by way of 922 and 926, respectively)”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan, can be reached at (571) 272-1988. The fax number for this group is (571) 273-8300.
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Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/Long Nguyen/
Primary Examiner, Art Unit 2842