DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Miscellaneous
The Applicant has added new claims 29-32; therefore, claims 1-32 remain for this Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 and 15-32 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2014/0145773) in view of Iadanza (US 11,764,764).
In regards to claim 1, Hashimoto discloses of a level shifter circuit comprising: a first output voltage supply (VDD); a second output voltage supply (VSS), the second output voltage supply having a lower voltage than the first output voltage supply (for example see Paragraph 0004); and a latch circuit (see Fig 17) comprising a first logic gate (19), a second logic gate (20), a latch output terminal (OUT), and an additional latch output terminal (for example not illustrated but connected to node N2, see Paragraphs 0042, 0046, 0048); wherein the latch circuit is configured to provide a first output signal (OUT) as an output of the latch circuit; wherein the first logic gate (19) comprises: at least two first transistors (12, 15), each of the first transistors (12, 15) being multi-gate transistors having a front gate and a back gate, a first main input terminal coupled to the back gates of the first transistors (12, 15), a first secondary input terminal coupled to the front gates of the first transistors (12, 15, see Fig 17), and a first output terminal; wherein the second logic gate (20) comprises: at least two second transistors (13, 16), each of the second transistors (13, 16) being multi-gate transistors having a front gate and a back gate, a second main input terminal coupled to the back gates of the second transistors (13, 16), a second secondary input terminal coupled to the front gates of the second transistors (13, 16, see Fig 17), and a second output terminal; wherein the first secondary input terminal is coupled to the second output terminal; wherein the second secondary input terminal is coupled to the first output terminal; wherein when the latch circuit is in a first state, the latch output terminal is coupled to the first output voltage supply; wherein when the latch circuit is in a second state, the latch output terminal is coupled to the second output voltage supply; and wherein the latch circuit is configured to be in the first state or the second state based on inputs to the first main input terminal and the second main input terminal (see Fig 17); and wherein the additional latch output (connected to node N2, see Paragraphs 0042, 0046, 0048) is coupled to a drain of one of the at least two first transistors (12, 15) of the first logic gate (19, for example see Figs 1, 17 and Paragraphs 0046, 0048, 0077; although no additional terminal is shown, the output of the first logic gate 19 at node N2 is an additional latch output that is the inverse potential of OUT).
Although one of ordinary skill in the art would readily recognize the potential of N2 has the inverse potential of the OUT signal and may be considered as an additional output terminal and output signal and having a connection of a separate line to the potential, Hashimoto does not explicitly disclose of the latch circuit providing first and second signals as outputs of the latch circuit, and wherein the latch circuit is configured to provide the first and second signals respectively via the latch output terminal and the additional latch output terminal; and wherein the additional latch output is coupled to at least one of the drains of the two first transistors without coupling to the secondary input terminal.
Iadanza discloses a latch circuit (220, 320, 420, 520) comprising a first logic gate (comprised of 101, 102), a second logic gate (comprised of 103, 104), a latch output terminal (OUT), and an additional latch output terminal (OUTF), wherein the latch circuit (220, 320, 420, 520) is configured to provide first and second signals (OUT, OUTF) as outputs of the latch circuit (see Figs 2-5), and wherein the latch circuit (220, 320, 420, 520) is configured to provide the first and second signals (OUT, OUTF) respectively via the latch output terminal (OUT) and the additional output terminal (OUTF, see Figs 2-5), wherein the first logic gate comprises at least two first transistors (101, 102), a first input terminal and a first output terminal (at N1), wherein the second logic gate comprises at least two second transistors (103, 104), a second input terminal and a second output terminal (at N2); wherein the latch output (OUT) is coupled between two of the at least second transistors (103, 104) of the second logic gate, and the additional latch output (OUTF) is coupled between two of the at least first transistors (101, 102) of the first logic gate; and wherein the additional latch output terminal (OUTF) is coupled to a drain of one of that at least two first transistors (101, 102) of the first logic gate, without coupled the secondary input terminal that is coupled to the front gates of the second transistors 103, 104, the line connected to OUTF at N1 is separate from the line connected to the inputs of 103, 104, see Figs 2-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have first and second output signals being outputs of a latch circuit with the additional latch output not being coupled to the input of the transistors of the second logic circuit as taught by Iadanza for latching signals that provide complimentary output signals for stable digital logic switching and operations without needing an additional inverter at the output.
In regards to claim 2, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the level shifter circuit further comprises an input circuit (17), the input circuit comprising: a first input voltage supply (VBG(P)), and a second input voltage supply (VBG(N)), the second input voltage supply having a lower voltage than the first input voltage supply (for example see Paragraph 0047), wherein the first input voltage supply and the second input voltage supply are coupled to the first main input terminal and the second main input terminal (see Hashimoto Figs 1, 17).
In regards to claim 3, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 2, wherein both the first input voltage supply and the second input voltage supply have a lower voltage than the second output voltage supply, or wherein both the first input voltage supply and the second input voltage supply have a higher voltage than the first output voltage supply (see Hashimoto Figs 1, 17).
In regards to claim 4, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the at least two first transistors comprise a first NMOS (15, T1) transistor and a first PMOS transistor (12, T2), and/or wherein the at least two second transistors comprise a second NMOS transistor (16, 103) and a second PMOS transistor (13, 104; see Hashimoto Figs 1, 17 and Iadanza Figs 2-5).
In regards to claim 5, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 4, wherein the first NMOS transistor (15) and the first PMOS transistor (12) are asymmetric, and/or wherein the second NMOS transistor (16) and the second PMOS transistor (13) are asymmetric (see Hashimoto Fig 17, PMOS and NMOS by nature are asymmetric to one another, also see Fig 21).
In regards to claim 6, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the first logic gate (19) comprises one or more first primary well(s), and/or wherein the second logic gate (20) comprises one or more second primary well(s) (see Hashimoto Figs 1, 17, 21, the doped regions of the transistors will define their respective wells).
In regards to claim 7, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 6, wherein the first logic gate (19) comprises one or more first secondary well(s), each of the one or more first secondary well(s) being embedded in a first primary well, and/or wherein the second logic gate (20) comprises one or more second secondary well, each of the one or more second secondary well(s) being embedded in a second primary well (the doped regions of the combined NMOS and PMOS transistors (forming the CMOS inverter) will be embedded together during fabrication, also see Hashimoto Fig 21).
In regards to claim 8, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the first logic gate (19) is a first inverter circuit, and the second logic gate (20) is a second inverter circuit (see Hashimoto Figs 1, 17 and Paragraphs 0042, 0077; and Iadanza Figs 2-5).
In regards to claim 9, Hashimoto in view of Iadanzal disclose of the level shifter circuit of claim 1, wherein the latch operates at a high speed (for example see Hashimoto Paragraphs 0050, 0064, 0066, 0070, 0076, 0101).
However, Hashimoto and Iadanza do not explicitly disclose of wherein the latch circuit is configured to switch between the first and second states in less than 1 ns.
Although one having ordinary skill in the art may easily identify less than 1 ns as being high-speed, it also has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the switching between states being less than 1ns for achieving the optimum transition speed between states to improve the overall operation of the level shifter circuit.
In regards to claim 10, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the first transistors (12, 15) and/or the second transistors (13, 16) are one or more of the following type: Partially Depleted Silicon on Oxide, PD-SOI, field effect transistor, FET, Fully Depleted Silicon on Oxide, FD-SOI, FET, finFET, and flexFET (for example see Hashimoto Figs 1, 17, 21 and Paragraphs 0005, 00088).
In regards to claim 11, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the first logic gate (19) and the second logic gate (20) are symmetric with each other (see Hashimoto Figs 1, 17, 21; Iadanza Figs 2-5).
In regards to claim 15, Hashimoto in view of Iadanza disclose of the multi-level shifter circuit of claim 13, wherein the second output voltage supply of one of the level shifter circuits and the first output voltage supply of another one of the level shifter circuits have the same voltage (see Hashimoto Figs 1, 17).
In regards to claim 16, Hashimoto in view of Iadanza disclose of the multi-level shifter circuit of claim 13, wherein the level shifter circuits share a first primary well, and/or a second primary well (see Hashimoto Fig 21).
In regards to claim 17, Hashimoto discloses of a latch circuit comprising: a first logic gate (19); and a second logic gate (20); wherein the first logic gate comprises: at least two first transistors (12, 15), each of the first transistors being multi-gate transistors having a front gate and a back gate, a first main input terminal coupled to the back gates of the first transistors (12, 15), a first secondary input terminal coupled to the front gates of the first transistors (12, 15, see Fig 17), and a first output terminal; wherein the second logic gate (20) comprises: at least two second transistors (13, 16), each of the second transistors (13, 16) being multi-gate transistors having a front gate and a back gate, a second main input terminal coupled to the back gates of the second transistors (13, 16), a second secondary input terminal coupled to the front gates of the second transistors (13, 16, see Fig 17), and a second output terminal; wherein the first secondary input terminal is coupled to the second output terminal; wherein the second secondary input terminal is coupled to the first output termina (see Fig 17); and wherein the latch circuit comprises a latch output terminal (OUT) configured to provide an output signal, and an additional latch output terminal (not illustrated but connected to node N2, see Paragraphs 0042, 0046, 0048) configured to provide an inverted output potential (at node N2; for example see Figs 1, 17 and Paragraphs 0046, 0048, 0077; although no additional terminal is shown, the output of the first logic gate 19 at node N2 is an additional latch output that is the inverse potential of OUT), wherein the output signal (OUT) is an output of the latch circuit; and wherein the additional latch output terminal (connected at node N2) is coupled to a drain of one of the at least two transistors (12, 15) of the first logic circuit (19, see Figs 1, 17).
Although one of ordinary skill in the art would readily recognize the potential of N2 has the inverse potential of the OUT signal and may be considered as an additional output terminal and output signal and having a connection of a separate line to the potential, Hashimoto does not explicitly disclose of the latch circuit providing first and second signals as outputs of the latch circuit, and wherein the latch circuit is configured to provide the first and second signals respectively via the latch output terminal and the additional latch output terminal; and wherein the additional latch output is coupled to at least one of the drains of the two first transistors without coupling to the secondary input terminal.
Iadanza discloses a latch circuit (220, 320, 420, 520) comprising a first logic gate (comprised of 101, 102), a second logic gate (comprised of 103, 104), a latch output terminal (OUT), and an additional latch output terminal (OUTF), wherein the latch circuit (220, 320, 420, 520) is configured to provide first and second signals (OUT, OUTF) as outputs of the latch circuit (see Figs 2-5), and wherein the latch circuit (220, 320, 420, 520) is configured to provide the first and second signals (OUT, OUTF) respectively via the latch output terminal (OUT) and the additional output terminal (OUTF, see Figs 2-5), wherein the first logic gate comprises at least two first transistors (101, 102), a first input terminal and a first output terminal (at N1), wherein the second logic gate comprises at least two second transistors (103, 104), a second input terminal and a second output terminal (at N2); wherein the latch output (OUT) is coupled between two of the at least second transistors (103, 104) of the second logic gate, and the additional latch output (OUTF) is coupled between two of the at least first transistors (101, 102) of the first logic gate; and wherein the additional latch output terminal (OUTF) is coupled to a drain of one of that at least two first transistors (101, 102) of the first logic gate, without coupled the secondary input terminal that is coupled to the front gates of the second transistors 103, 104, the line connected to OUTF at N1 is separate from the line connected to the inputs of 103, 104, see Figs 2-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have first and second output signals being outputs of a latch circuit with the additional latch output not being coupled to the input of the transistors of the second logic circuit as taught by Iadanza for latching signals that provide complimentary output signals for stable digital logic switching and operations without needing an additional inverter at the output.
In regards to claim 18, Hashimoto in view of Iadanza disclose of the latch circuit of claim 17, wherein when the latch circuit is in a first state, the latch output terminal is coupled to a first output voltage supply (VDD); wherein when the latch circuit is in a second state, the latch output terminal is coupled to a second output voltage supply (VSS); and wherein the latch circuit is configured to be in the first state or the second state based on inputs to the first main input terminal and the second main input terminal (see Hashimoto Figs 1, 17).
In regards to claim 19, Hashimoto in view of Iadanza disclose of a level shifter circuit comprising the latch circuit of claim 18, the first output voltage supply, and the second output voltage supply (see Hashimoto Figs 1, 17).
In regards to claim 20, Hashimoto in view of Idanza disclose of a multi-level shifter circuit comprising the latch circuit of claim 17 and an additional latch circuit (see Figs 28-29) having a third logic gate and a fourth logic gate (for example 100-1:100-N and 110-1:110-N would be similar latching structure as seen in Figs 1, 17); wherein the third logic gate comprises: at least two third transistors, each of the third transistors being multi-gate transistors having a front gate and a back gate, a third main input terminal coupled to the back gates of the third transistors, a third secondary input terminal coupled to the front gates of the third transistors, and a third output terminal; wherein the fourth logic gate comprises: at least two fourth transistors, each of the fourth transistors being multi-gate transistors having a front gate and a back gate, a fourth main input terminal coupled to the back gates of the fourth transistors, a fourth secondary input terminal coupled to the front gates of the fourth transistors, and a fourth output terminal; wherein the third secondary input terminal is coupled to the fourth output terminal; and wherein the fourth secondary input terminal is coupled to the third output terminal (see Hashimoto Figs 1, 17 and 28-29, detailed logic gates illustrated in Figs 1, 17).
In regards to claim 21, Hashimoto in view of Iadanza disclose of the multi-level shifter circuit of claim 20, wherein the first main input terminal of the first logic gate is connected to the third main input terminal of the third logic gate; and wherein the second main input terminal of the second logic gate is connected to the fourth main input terminal of the fourth logic gate (for example see Hashimoto Figs 1, 17, 28-29).
In regards to claim 22, Hashimoto in view of Iadanza disclose of the multi-level shifter circuit of claim 20, wherein the latch circuit and the additional latch circuit are configured to couple to respective first output voltage supplies, and wherein the first output voltage supplies have different respective voltages (for example see Hashimoto Figs 28-29).
In regards to claim 23, Hashimoto in view of Iadanza disclose of the multi-level shifter circuit of claim 20, wherein the latch circuit is configured to couple to a voltage supply, and wherein the additional latch circuit is configured to couple to the voltage supply (for example see Hashimoto Figs 28-29).
In regards to claim 24, Hashimoto in view of Iadanza disclose of the multi-level shifter circuit of claim 20, wherein the first logic gate and the third logic gate share a first primary well (for example see Hashimoto Figs 1, 17, 21, 28-29, the doped regions of the combined NMOS and PMOS transistors (forming the CMOS inverters and latches) will be shared during fabrication).
In regards to claim 25, Hashimoto in view of Iadanza disclose of the multi-level shifter circuit of claim 24, wherein the second logic gate and the fourth logic gate share a second primary well (for example see Hashimoto Figs 1, 17, 21, 28-29, the doped regions of the combined NMOS and PMOS transistors (forming the CMOS inverters and latches) will be shared during fabrication).
In regards to claim 26, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the latch output terminal (OUT) is configured to provide an output signal (OUT), and wherein the additional latch output terminal (not illustrated but connected to node N2, see Paragraphs 0046, 0048, 0077) is configured to provide an inverted output signal (at node N2; for example see Hashimoto Figs 1, 17 and Paragraphs 0046, 0048, 0077; although no additional terminal is shown, the output of the first logic gate 19 at node N2 is an additional latch output that is the inverse potential of OUT, also see output signals OUT and OUTF of Iadanza in Figs 2-5).
In regards to claim 27, Hashimoto in view of Iadanza disclose of the latch circuit of claim 17, wherein the latch output terminal (OUT, OUT) is coupled between two of the at least two second transistors (13, 16/103, 104) of the second logic gate (20, see Hashimoto Figs 1, 17 and Iadanza Figs 2-5).
In regards to claim 28, Hashimoto in view of Iadanza disclose of the latch circuit of claim 17, wherein the additional latch output terminal (not illustrated but connected to node N2, see Paragraph 0046, 0048, 0077; or OUTF in Iadanza) is coupled between two of the at least two first transistors (12, 15/101, 102) of the first logic gate (19, see Hashimoto Figs 1, 17 and Paragraphs 0046, 0048, 0077; Iadanza Figs 2-5).
In regards to claim 29, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein another one of the at least two first transistors (12, 15/101, 102) of the first logic gate and the one of the at least two first transistors (12, 15/101, 102) of the first logic gate share the drain (see Hashimoto Figs 1, 17 and Iadanza Figs 2-5), and wherein the additional latch output terminal (at node N2 of Hashimoto, OUTF of Iadanza) is coupled to the drain of the one of the at least two first transistors (12, 15/101, 102) and the other one of the at least two first transistors (12, 15/101, 102), without coupling to the second secondary input terminal that is coupled to the front gates of the second transistors (13, 16,/103, 104, see Hashimoto Figs 1, 17 and Iadanza Figs 2-5).
In regards to claim 30, Hashimoto in view of Iadanza disclose of the level shifter circuit of claim 1, wherein the latch output terminal (OUT, OUT) is coupled to a drain of one of the at least two second transistors (13, 16/103, 104) of the second logic gate, without coupling to the first secondary input terminal that is coupled to the front gates of the first transistors (12, 15/101, 102, see Hashimoto Figs 1, 17 and Iadanza Figs 2-5).
In regards to claim 31, Hashimoto in view of Iadanza disclose of the latch circuit of claim 17, wherein another one of the at least two first transistors (12, 15/101, 102) of the first logic gate and the one of the at least two first transistors (12, 15/101, 102) of the first logic gate share the drain, and wherein the additional latch output terminal (at node N2 of Hashimoto, OUTF of Iadanza) is coupled to the drain of the one of the at least two first transistors (12, 15/101, 102) and the other one of the at least two first transistors (12, 15/101, 102), without coupling to the second secondary input terminal that is coupled to the front gates of the second transistors (13, 16/103, 104, see Hashimoto Figs 1, 17 and Iadanza Figs 2-5).
In regards to claim 32, Hashimoto in view of Iadanza disclose of the latch circuit of claim 17, wherein the latch output terminal (OUT, OUT) is coupled to a drain of one of the at least two second transistors (13, 16/103, 104) of the second logic gate, without coupling to the first secondary input terminal that is coupled to the front gates of the first transistors (12, 15/101, 102, see Hashimoto Figs 1, 17 and Iadanza Figs 2-5).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2014/0145773) in view Iadanza (US 11,764,764) as applied to claim 1 above, and in further view of Christensen (US 2022/0386045).
In regards to claim 12, Hashimoto in view of Iadanza disclose of a level shifter circuit as found within the explanation of claim 1 above.
However, Hashimoto and Iadanza do not explicitly disclose of a hearing device configured to be worn at an ear of a user, wherein the hearing device comprises: one or more input transducers; an output transducer; a battery; and circuitry comprising the level shifter circuit of claim 1.
Christensen discloses of a hearing device (10) configured to be worn at an ear of a user (see Paragraph 0006), wherein the hearing device comprises: one or more input transducers; an output transducer (see Paragraphs 0096-0097); a battery (60); and circuitry including level shifter circuitry (100, see Figs 1-3, 4A-B, 5-6).
It would have been obvious to one of ordinary skill in the art to have a hearing device using level shifter circuitry as taught by Christensen to translate between various voltage levels to optimize operation of the hearing device.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2014/0145773) in view of Iadanza (US 11,764,764) as applied to claim 1 above, and in further view of Asthana et al. (US 2014/0003135).
In regards to claim 13, Hashimoto and Iadanza disclose of the multi-level shifter circuit of claim 1 as found within the explanation above.
However, Hashimoto and Iadanza do not explicitly disclose of wherein the first main input terminals of the level shifter circuits are connected; and wherein the second main input terminals of the level shifter circuit are connected.
Asthana discloses of a level shifter circuit comprising: a first output voltage supply (VH); a second output voltage supply (VL), the second output voltage supply having a lower voltage than the first output voltage supply (for example see Paragraph 0002); and a latch circuit comprising a first logic gate (112), a second logic gate (114), and a latch output terminal; wherein the first logic gate (112) comprises: at least two first transistors (102, 104), each of the first transistors (102, 104) being multi-gate transistors having a front gate and a back gate, a first main input terminal coupled to the back gates of the first transistors (102, 104), a first secondary input terminal coupled to the front gates of the first transistors (102, 104, see Fig 4), and a first output terminal; wherein the second logic gate (114) comprises: at least two second transistors (106, 108), each of the second transistors (106, 108) being multi-gate transistors having a front gate and a back gate, a second main input terminal coupled to the back gates of the second transistors (106, 108), a second secondary input terminal coupled to the front gates of the second transistors (106, 108, see Fig 4), and a second output terminal; wherein the first secondary input terminal is coupled to the second output terminal; wherein the second secondary input terminal is coupled to the first output terminal; wherein when the latch circuit is in a first state, the latch output terminal is coupled to the first output voltage supply; wherein when the latch circuit is in a second state, the latch output terminal is coupled to the second output voltage supply; and wherein the latch circuit is configured to be in the first state or the second state based on inputs to the first main input terminal and the second main input terminal (see Fig 4); and wherein the first main input terminals of the level shifter circuits are connected; and wherein the second main input terminals of the level shifter circuits are connected (see Fig 4).
It would have been obvious to one of ordinary skill in the art to have the first and second main input terminals connected as taught by Asthana for synchronized back gate control to improve transitional timing speeds of the device.
In regards to claim 14, Hashimoto in view of Asthana disclose of the multi-level shifter circuit of claim 13, wherein the first output voltage supplies of the respective level shifter circuits have different respective voltages (see Hashimoto Figs 1, 17 and Asthana Fig 4).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-32 have been considered but are moot because the new ground of rejection does not solely rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Although it would be apparent to one having ordinary skill in the art to have a separate line connected to the output terminals of a latch circuit instead of having them connected along the same line as shown in the previous prior art, the newly applied prior art of Iadanza clearly shows separate lines connected between the inputs and outputs that are shared across the cross-coupled inverter latch as seen in example Figs 2-5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2845
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