CTNF 18/312,752 CTNF 83252 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4, 6-9 and 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 11,604,748), hereinafter referred to as Peng in view of Chafin et al. (US 10,915,478), hereinafter referred to as Chafin . Referring to claim 1 , Peng teaches, as claimed, a computing system comprising: a network controller; a plurality of dynamic random access memories (DRAMs); and a processor coupled to the network controller (see fig. 1 and col. 2, lines 24-32 and 36-42), the processor including logic coupled to one or more substrates (col. 3, lines 8-12 and/or 43-47), wherein the logic includes: a plurality of memory engines corresponding to a plurality of pipelines (i.e.-plurality of DMA controllers configured to receive plurality sequential read request 32/responses 34, col. 4, lines 12-14), wherein each memory engine in the plurality of memory engines is adjacent to a pipeline in the plurality of pipelines (i.e.- see fig. 5, 34A and 34B), and a plurality of operation engines corresponding to the plurality of DRAMs (i.e.-processing devices 14 corresponding to plurality of memory devices, col. 2, lines 41-43), wherein each operation engine in the plurality of operation engines is adjacent to a DRAM in the plurality of DRAMs (see fig. 1; memory device 12 and processing device 14). However, Peng does not teach wherein a first memory engine is to request one or more direct memory access (DMA) operations associated with a first pipeline, and wherein one or more of the plurality of operation engines is to conduct the one or more DMA operations based on one or more bitmaps. On the other hand, Chafin discloses method and apparatus for scatter gather processing engine in a storage controllers, including DMA systems to request one or more direct memory access (DMA) operations (col. 4, lines 50-53 and col. 5, lines 53-55) associated with a first pipeline, and wherein one or more of the plurality of operation engines is to conduct the one or more DMA operations based on one or more bitmaps (col. 6, lines 25-27). Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Peng so that the first memory engine is to request one or more direct memory access (DMA) operations associated with a first pipeline, and wherein one or more of the plurality of operation engines is to conduct the one or more DMA operations based on one or more bitmaps, as taught by Chafin. The motivation for doing so would have been to initiate data transfers by instructing DMA controllers to use descriptors in a DMA descriptor table. As to claim 2, the modified Peng in view of Chafin teaches the computing system of claim 1, wherein the one or more of the plurality of operation engines is to conditionally transfer data based on the one or more bitmaps (see Chafin, col. 5, lines 30-32). As to claim 3, the modified Peng teaches the computing system of claim 1, wherein the one or more DMA operations include one or more of a gather operation, a scatter operation or a broadcast operation (see Chafin, col. 4, lines 51-53 & col. 5, lines 5-7; and see Peng, col. 3, line 41). As to claim 4, the modified Peng teaches the computing system of claim 1, wherein the one or more DMA operations are conducted in one or more of a base plus offset mode or an address mode (see Chafin, col. 6, lines 25-27; and col. 8, lines 29-32). Referring to claims 6-9, the claims are substantially the same as claims 1-4, hence the rejection of claims 1-4 is applied accordingly. Referring to claims 11-17, the claims are substantially the same as claims 1-4, hence the rejection of claims 1-4 is applied accordingly. Examiner’s note: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner . Claim Objections 12-151-08 AIA 07-43 12-51-08 Claim s 5, 10 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US 7,689,732), Murata (US 6,628,289), Katayama (US 5,926,839), Kobayashi et al. (US 6,014,339) and Vu (US 8,417,842) do teach memory system comprised of plurality of DRAMs, controllers and pipelines to perform multiple DMA operations based on associated bit maps . Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HENRY TSAI can be reached at 571-272-4176. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Elias Mamo/Primary Examiner, Art Unit 2184 Application/Control Number: 18/312,752 Page 2 Art Unit: 2184 Application/Control Number: 18/312,752 Page 3 Art Unit: 2184 Application/Control Number: 18/312,752 Page 4 Art Unit: 2184 Application/Control Number: 18/312,752 Page 5 Art Unit: 2184 Application/Control Number: 18/312,752 Page 6 Art Unit: 2184
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