DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 05/05/2023 for application number 18/313,242.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Paragraph 21 states “Factors pointing away from a conclusion that the processor activity is inconsistent with the low power state…” and “Factors pointing toward a conclusion that the processor activity is consistent with the low power state…”; both of these phrases are directed at the same condition, please correct one of the phrases to distinguish the two conclusions
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 8, 10-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lake et al. (US 2021/0303053 A1) in view of Garg et al. (US 2017/0177046 A1).
Regarding claim 1, Lake teaches an apparatus (Figures 1, 3, 8, 9), comprising:
a chip package (Figure 8, SoC 801) comprising a processor (Figure 8, processor 804) and one or more counters (Figure 3, timers 390), wherein each counter of the one or more counters is to provide a count which represents an idle time of a respective subsystem of one or more subsystems (“monitor 380 is coupled to (or alternatively, includes) one or more timers 390 which are each operable to count or otherwise track the running of a respective limited period of time.” Par 0056 and “Based on such operation of the one or more timers 390, monitor 380 detects whether a duration of a power state, and/or a duration of an attempted power state transition, exceeds a predetermined time limit.” Par 0057); and
determine whether activity of the processor is inconsistent with the low power state based on the count from each counter of the one or more counters (“where it is … determined at 414 that the power domain has yet to complete an entry into the LPS, method 400 performs another evaluation (at 420) to determine whether the timer has expired while … the power domain is outside of the LPS … method 400 generates an interrupt message (at 422)” Par 0064 and “The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time.” Abstract, and par. 25 and Figure 4) [timers are utilized to track amount of time a subsystem spends in/out of a low power state, effectively counting the idle time to determine if the system’s activity is consistent with the low power mode, also see Figures 2 and 4].
However, Lake does not explicitly teach an embedded controller (EC); and a serial peripheral interface (SPI) bus coupled to the chip package and the embedded controller, wherein when the processor enters a low power state, the EC is to obtain the count from each counter of the one or more counters via the SPI bus.
In the analogous art, Garg teaches an embedded controller (EC) (Figure 14, EC 1435 and “The system may further include a management controller coupled to the processor.” Par 0183); and
a serial peripheral interface (SPI) bus coupled to the chip package and the embedded controller (“Also seen in FIG. 14, various peripheral devices may couple to processor 1410 via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller 1435.” Par 0108 and “communications may be via a variety of communication protocols such as … SPI, HDMI, among other types of communication protocols” par 0081 and Figure 14), wherein when the processor enters a low power state , the EC is to obtain the count from each counter of the one or more counters via the SPI bus (“telemetry data control logic 2050 may be configured to maintain telemetry data, e.g., associated with a plurality of different counter types, such as one or more core activity counters, one or more core inactivity counters” par 0141 and “the power controller is to communicate at least some of the telemetry information to the management controller.” Par 0184 and “To avoid losing such data, responsive to receipt of this low power state request, the telemetry data may be sent” par 0156).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lake and Garg before him before the effective filing date of the claimed invention, to have modified Lake to incorporate the teachings of Garg to incorporate a SPI bus to communicate with the EC for high speed data transfer and lower latency.
Regarding claim 2, Lake and Garag teach the apparatus of claim 1. Lake further teaches wherein:
the chip package is to transmit a C10 signal and an SLP_S0# signal to a voltage regulator (“controller logic 140 sends one or more signals … to variously configure one of more of devices 122. For example … selectively enabling/disabling voltage supply circuitry” par 0034 and “PCU 810 and/or PMIC 812 may control a voltage output by VR 814 … by outputting the VID signal” par 0107 and “PMC 310 is coupled to participate in communications with the power domain and, based on such communications, to initiate and/or otherwise manage one or more attempts to provide an LPS of the power domain.” Par 0052 and “the LPS of the domain includes, requires or is otherwise based on said local power state of processor unit 350.” Par 0053) [the SLP_S0# signal corresponds to the signals used to configure the low power state (LPS) of the power domain (platform)]; the C10 signal indicates whether the processor is in the low power state (“μC 512 receives another signal 522 which specifies or otherwise indicates that CPU 514 has entered a local power state (in this example, a C10 power state)” par 0068);
the SLP_S0# signal indicates whether a platform of the processor is in the low power state (“During the one or more attempts to transition the power domain to the LPS, signals 144 communicate to controller logic 140 various operational conditions of the power domain —e.g., wherein signals 144 indicate a current power state of the power domain” par 0035); and
the EC is to determine whether the activity of the processor is inconsistent with the low power state without accessing the C10 signal or the SLP_S0# signal (“timer 150 is coupled to provide to a detector 160 of circuit 120 a signal 152 which indicates an expiration of a time limit … Based on signal 152 indicating such an expiration, detector 160 generates a signal 162 which provides a basis for modifying operation” par 0037 and “In response to the detection 627, FD 616 communicates a signal 628 to bring CPU 614 out of a local power state (in this example, a C10 state).” Par 0073) [the inconsistency is determined based on the timer’s expiration rather than accessing the C10 or low power signals].
Regarding claim 3, Lake and Garag teach the apparatus of claim 1. Lake further teahces wherein the one or more subsystems comprise at least one of a Serial Advanced Technology Attachment (SATA) interface, an audio controller, a hard drive controller, a Universal Serial Bus (USB) controller, or a Peripheral Component Interconnect (PCI) express interface (“control hub 832 may couple to various devices using any appropriate communication protocol, e.g., PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.” par 0090 and Figure 8, control hub 832 and paragraphs 87-89).
Regarding claim 7, Lake and Garag teache the apparatus of claim 1. Lake further teaches wherein when the processor enters the low power state, the EC is to obtain internal temperature data of the processor via the SPI bus and determine whether the activity of the processor is inconsistent with the low power state based on the internal temperature data (“temperature measurement circuitries 840 may measure temperature of (or within) one or more of cores 808 a, 808 b, 808 c,” Par 0099 and “Interconnect circuitry 320 includes any of a variety of one or more busses … and/or other connection mechanisms to variously couple one or more devices of SOC 300 to PMC 310.” Par 0048 and “PMIC 812 is communicatively coupled to one or more sensors … sensor(s) may be directly coupled to PCU 810 and/or PMIC 812 in at least one embodiment to allow PCU 810 and/or PMIC 812 to manage processor core energy at least in part based on value(s) detected by one or more of the sensors… Examples of the one or more factors include … temperature…PMIC 812 is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors having an effect on power/ thermal behavior of the system/platform” par 0109).
Regarding claim 8, Lake and Garag teach the apparatus of claim 1. Lake further teaches wherein when the processor enters the low power state, the EC is to obtain external temperature data, external to the chip package, and determine whether the activity of the processor is inconsistent with the low power state based on the external temperature data (“temperature measurement circuitries 840 may measure temperature of … a mother-board of SOC 801, and/or any appropriate component of device 800.” Par 0099 and “PCU 810 and/or PMIC 812 may perform power management operations, e.g., based at least in part on receiving measurements from … temperature measurement circuitries 840 … PMIC 812 is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors … factors include …temperature” par 0109).
Regarding claim 10, Lake and Garag teach the apparatus of claim 1. Lake further teaches wherein when the processor enters the low power state, the EC receives a notification from a basic input output system (BIOS) of the processor and initiates the obtaining of the count from each counter of the one or more counters in response to the notification (“one or more of PM applications 858, 856, drivers 854, BIOS 820, etc. may be used to implement power management specific tasks, e.g., to control … various components of device 800,” par 0111 and “μC 512 receives another signal 522 which specifies or otherwise indicates that CPU 514 has entered a local power state” par 0068 and “μC 512 generates a control signal 524 to start a timer circuit” par 0069) [the BIOS implements power management tasks and controls the power states; the EC receives the transition signals to start the counters].
Regarding claim 11, Lake teaches an apparatus, comprising:
a processor (Figure 3, processor unit 350);
one or more counters (Figure 3, timers 390), wherein each counter of the one or more counters is to provide a count which represents a portion of a time period in which a respective subsystem of one or more subsystems is idle (“monitor 380 is coupled to (or alternatively, includes) one or more timers 390 which are each operable to count or otherwise track the running of a respective limited period of time.” Par 0056 and “Based on such operation of the one or more timers 390, monitor 380 detects whether a duration of a power state, and/or a duration of an attempted power state transition, exceeds a predetermined time limit.” Par 0057); and
wherein the apparatus is to notify the EC via the SPI bus when the processor enters a low power state (“μC 512 receives another signal 522 which specifies or otherwise indicates that CPU 514 has entered a local power state (in this example, a C10 power state)” par 0068 and “Interconnect circuitry 320 includes any of a variety of one or more busses … and/or other connection mechanisms to variously couple one or more devices of SOC 300 to PMC 310.” Par 0048 and Figures 3 and 5 and Figure 8, connectivity circuitries 831) [the microcontroller receives a status signal via the busses when the processor enters low power mode].
However, Lake does not explicitly teach a pin coupled to a serial peripheral interface (SPI) bus to communicate with an embedded controller (EC), and to transmit the count from each counter of the one or more counters to the EC via the SPI bus in response to a request from the EC via the SPI bus.
In the analogous art, Garg teaches a pin coupled to a serial peripheral interface (SPI) bus to communicate with an embedded controller (EC) (“Also seen in FIG. 14, various peripheral devices may couple to processor 1410 via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller 1435.” Par 0108 and “communications may be via a variety of communication protocols such as … SPI, HDMI, among other types of communication protocols” par 0081 and Figure 14), and to transmit the count from each counter of the one or more counters to the EC via the SPI bus in response to a request from the EC via the SPI bus (“the power controller is to communicate at least some of the telemetry information to the management controller.” Par 0184 “telemetry data control logic 2050 may be configured to maintain telemetry data, e.g., associated with a plurality of different counter types, such as one or more core activity counters, one or more core inactivity counters and so forth.” Par 0141) [controller provides counter data to EC].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lake and Garg before him before the effective filing date of the claimed invention, to have modified Lake to incorporate the teachings of Garg to incorporate a pin connected to the SPI bus to communicate with the EC for high speed data transfer and low latency.
Regarding claim 12, Lake and Garg teach the apparatus of claim 11. Lake further teaches wherein the processor is on a system-on-a-chip (SoC) (Figure 3, SoC 300), and the SoC is to notify the EC via the SPI bus when the processor enters the low power state (“μC 512 receives another signal 522 which specifies or otherwise indicates that CPU 514 has entered a local power state (in this example, a C10 power state)” par 0068 and “Interconnect circuitry 320 includes any of a variety of one or more busses … and/or other connection mechanisms to variously couple one or more devices of SOC 300 to PMC 310.” Par 0048 and Figures 3 and 5 and Figure 8, connectivity circuitries 831) [the microcontroller receives a status signal via the busses when the processor enters low power mode].
Garg further teaches to transmit the count from each counter of the one or more counters to the EC via the SPI bus in response to the request from the EC via the SPI bus (“the power controller is to communicate at least some of the telemetry information to the management controller.” Par 0184 “telemetry data control logic 2050 may be configured to maintain telemetry data, e.g., associated with a plurality of different counter types, such as one or more core activity counters, one or more core inactivity counters and so forth.” Par 0141) [controller provides counter data to EC].
Regarding claim 13, Lake and Garg teach the apparatus of claim 11. Garg further teaches further comprising another pin to transmit a signal to a voltage regulator when the processor enters the low power state, wherein the another pin is not coupled to the EC (“PUC 138 provides control information to external voltage regulator 160 via a digital interface 162 to cause the voltage regulator to generate the appropriate regulated voltage. PCU 138 also provides control information to IVRs 125 via another digital interface 163 to control the operating voltage generated (or to cause a corresponding IVR to be disabled in a low power mode).” Par 0030 and Figure 1) [the digital interface corresponds to the pins; this path is distinct from the LPC based EC].
Regarding claim 14, Lake and Garg teach the apparatus of claim 11. Garg further teaches further comprising other pins to transmit a C10 signal and an SLP_S0# signal to a voltage regulator (“PCU 138 provides control information to external voltage regulator 160 via a digital interface 162 to cause the voltage regulator to generate the appropriate regulated voltage.” Par 0030) and the other pins are not coupled to the EC (“various peripheral devices may couple to processor 1410 via a low pin count (LPC) interconnect…various components can be coupled through an embedded controller 1435.” Par 0108).
Lake further teaches wherein the C10 signal indicates whether the processor is in the low power state (“μC 512 receives another signal 522 which specifies or otherwise indicates that CPU 514 has entered a local power state (in this example, a C10 power state)” par 0068), the SLP_S0# signal indicates whether a platform of the processor is in the low power state (“During the one or more attempts to transition the power domain to the LPS, signals 144 communicate to controller logic 140 various operational conditions of the power domain —e.g., wherein signals 144 indicate a current power state of the power domain” par 0035).
Regarding claim 15, Lake and Garg teach the apparatus of claim 11. Lake further teaches further comprising a temperature sensor for the processor, wherein the apparatus is to transmit temperature data from the temperature sensor to the EC via the SPI bus in response to a request for the temperature data from the EC via the SPI bus (“device 800 comprises temperature measurement circuitries 840, e.g., for measuring temperature of various components of device 800. In an example, temperature measurement circuitries 840 may be embedded, or coupled or attached to various components, whose temperature are to be measured and monitored. For example, temperature measurement circuitries 840 may measure temperature of (or within) one or more of cores 808 a, 808 b, 808 c, voltage regulator 814, memory 830, a mother-board of SOC 801, and/or any appropriate component of device 800.” Par 0099 and “PCU 810 and/or PMIC 812 may perform power management operations, e.g., based at least in part on receiving measurements from … temperature measurement circuitries 840,” par 0109).
Regarding claim 16, Lake and Garg the apparatus of claim 11. Lake further teaches wherein the apparatus comprises a chip package (Figure 8, SoC 801).
Regarding claim 17, Lake teaches an embedded controller (EC) (Figure 8, PMIC 812; Figure 5, microcontroller 512), comprising:
a second pin coupled to a fuel gauge of a battery (“PCU 810 and/or PMIC 812 may perform power management operations, e.g., based at least in part on receiving measurements from … charge level of battery 818, and/or any other appropriate information that may be used for power management … PMIC 812 is communicatively coupled to one or more sensors to sense/detect various values/variations … Examples of the one or more factors include electrical current, voltage droop, temperature … power consumption,” Par 0109) [the PMIC is coupled via hardware interface (second pin) to sensors that monitor battery’s charge level and current, corresponding to the battery’s fuel gauge]; and
a microcontroller coupled to the first pin and the second pin (Figure 1, controller logic is connected to hardware interface that send and receive signals, 142, 144), wherein the microcontroller, in response to the message, is to determine a discharge rate of the battery and determine based on the discharge rate of the battery whether the processor is in an anomalous low power state (“μC 512 receives another signal 522 which specifies or otherwise indicates that CPU 514 has entered a local power state (in this example, a C10 power state)” par 0068 and “Based on signals 520, 522, μC 512 generates a control signal 524 to start a timer circuit” par 0069 and “The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time.” Abstract and “PCU 810 and/or PMIC 812 may perform power management operations, e.g., based at least in part on receiving measurements from … charge level of battery 818, … PMIC 812 is communicatively coupled to one or more sensors to sense/detect various values/variations … Examples of the one or more factors include electrical current,” par 0109 and Figures 1, 5, 9) [battery’s charge level and electrical current are used to determine anomalous low power state].
However, Lake does not explicitly teach a first pin coupled to a serial peripheral interface (SPI) bus to receive a message from a chip package when a processor of the chip package enters a low power state.
In the analogous art, Garg teaches a first pin coupled to a serial peripheral interface (SPI) bus to receive a message from a chip package when a processor of the chip package enters a low power state (“Also seen in FIG. 14, various peripheral devices may couple to processor 1410 via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller 1435.” Par 0108 and “communications may be via a variety of communication protocols such as … SPI, HDMI, among other types of communication protocols” par 0081 and “the power controller is to communicate at least some of the telemetry information to the management controller.” Par 0184 and “To avoid losing such data, responsive to receipt of this low power state request, the telemetry data may be sent” par 0156 and Figure 14).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lake and Garg before him before the effective filing date of the claimed invention, to have modified Lake to incorporate the teachings of Garg to incorporate a pin connected to the SPI bus to communicate with the EC for high speed data transfer and low latency.
Regarding claim 18, Lake and Garg teach the EC of claim 17. Lake further teaches to determine based on the idle state residency data whether the processor is in the anomalous low power state (“The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time.” Abstract and “In some embodiments, circuitry of PMC 310… generates analytic information based on the monitored one or more attempts by the power domain to enter the LPS. In one such embodiment, the analytic information specifies or otherwise indicates a duration of an instance of power domain being in the LPS, a duration of an instance of power domain being in a power state other than the LPS, and/or the like.” Par 0059) [PMC uses analytic information for the duration spend in a state (residency data) to determine if system is in anomalous low power state].
Garg further teacheswherein in response to the message, the microcontroller is to request idle state residency data from the chip package via the SPI bus for one or more subsystems (“PCU 138 may control communication of telemetry data from cores 120 and other logic” par 0030 and “ PCU 138 may be implemented as a microcontroller” par 0031 and “Examples of fast telemetry data may include, in an embodiment C0 residency [idle state residency], instructions retired, and so forth.” Par 0146 and “SoC 900 may further include a non-coherent fabric coupled to the coherent fabric to which various peripheral devices may couple. … Such communications may be via a variety of communication protocols such as … SPI,” par 0081).
Regarding claim 19, Lake and Garg teach the EC of claim 17. Lake further teaches wherein in response to the message, the microcontroller is to request internal temperature data from the chip package via the SPI bus, and to determine based on the internal temperature data whether the processor is in the anomalous low power state (“temperature measurement circuitries 840 may measure temperature of (or within) one or more of cores 808 a, 808 b, 808 c,” Par 0099 and “Interconnect circuitry 320 includes any of a variety of one or more busses … and/or other connection mechanisms to variously couple one or more devices of SOC 300 to PMC 310.” Par 0048 and “PMIC 812 is communicatively coupled to one or more sensors … sensor(s) may be directly coupled to PCU 810 and/or PMIC 812 in at least one embodiment to allow PCU 810 and/or PMIC 812 to manage processor core energy at least in part based on value(s) detected by one or more of the sensors… Examples of the one or more factors include … temperature…PMIC 812 is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors having an effect on power/ thermal behavior of the system/platform” par 0109).
Claims 4, 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lake and Garg in view of Scherr (US 2019/0227896 A1).
Regarding claim 4, Lake and Garg teach the apparatus of claim 1. However, Lake and Garg do not explicitly teach wherein when the EC determines that the activity of the processor is inconsistent with the low power state, the EC is to initiate a fail safe mode for the apparatus.
In the analogous art, Scherr teaches wherein when the EC determines that the activity of the processor is inconsistent with the low power state, the EC is to initiate a fail safe mode for the apparatus (“if the counter value is greater than or equal to the threshold, then this may indicate that the bus 102 has been active for a threshold amount of time, which may indicate that the bus 102 is stalled.” Par 0034 and “the monitoring device 402 may perform one or more actions to recover the stalled bus 102 when the comparison signal indicates that the bus 102 is stalled. For example, the monitoring device 402 may reset the device 108 (e.g., by powering off the device 108 and powering the device 108 back on within a threshold time period), may disable the device 108 (e.g., by powering off a device 108 without powering the device 108 back on within the threshold time period),” par 0036) [these corrective actions correspond to a fail safe mode].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lake, Garg and Scherr before him before the effective filing date of the claimed invention, to have modified Lake and Garg to incorporate the teachings of Scherr to include a fail safe mode to increase the flexibility and usefulness of the monitoring device and reduce design costs. (Scherr, paragraph 40)
Regarding claim 5, Lake, Garg and Scherr teach the apparatus of claim 4. Scherr further teaches wherein the fail safe mode comprises a suspend, shutdown or restart of the apparatus (“the action includes at least one of: performing one or more diagnostic tests on the device 108, resetting the device 108, disabling the device 108, resetting the one or more drivers of the device 108, disabling the one or more drivers of the device 108, or some combination thereof.” Par 0050).
Regarding claim 20, Lake and Garg teach the EC of claim 17. However, Lake and Garg do not explicitly teach wherein the microcontroller is to transmit a message to the chip package via the SPI bus to suspend, restart or shutdown the processor when the processor is in the anomalous low power state.
In the analogous art, Scherr teaches wherein the microcontroller is to transmit a message to the chip package via the SPI bus to suspend, restart or shutdown the processor when the processor is in the anomalous low power state (“if the counter value is greater than or equal to the threshold, then this may indicate that the bus 102 has been active for a threshold amount of time, which may indicate that the bus 102 is stalled.” Par 0034 and “the monitoring device 402 may perform one or more actions to recover the stalled bus 102 when the comparison signal indicates that the bus 102 is stalled. For example, the monitoring device 402 may reset the device 108 (e.g., by powering off the device 108 and powering the device 108 back on within a threshold time period), may disable the device 108 (e.g., by powering off a device 108 without powering the device 108 back on within the threshold time period),” par 0036 and “the action includes at least one of: … resetting the device 108, disabling the device 108, resetting the one or more drivers of the device 108, disabling the one or more drivers of the device 108, or some combination thereof.” Par 0050 and Figure 4, “the system 100 may include … a serial peripheral interface (SPI),” par 0029 and par 35) [the comparison signal corresponds to the message].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lake, Garg and Scherr before him before the effective filing date of the claimed invention, to have modified Lake and Garg to incorporate the teachings of Scherr to suspend, restart, or shut down the processor in response to an anomalous low power state to reduce power consumption. This fail safe mode increases the flexibility and usefulness of the monitoring device and reduces design costs. (Scherr, paragraph 40)
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lake and Garg in view of Aqrabawi et al. (US 2021/0349519 A1).
Regarding claim 6, Lake and Garg teach the apparatus of claim 1. However, Lake and Garg do not explicitly teach wherein the low power state comprises a deep idle state.
In the analogous art, Aqrabawi teaches wherein the low power state comprises a deep idle state (“S0i4 is a deeper sleep state compared to S0i3… In the deepest power state (e.g., S0i4), the SoC consumes the least amount of power.” Par 0011) [S0i4 corresponds to a deep idle state].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lake, Garg and Aqrabawi before him before the effective filing date of the claimed invention, to have modified Lake and Garg to incorporate the teachings of Aqrabawi to have a deep idle state to conserve power during power state transitions.
Regarding claim 9, Lake and Garg teach the apparatus of claim 1. However, Lake and Garg do not explicitly teach wherein the processor is powered by a battery, and when the processor enters the low power state, the EC is to determine a discharge rate of the battery, and determine whether the activity of the processor is inconsistent with the low power state based on whether the discharge rate of the battery exceeds a threshold.
In the analogous art, Aqrabawi teaches wherein the processor is powered by a battery (“battery 2418 is illustrated to be supplying power to processor 2404.” Par 0082), and when the processor enters the low power state, the EC is to determine a discharge rate of the battery (“At block 301, system telemetry logic 203 gathers telemetry information from various sources … battery information (e.g., charging and/or discharging patterns)” par 0041), and determine whether the activity of the processor is inconsistent with the low power state based on whether the discharge rate of the battery exceeds a threshold (“The ML creates a High Water Mark (HWM) number of dirty cache lines as a hint to Power Management Unit 101 a to decide which power state to enter (e.g., SiO3 or SiO4)… to inform the low power state entry decision… based on the telemetry information, the ML scheme predicts an idle duration for SoC 101 and, then depending of that duration, puts the SoC 101 in a sleep mode” Par 0028 and “ HWM 205 indicates a threshold level or count of dirty cache lines that dictates whether SoC 101 should enter a particular power state.” Par 0037).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Lake, Garg and Aqrabawi before him before the effective filing date of the claimed invention, to have modified Lake and Garg to incorporate the teachings of Aqrabawi to determine whether the processor is in an anomalous low power state based on the discharge rate of the battery to predict user behavior and train the ML model to choose the best course of corrective action (e.g. modern standby) and increase product reliability.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Hsia et al. (US 2023/0114256 A1) teaches a standby mode in a computing device. While in standby mode, a controller monitors a power source’s remaining capacity. If the capacity is below a threshold, the controller modifies a feature of the computing device.
Verdun (US 2007/0050653 A1) teaches power management of an IHS that dynamically adjusts idle time at a bus before entering low power mode by determining previous patterns of transitions between low and operating power states. See Figure 2.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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