DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-8 and 10-22 are pending. Claim 9 is canceled. Claims 1-4, 7-8, and 10-15 are amended. Claims 5-6 are original. Claims 16-22 are new.
Terminal Disclaimer
The terminal disclaimer filed on 10/28/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent 11,695,283 has been reviewed and is accepted. The terminal disclaimer has been recorded. The rejection of claims 1 and 7-15 on the ground of nonstatutory double patenting is rendered moot.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 7, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The indicated allowability of claims 1-15 is withdrawn in view the amendments to independent claims 1 and 7, and in view of the newly discovered reference(s) LI (US Pub. No. 2020/0153261). Rejections based on the newly cited reference(s) follow.
Drawings
The drawings were received on 10/28/2025. These drawings are acceptable.
Claim Objections
Claims 1, 8, and 20 are objected to because of the following informalities:
In claim 1, lines 1-2, “a first voltage at an input voltage terminal to a threshold” should be changed to --the first voltage at the input voltage terminal to the threshold --.
In claim 8, line 2, “a threshold” should be changed to --the threshold--.
In claim 20, line 4, --to-- should be inserted after “configurable”.
In claim 20, line 4, “an input voltage terminal” should be changed to --the input terminal--.
In claim 20, line 6, “a battery terminal” should be changed to --the battery terminal--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-8, 10-11, 17, and 19-21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LI (US Pub. No. 2020/0153261).
Regarding claim 1, LI discloses a method, comprising:
receiving a request to enter a low-power mode (¶ 0002: MCU 108 can also instruct the control circuit 102 to turn off both the switches QCHG and QDSG such that the battery pack 100 enters into a deep sleep mode or a low-power mode in which the power can be saved; ¶ 0037: logic circuit 520 can also generate an interrupt signal 530 to inform a controller (e.g., similar to the controller 208) of the over-heavy status of the load 550. In response to the interrupt signal 530, the controller can instruct the control circuit 502 to turn off the discharge switch QDSG or reduce the load 550);
comparing a first voltage (VPP, Fig. 5) at an input voltage terminal (248, Fig. 5) to a threshold (¶ 0036: if the voltage VPP [decreases] to a level such that the voltage difference VBP−VPP is greater than the voltage reference VSC, then it indicates that the load 550 is in the over-heavy status);
comparing a second voltage (VCP, Fig. 5) at a power middle terminal (246, Fig. 5) to a third voltage (VBP + VTH1) at a battery terminal (the “-” terminal of comparator 426 in Figure 5 is the “battery terminal”; ¶ 0032: the multiplexer 434 provides the input voltage VCP to the comparator 426. The reference generator 424 receives a first signal VBP indicative of a voltage of the battery 238 and generates a second signal indicative of a combination of the first signal VBP and the voltage reference VTH1. In one embodiment, similar to the combination signal described in relation to FIG. 2, the second signal has a voltage level of VBP + VTH1. Similar to the comparator 226 described in relation to FIG. 2, the comparator 426 compares the second signal VBP + VTH1 with the input voltage VCP to generate a comparison result 428 indicative of whether a charger/adapter is connected to the interface PACK±. If the logic circuit 420 detects that the input voltage VCP is greater than the second signal VBP + VTH1, i.e., VCP − VBP > VTH1, for a predefined time interval ΔT1, then the logic circuit 420 determines that a charger/adapter is connected to the interface PACK±); and
entering the low-power mode responsive to the first voltage being lower than the threshold (¶ 0036: see above; ¶ 0027: during discharging of the battery 238, if an over-heavy/short-circuit load condition is detected, then the control circuit 302 disables the discharge switch QDSG to stop the discharging; ¶ 0037: logic circuit 520 can also generate an interrupt signal 530 to inform a controller (e.g., similar to the controller 208) of the over-heavy status of the load 550. In response to the interrupt signal 530, the controller can instruct the control circuit 502 to turn off the discharge switch QDSG or reduce the load 550) and the second voltage being lower than the third voltage (the “low power-mode” occurs during discharging, said discharging occurs when the charger/adapter is not connected, and as such the second voltage VCP would be lower than the third voltage “VBP + VTH1” as described in ¶ 0032)
Regarding claim 2, LI discloses disconnecting the input voltage terminal from the power middle terminal and disconnecting the power middle terminal from the battery terminal responsive to entering the low-power mode (¶ 0020, 0025, 0027, 0035, 0037).
Regarding claim 3, LI discloses disconnecting the input voltage terminal from the power middle terminal and disconnecting the power middle terminal from the battery terminal includes controlling one or more transistors to enter a non-conductive state (¶ 0020, 0025, 0027, 0035, 0037).
Regarding claim 4, LI discloses comparing a first voltage at an input voltage terminal to a threshold includes comparing the first voltage to the threshold using a first comparator, and wherein comparing a second voltage at a power middle terminal to a third voltage at a battery terminal includes comparing the second voltage to the third voltage using a second comparator (¶ 0032-0033).
Regarding claim 5, LI discloses the request to enter the low-power mode is generated based on input received from a user (¶ 0017, 0026: connecting or removing of the load implies a user).
Regarding claim 7, LI discloses a method comprising:
receiving a request to enter a ship mode or a low power mode (¶ 0002: MCU 108 can also instruct the control circuit 102 to turn off both the switches QCHG and QDSG such that the battery pack 100 enters into a deep sleep mode or a low-power mode in which the power can be saved; ¶ 0037: logic circuit 520 can also generate an interrupt signal 530 to inform a controller (e.g., similar to the controller 208) of the over-heavy status of the load 550. In response to the interrupt signal 530, the controller can instruct the control circuit 502 to turn off the discharge switch QDSG or reduce the load 550); and
entering the ship mode or the low power mode responsive to: receiving the request (¶ 0037: see above), a first voltage (VPP, Fig. 5) at an input voltage terminal (248, Fig. 5) being lower than a threshold (¶ 0036: if the voltage VPP deceases to a level such that the voltage difference VBP−VPP is greater than the voltage reference VSC, then it indicates that the load 550 is in the over-heavy status; ¶ 0027: during discharging of the battery 238, if an over-heavy/short-circuit load condition is detected, then the control circuit 302 disables the discharge switch QDSG to stop the discharging; ¶ 0037: logic circuit 520 can also generate an interrupt signal 530 to inform a controller (e.g., similar to the controller 208) of the over-heavy status of the load 550. In response to the interrupt signal 530, the controller can instruct the control circuit 502 to turn off the discharge switch QDSG or reduce the load 550), and a second voltage (VCP, Fig. 5) at a power middle terminal (246, Fig. 5) being lower than a third voltage (VBP + VTH1) at a battery terminal (the “-” terminal of comparator 426 in Figure 5 is the “battery terminal”; ¶ 0032: the multiplexer 434 provides the input voltage VCP to the comparator 426. The reference generator 424 receives a first signal VBP indicative of a voltage of the battery 238 and generates a second signal indicative of a combination of the first signal VBP and the voltage reference VTH1. In one embodiment, similar to the combination signal described in relation to FIG. 2, the second signal has a voltage level of VBP + VTH1. Similar to the comparator 226 described in relation to FIG. 2, the comparator 426 compares the second signal VBP + VTH1 with the input voltage VCP to generate a comparison result 428 indicative of whether a charger/adapter is connected to the interface PACK±. If the logic circuit 420 detects that the input voltage VCP is greater than the second signal VBP + VTH1, i.e., VCP − VBP > VTH1, for a predefined time interval ΔT1, then the logic circuit 420 determines that a charger/adapter is connected to the interface PACK±; the “low power-mode” occurs during discharging, said discharging occurs when the charger/adapter is not connected, and as such the second voltage VCP would be lower than the third voltage “VBP + VTH1” as described in ¶ 0032).
Regarding claim 8, LI discloses comparing the first voltage to a threshold using a first comparator and comparing the second and third voltages using a second comparator (¶ 0032-0033).
Regarding claim 10, LI discloses disconnecting the input voltage terminal from the power middle terminal and disconnecting the power middle terminal from the battery terminal responsive to entering the ship mode or the low power mode (¶ 0020, 0025, 0027, 0035, 0037).
Regarding claim 11, LI discloses disconnecting the input voltage terminal from the power middle terminal includes disabling a first transistor and a second transistor (¶ 0020, 0025, 0027, 0035, 0037).
Regarding claim 17, LI discloses not entering the ship mode or the low power mode responsive to the first voltage being equal to or higher than the threshold, or the second voltage being equal to or higher than the third voltage (¶ 0027, 0032, 0037).
Regarding claim 19, LI discloses not entering the low-power mode responsive to either the first voltage being higher than or equal to the threshold or the second voltage being higher than or equal to the third voltage (¶ 0027, 0032, 0037).
Regarding claim 20, LI discloses an apparatus comprising:
a first switch (QDSG, Fig. 5) coupled between an input terminal (248, Fig. 5) and a middle terminal (246);
a second switch (QCHG) coupled between the middle terminal (246) and a battery terminal (244);
a control circuit (502, Fig. 5) configurable, responsive to a first voltage (VPP) at an input voltage terminal (248, Fig. 5) being lower than a threshold (¶ 0036: if the voltage VPP deceases to a level such that the voltage difference VBP−VPP is greater than the voltage reference VSC, then it indicates that the load 550 is in the over-heavy status; ¶ 0027: during discharging of the battery 238, if an over-heavy/short-circuit load condition is detected, then the control circuit 302 disables the discharge switch QDSG to stop the discharging; ¶ 0037: logic circuit 520 can also generate an interrupt signal 530 to inform a controller (e.g., similar to the controller 208) of the over-heavy status of the load 550. In response to the interrupt signal 530, the controller can instruct the control circuit 502 to turn off the discharge switch QDSG or reduce the load 550), and a second voltage (VCP, Fig. 5) at the middle terminal (246, Fig. 5) being lower than a third voltage (VBP + VTH1) at a battery terminal (the “-” terminal of comparator 426 in Figure 5 is the “battery terminal”; ¶ 0032: the multiplexer 434 provides the input voltage VCP to the comparator 426. The reference generator 424 receives a first signal VBP indicative of a voltage of the battery 238 and generates a second signal indicative of a combination of the first signal VBP and the voltage reference VTH1. In one embodiment, similar to the combination signal described in relation to FIG. 2, the second signal has a voltage level of VBP + VTH1. Similar to the comparator 226 described in relation to FIG. 2, the comparator 426 compares the second signal VBP + VTH1 with the input voltage VCP to generate a comparison result 428 indicative of whether a charger/adapter is connected to the interface PACK±. If the logic circuit 420 detects that the input voltage VCP is greater than the second signal VBP + VTH1, i.e., VCP − VBP > VTH1, for a predefined time interval ΔT1, then the logic circuit 420 determines that a charger/adapter is connected to the interface PACK±; the “low power-mode” occurs during discharging, said discharging occurs when the charger/adapter is not connected, and as such the second voltage VCP would be lower than the third voltage “VBP + VTH1” as described in ¶ 0032), disable the first and second switches (¶ 0035: during discharging, the switch circuit QCHG & QDSG is turned on (e.g., at least the discharge switch QDSG is turned on); during discharge, QCHG remains disabled; ¶ 0037: logic circuit 520 can also generate an interrupt signal 530 to inform a controller (e.g., similar to the controller 208) of the over-heavy status of the load 550. In response to the interrupt signal 530, the controller can instruct the control circuit 502 to turn off the discharge switch QDSG or reduce the load 550).
Regarding claim 21, LI discloses the control circuit is configurable to disable the first and second switches responsive to receiving a request to enter a ship mode or a low power mode (¶ 0020, 0025, 0027, 0035, 0037).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI.
Regarding claim 6, LI discloses the method as applied to claim 3, but fails to disclose the transistors being controlled are field effect transistors (FETs).
Official notice is taken that field effect transistors were an old and known expedient in the art at the time of the invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the field effect transistors into the method of LI to produce an expected result of a method including the use of field effect transistors. The modification would be obvious because one of ordinary skill in the art would be motivated to utilize the known switching characteristics of field effect transistors.
Regarding claim 12, LI discloses the method as applied to claim 11, but fails to disclose each of the first and second transistors being an n-type field effect transistors (nFETs).
Official notice is taken that n-type field effect transistors were an old and known expedient in the art at the time of the invention.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the n-type field effect transistors into the method of LI to produce an expected result of a method including the use of n-type field effect transistors. The modification would be obvious because one of ordinary skill in the art would be motivated to utilize the known switching characteristics of n-type field effect transistors.
Regarding claim 13, LI discloses disconnecting the power middle terminal from the battery terminal responsive to entering the ship mode or the low power mode (¶ 0020, 0025, 0027, 0035, 0037).
Claim(s) 14-15 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI as applied to claims 1-5, 6-8, 10-13, 17, and 19-21 above, and further in view of KITANO (US Pub. No. 2010/0194352).
Regarding claim 14, LI discloses the method as applied to claim 13 but fails to disclose disconnecting the power middle terminal from the battery terminal includes disabling a third transistor.
KITANO discloses disconnecting the power middle terminal (Pb, Fig. 4) from the battery terminal (Pa, Fig. 4) includes disabling a third transistor (SW3, Fig. 4; ¶ 0025, 0047-0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the third transistor of KITANO into the method of LI to produce an expected result of a method including a third transistor. The modification would be obvious because one of ordinary skill in the art would be motivated to enable greater control of the connections and current flow between the input voltage terminal, the power middle terminal, and the battery terminal.
Regarding claim 15, LI as modified by KITANO discloses the third transistor is a p-type field effect transistor (pFET) (KITANO, ¶ 0047).
Regarding claim 22, LI discloses the apparatus as applied to claim 20, but fails to disclose the first switch includes a first NFET and a second NFET, and the second switch includes a PFET.
KITANO discloses the first switch includes a first [MOSFET] (SW1, Fig. 4) and a second [MOSFET] (SW2, Fig. 4), and the second switch includes a PFET (SW3, Fig. 4; ¶ 0024-0025, 0047-0048).
Official notice is taken that “NFET” switches (N-channel Field-Effect Transistors) were an old and known expedient in the art at the time of the invention. One of ordinary skill would recognize how to implement the first and second switches as NFETs, which would not provide any new functionality, or new or unexpected results.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the first switch includes a first NFET and a second NFET, and the second switch includes a PFET into the apparatus of LI to produce an expected result of an apparatus comprising a first NFET, a second NFET, and a PFET. The modification would be obvious because one of ordinary skill in the art would be motivated to enable greater control of the connections and current flow between the input terminal, the middle terminal, and the battery terminal.
Claim(s) 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI as applied to claims 1-5, 7-8, 10-11, 17, and 19-21 above, and further in view of ESNARD (US 2010/0109765; cited on PTO-892 with date 5/28/2025).
Regarding claim 16, LI discloses the method as applied to claim 7, but fails to disclose the threshold is a under voltage lockout threshold.
ESNARD discloses the threshold is a under voltage lockout threshold (¶ 0077, 0080, 0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the threshold is a under voltage lockout threshold of ESNARD into the method of LI to produce an expected result of a method including an under voltage lockout threshold. The modification would be obvious because one of ordinary skill in the art would be motivated to enable the low power mode without physical interfaces or the need for manual interaction (ESNARD, ¶ 0009).
Regarding claim 18, LI discloses the method as applied to claim 1, but fails to disclose the threshold is a under voltage lockout threshold.
ESNARD discloses the threshold is a under voltage lockout threshold (¶ 0077, 0080, 0085).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the threshold is a under voltage lockout threshold of ESNARD into the method of LI to produce an expected result of a method including an under voltage lockout threshold. The modification would be obvious because one of ordinary skill in the art would be motivated to enable the low power mode without physical interfaces or the need for manual interaction (ESNARD, ¶ 0009).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANUEL HERNANDEZ whose telephone number is (571)270-7916. The examiner can normally be reached Monday-Friday 9a-5p ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Manuel Hernandez/Examiner, Art Unit 2859 2/12/2026
/DREW A DUNN/Supervisory Patent Examiner, Art Unit 2859