DETAILED ACTION
Claims 1-20 have been examined.
This office action is in response to the communication filed on September 4, 2025.
This office action is made Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 5-10 of Remarks, filed 5/16/25, with respect to the rejection(s) of claim(s) under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1,5,8,14,15,16, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,10, 13, and 24 of U.S. Patent No. 11,645,135. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the claims of U.S. Patent No. 11,645,135 contains, as thus anticipates, the limitations of claims of the instant application.
Instant Application
US Patent No. 11645135
1. (Original) A processor comprising: decode circuitry to decode a load instruction, the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value; and
1. A processor comprising: decode circuitry to decode a load instruction, the load instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [59:56]; and
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
determine whether the first value matches a second value corresponding to the block of data; and
determine whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data;
load the block of data from the memory when the first value matches the second value.
load the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory;
5. (Original) The processor of claim 1, further comprising a configuration register to store data to control whether the circuitry is to determine whether the first value matches the second value.
10. The processor of claim 1, further comprising a register to control whether the circuitry is to determine whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data.
8. (Original) The processor of claim 1, wherein the first value does not include a most significant bit of the pointer.
1. … the 64-bit pointer comprising ... a 4-bit value in bits [59:56];
14. (Original) The processor of claim 1, wherein the block of data is a 128-bit block of data.
1. ... an address to a 128-bit block of data in memory ...; and
15. (Original) The processor of claim 1, wherein the processor is to indicate if the first value does not match the second value.
1. ... and generate a fault when the 4-bit value from the 64-bit pointer does not match the 4-bit value from the memory.
16. (Original) A computer system comprising: a dynamic random access memory (DRAM); a processor coupled with the DRAM, the processor comprising: decode circuitry to decode a load instruction, the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value; and
24. A computer system comprising: a dynamic random access memory (DRAM); and a processor coupled with the DRAM, the processor comprising: decode circuitry to decode a load instruction, the load instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [59:56];
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
determine whether the first value matches a second value corresponding to the block of data; and
determine whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data;
load the block of data from the memory when the first value matches the second value.
load the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory;
20. (Original) A method comprising: decoding a load instruction, the load instruction operating on a pointer, the pointer comprising an address to a block of data in memory and a first value;
13. A method comprising: decoding a load instruction, the load instruction operating on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [59:56]; and based on the decode of the load instruction:
determining whether the first value matches a second value corresponding to the block of data; and
determining whether the 4-bit value from the 64-bit pointer matches a 4-bit value from the memory corresponding to the 128-bit block of data;
loading the block of data from the memory when the first value matches the second value.
loading the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value from the memory;
Claims 9-13 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,12, 24, and 26 of U.S. Patent No. 11,645,135 in view of Radovic et al. (US 2013/0013843).
Regarding claim 9, claim 1 of U.S. Patent 11,645,135 discloses process of claim 1. However, claim 1 of U.S. Patent 11,645,135 fails to disclose;
wherein the most significant bit of the pointer is to have a value of one for an operating system.
Radovic teaches wherein the most significant bit of the pointer is to have a value of one for an operating system ([0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of U.S. Patent 11,645,135 and Radovic wherein the most significant bit of the pointer is to have a value of one for an operating system. A person of ordinary skill in the art could have been motivated to combine the teachings as it is known various combinations are possible and other or additional bits may be utilized as well (Radovic [0040])
Regarding claim 10, claim 1 of U.S. Patent 11,645,135 discloses process of claim 1. However, claim 1 of U.S. Patent 11,645,135 fails to disclose;
wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value.
Radovic teaches wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value ([0042] “In such a case, the most-significant bits of an associated virtual address may comprise binary 0s”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of U.S. Patent 11,645,135 and Radovic wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value. A person of ordinary skill in the art could have been motivated to combine the teachings as it is a known configuration (Radovic [0042]).
Regarding claim 11, claim 1 of U.S. Patent 11,645,135 discloses process of claim 1. However, claim 1 of U.S. Patent 11,645,135 fails to disclose;
wherein the first value comprises a most significant bit of the pointer.
Radovic teaches wherein the first value comprises a most significant bit of the pointer ([0040], [0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of U.S. Patent 11,645,135 and Radovic wherein the first value comprises a most significant bit of the pointer. A person of ordinary skill in the art could have been motivated to combine the teachings as it is known various combinations are possible and other or additional bits may be utilized as well (Radovic [0040])
Regarding claim 12, claim 1 of U.S. Patent 11,645,135 discloses process of claim 1. Claim 12 of U.S. Patent 11,645,135 further discloses wherein the processor is a reduced instruction set computing (RISC) processor (12. The processor of claim 1, wherein the processor is a reduced instruction set computing (RISC) processor).
However, claims of U.S. Patent 11,645,135 fails to disclose;
wherein the first value comprises five bits.
Radovic teaches wherein the first value comprises five bits ([0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of U.S. Patent 11,645,135 and Radovic wherein the first value comprises five bits. A person of ordinary skill in the art could have been motivated to combine the teachings as it is known various combinations are possible and other or additional bits may be utilized as well (Radovic [0040])
Regarding claim 13, Radovic further teaches wherein the first value comprises ten bits ([0031] “As used herein, ‘version bits’ generally refers to one or more bits used as a tag or identifier”; [0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
Regarding claim 19, claim 24 of U.S. Patent 11,645,135 discloses computer system of claim 16. Claim 26 of U.S. Patent 11,645,135 further discloses wherein the computer system further comprises a communication device coupled with the processor (26. The computer system of claim 25, wherein the computer system further comprises a communication device coupled with the processor). The remaining limitations are similar to limitations recited in claims 10 and 12 and rejected under the same rationale.
Claims 1,8,14,15, and 20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 7 of copending Application No. 19/004156. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the claims of U.S. Patent No. 11,645,135 contains, as thus anticipates, the limitations of claims of the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application
US Patent Application 19/004156
1. (Original) A processor comprising: decode circuitry to decode a load instruction, the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value; and
1. A processor comprising: first circuitry to decode an instruction, the instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [60:57]; and
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
second circuitry coupled with the first circuitry, the second circuitry, to perform operations associated with the instruction, including to:
determine whether the first value matches a second value corresponding to the block of data; and
...determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data;
load the block of data from the memory when the first value matches the second value.
7. The processor of claim 1, wherein the second circuitry is to load at least a portion of the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data.
8. (Original) The processor of claim 1, wherein the first value does not include a most significant bit of the pointer.
1. … the 64-bit pointer comprising ... a 4-bit value in bits [60:57];
14. (Original) The processor of claim 1, wherein the block of data is a 128-bit block of data.
1. ... an address to a 128-bit block of data in memory ...; and
15. (Original) The processor of claim 1, wherein the processor is to indicate if the first value does not match the second value.
1 … generate a fault when the 4-bit value from the 64-bit pointer does not match the 4-bit value corresponding to the 128-bit block of data.
20. (Original) A method comprising: decoding a load instruction, the load instruction operating on a pointer, the pointer comprising an address to a block of data in memory and a first value;
1. A processor comprising: first circuitry to decode an instruction, the instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [60:57];
determining whether the first value matches a second value corresponding to the block of data; and
...determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data;
loading the block of data from the memory when the first value matches the second value.
7. The processor of claim 1, wherein the second circuitry is to load at least a portion of the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data.
Regarding claim 20, although claim 1 and 7 of US Patent Application 19/004156 directed to a processor and thus, does not disclose a method, it would have been obvious for one of ordinary skill in the art to have the processor perform the method of claim 20.
Claims 9-13, 16 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,12, 24, and 26 of US Patent Application 19/004156 in view of Radovic et al. (US 2013/0013843).
Regarding claim 9, claims 1 and 7 of US Patent Application 19/004156 discloses process of claim 1. However, claims 1 and 7 of US Patent Application 19/004156 fails to disclose;
wherein the most significant bit of the pointer is to have a value of one for an operating system.
Radovic teaches wherein the most significant bit of the pointer is to have a value of one for an operating system ([0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of US Patent Application 19/004156 and Radovic wherein the most significant bit of the pointer is to have a value of one for an operating system. A person of ordinary skill in the art could have been motivated to combine the teachings as it is known various combinations are possible and other or additional bits may be utilized as well (Radovic [0040]).
Regarding claim 10, claim 1 of US Patent Application 19/004156 discloses process of claim 1. However, claim 1 of US Patent Application 19/004156 fails to disclose;
wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value.
Radovic teaches wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value ([0042] “In such a case, the most-significant bits of an associated virtual address may comprise binary 0s”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of US Patent Application 19/004156 and Radovic wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value. A person of ordinary skill in the art could have been motivated to combine the teachings as it is a known configuration (Radovic [0042]).
Regarding claim 11, claim 1 of US Patent Application 19/004156 discloses process of claim 1. However, claim 1 of US Patent Application 19/004156 fails to disclose;
wherein the first value comprises a most significant bit of the pointer.
Radovic teaches wherein the first value comprises a most significant bit of the pointer ([0040], [0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of US Patent Application 19/004156 and Radovic wherein the first value comprises a most significant bit of the pointer. A person of ordinary skill in the art could have been motivated to combine the teachings as it is known various combinations are possible and other or additional bits may be utilized as well (Radovic [0040])
Regarding claim 12, claim 1 of US Patent Application 19/004156 discloses process of claim 1. Claim 12 of US Patent Application 19/004156 further discloses wherein the processor is a reduced instruction set computing (RISC) processor (12. The processor of claim 1, wherein the processor is a reduced instruction set computing (RISC) processor).
However, claims of US Patent Application 19/004156 fails to disclose;
wherein the first value comprises five bits.
Radovic teaches wherein the first value comprises five bits ([0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of US Patent Application 19/004156 and Radovic wherein the first value comprises five bits. A person of ordinary skill in the art could have been motivated to combine the teachings as it is known various combinations are possible and other or additional bits may be utilized as well (Radovic [0040])
Regarding claim 13, Radovic further teaches wherein the first value comprises ten bits ([0031] “As used herein, ‘version bits’ generally refers to one or more bits used as a tag or identifier”; [0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
Regarding claim 16. claims 1 and 7 of US Patent Application 19/004156 discloses the processor of claim 16.
16. (Original) A computer system comprising: a processor coupled with the DRAM, the processor comprising: decode circuitry to decode a load instruction, the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value; and
1. A processor comprising: first circuitry to decode an instruction, the instruction to operate on a 64-bit pointer, the 64-bit pointer comprising an address to a 128-bit block of data in memory and a 4-bit value in bits [60:57];
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
second circuitry coupled with the first circuitry, the second circuitry, to perform operations associated with the instruction, including to:
determine whether the first value matches a second value corresponding to the block of data; and
...determine whether the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data;
load the block of data from the memory when the first value matches the second value.
7. The processor of claim 1, wherein the second circuitry is to load at least a portion of the 128-bit block of data from the memory when the 4-bit value from the 64-bit pointer matches the 4-bit value corresponding to the 128-bit block of data.
However, claim 1 and 7 of US Patent Application 19/004156 fails to disclose a computer system comprising a dynamic random access memory (DRAM);
Radovic teaches a dynamic random access memory (DRAM) ([0023]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of US Patent Application 19/004156 and Radovic to have a computer system comprising a dynamic random access memory (DRAM). A person of ordinary skill in the art could have been motivated to combine the teachings as the DRAM is a well-known type of physical memory for storing data (Radovic [0023]).
Regarding claim 19, claim 1 and 7 of US Patent Application 19/004156 and Radovic further discloses a processor of claim 16. Radovic further discloses wherein the computer system further comprises a communication device coupled with the processor (Fig 1 and [0023], [0065]),. The remaining limitations are similar to limitations recited in claims 10 and 12 and rejected under the same rationale.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, the claim recites the first value comprises ten bits. However, base claim 12 recites wherein the first value comprises five bits. It is unclear whether the first value should be interpreted as comprising 5 or 10 bits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-13, 15,16,19, and 20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Radovic et al. (US 2013/0013843).
Regarding claim 1, Radovic teaches a processor comprising:
decode circuitry to decode a load instruction (Fig 7 item 704 and [0060] “If a memory access operation, such as a load or store instruction …” [0054] “… The processor may fetch instructions concurrently for one or more threads. These fetch instructions are decoded.”), the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value ([0060] “For example, the first version number (ie first value) associated with the array may be stored in the upper bits of the pointer value as described above …. the pointer may identify a cache line at the start of the array (ie address to a block of data) ); and
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
determine whether the first value matches a second value corresponding to the block of data (Fig 7 item 716 and [0062] “the first version number is compared with the second version number”); and
load the block of data from the memory when the first value matches the second value (Fig 7 item 718 and [0064]).
Regarding claim 8, Radovic teaches the processor of claim 1, wherein the first value does not include a most significant bit of the pointer ([0040] Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
Regarding claim 9, Radovic teaches the processor of claim 8, wherein the most significant bit of the pointer is to have a value of one for an operating system ([0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
Regarding claim 10, Radovic teaches the processor of claim 1, wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value ([0042] “In such a case, the most-significant bits of an associated virtual address may comprise binary 0s”).
Regarding claim 11, Radovic teaches the processor of claim 1, wherein the first value comprises a most significant bit of the pointer ([0040], [0061]).
Regarding claim 12, Radovic teaches the processor of claim 1, wherein the processor is a reduced instruction set computing (RISC) processor ([0025]) , and wherein the first value comprises five bits ([0031] “As used herein, ‘version bits’ generally refers to one or more bits used as a tag or identifier”; [0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
Regarding claim 13, Radovic teaches the processor of claim 12, wherein the first value comprises ten bits ([0031] “As used herein, ‘version bits’ generally refers to one or more bits used as a tag or identifier”; [0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”).
Regarding claim 15, Radovic teaches the processor of claim 1, wherein the processor is to indicate if the first value does not match the second value (Fig 7 item 720 and [0064-0065]).
Regarding claim 16, Radovic teaches a computer system comprising:
a dynamic random access memory (DRAM) ([0023]);
a processor coupled with the DRAM, the processor comprising decode circuitry to decode a load instruction (Fig 7 item 704 and [0060] “If a memory access operation, such as a load or store instruction …” [0054] “… The processor may fetch instructions concurrently for one or more threads. These fetch instructions are decoded.”), the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value ([0060] “For example, the first version number (ie first value) associated with the array may be stored in the upper bits of the pointer value as described above …. the pointer may identify a cache line at the start of the array (ie address to a block of data) ); and
circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
determine whether the first value matches a second value corresponding to the block of data (Fig 7 item 716 and [0062] “the first version number is compared with the second version number”); and
load the block of data from the memory when the first value matches the second value (Fig 7 item 718 and [0064]).
Regarding claim 19, Radovic teaches the computer system of claim 16, wherein the computer system further comprises a communication device coupled with the processor (Fig 1 and [0023], [0065]), wherein the first value comprises five bits ([0031] “As used herein, ‘version bits’ generally refers to one or more bits used as a tag or identifier”; [0040] “Although the bits in the memory access are shown in a particular order, other combinations are possible and other or additional bits may be utilized as well”), and wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value ([0042] “In such a case, the most-significant bits of an associated virtual address may comprise binary 0s”).
Regarding claim 20, Radovic teaches a method comprising:
decoding a load instruction (Fig 7 item 704 and [0060] “If a memory access operation, such as a load or store instruction …” [0054] “… The processor may fetch instructions concurrently for one or more threads. These fetch instructions are decoded.”), the load instruction operating on a pointer, the pointer comprising an address to a block of data in memory and a first value ([0060] “For example, the first version number (ie first value) associated with the array may be stored in the upper bits of the pointer value as described above …. the pointer may identify a cache line at the start of the array (ie address to a block of data));
determining whether the first value matches a second value corresponding to the block of data (Fig 7 item 716 and [0062] “the first version number is compared with the second version number”); and
loading the block of data from the memory when the first value matches the second value (Fig 7 item 718 and [0064]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Radovic et al. (US 2013/0013843) in view of Bruno (US 2004/0036159).
Regarding claim 14, Radovic teaches the processor of claim 1. However, Radovic fails to explicitly disclose wherein the block of data is a 128-bit block of data.
Bruno discloses wherein the block of data is a 128-bit block of data ([0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Radovic and Bruno wherein the block of data is a 128 bit block of data. A person of ordinary skill in the art could have been motivated to combine the teachings to have a 128 bit block data, as per teachings of Bruno, as it is a commonly known configuration for a line or block of memory that can be accessed (Bruno, [0004]).
Allowable Subject Matter
Claims 2-7 and 17-18 would be allowable if rewritten to overcome the rejections under double patenting set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMERSON C PUENTE whose telephone number is (571)272-3652. The examiner can normally be reached M-F 8:00am-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John R Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187