Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the communications filed 5/08/2023. As per the claims filed 5/08/2023:
Claims 21-36 were cancelled.
No claims were added.
Claims 1-20 are pending.
Claim(s) 1, 9, 15 is/are independent claim(s).
Note Regarding Prior Art
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Note Regarding AIA Status
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 7-12, 15-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pradip Bose et al (US PG Pub No: 2022/0179465; Published: 06/09/2022)(hereinafter: Bose).
Claim 1:
As per independent claim 1, Bose discloses an apparatus comprising:
interface circuitry [[0028] computing device 102];
machine-readable instructions [0099]; and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to [0100]:
generate a heatmap based on outputs of one or more sensors in an environment, the environment including a first compute device [[0073] FIG. 8 illustrates a schematic of another example, non-limiting two-phase liquid cooling channel design for a quarter section of an electronic device in accordance with one or more embodiments described herein. FIG. 8 illustrates hot spots 510 up to 1.5 kW/cm2 for device 800. The figure also shows the expected active surface temperature profile.],
the sensor outputs including a metric associated with a property of a coolant and a location of the sensor in the environment [[0078] Sensors 508 can continuously or regularly provide temperature feedback identifying respective temperatures of the cores 108. For example, in some implementations, the cooling controller 906 can receive temperature feedback from sensors 508 regarding respective temperatures of the cores 108. The cooling controller 906 can further adjust the one or more chip cooling apparatus components 110 to cool those cores that become relatively hotter than others.]
identify a compute performance metric of the first compute device [[0034] first subset of the cores 108 can include one or more first cores that are configured to operate using a higher voltage and/or operating frequency relative to a second subset of the one or more cores 108. For example, a first subset of the cores 108 can comprise high performance cores configured to operate up to about 5.0 Ghz and the second subset of cores can include low frequency or low power cores configured to operate up to about 2.0 Ghz. In this scenario, when performance of a defined computational task or workload requiring a high voltage or operating frequency is requested, the thread controller 114 can direct the one or more of the cores 108 included in the first subset to perform the defined computational task or workload using the higher operating voltage or frequency. Likewise, when performance of a defined computational task or workload requiring a low voltage or operating frequency is requested, the thread controller 114 can direct the one or more of the cores 108 included in the second subset to perform the defined computational task or workload using the lower operating voltage or frequency.]
determine a cooling parameter for the first compute device based on the heatmap and the compute performance metric [[0036] the one or more chip cooling apparatus components 110 of the computing device 102 can cool the one or more IC chips and the cores 108 in response to detection of one or more anomalous hot spots. In general, an anomalous hot spot can be caused by actual malicious activity, sensor malfunction, and/or malicious activity causing sensor malfunction. However, it should be noted that the aforementioned causes of anomalous hot spots are not restrictive and other causes can exist. The one or more chip cooling apparatus components 110 can non-uniformly cool the one or more IC chips 104 such that a first subset (including one or more) of the cores 108 that have encountered a hot spot can be cooled relative to a second subset of the one or more cores 108.] and
cause a cooling distribution unit to control flow of the coolant in the environment based on the cooling parameter [[0046] cooling of the one or more IC chips (e.g., IC chip 200 or IC chip stack 201) can be achieved via removal of heat from liquid coolant that is passed through cooling channels located on, within, or near the one or more IC chips using a liquid to liquid heat exchanger or via condensing vapor resulting from boiling of the liquid coolant within the channels (e.g., using a condenser). [0057] the amount and flow rate of the liquid coolant is controlled through the usage of one or more flow impedance structures (not shown) that are integrated within or near openings of the microchannels. The flow impedance structures physically block or impede the flow of liquid coolant through the respective micro-channels they are associated with. The flow impedance manipulators can thus be arranged to divert liquid coolant to a desired subset of the microchannels associated with an area of the one or more IC chips 104 including one or more cores 108 to be cooled, depending on the type of cooling system employed (e.g., single-phase verses two-phase). For example, in order to increase the flow of liquid coolant to a first subset of microchannels located adjacent to an area of the chip comprising a core that is to be cooled, one or more flow impedance structures can be provided near openings of a second subset of the microchannels surrounding the first subset of microchannels. In other embodiments, the amount and flow rate of the liquid coolant to respective areas of the one or more IC chips 104 comprising cores to be cooled or can be controlled via the physical configuration of the microchannels.]
Claim 3:
As per claim 3, which depends on claim 1, Bose discloses wherein, to determine the cooling parameter, the programmable circuitry is to: identify a workload to be performed by the first compute device [[0033] the first subset of the cores 108 can be selected to operate at a higher operating voltage or frequency for one or more defined computational tasks or workloads that require a higher operating voltage or frequency based on a time constraint assigned for completion of the task or workload and/or a degree of processing strain/complexity associated with performance of the computational task or workload.] and determine a target property of coolant to be provided to the location based on the workload, the heatmap, and the compute performance metric [[0030] the one or more chip cooling apparatus components 110 can facilitate non-uniform cooling of the one or more IC chips and the respective cores 108 formed thereon, thereby enabling some of the cores to be cooled to lower temperatures than others (referred to herein as being “overcooled”) and thus enabling the overcooled cores to compensate for anomalous hot spots. In some embodiments, the computing device 102 can further comprise a thread controller 114 that assigns threads or computational tasks/workloads to the respective cores 108 of the multi-core processor 106. In one or more embodiments, the computing device 102 can also comprise a voltage/frequency controller 116 that can direct one or more of the cores 108 to perform an assigned computational task/workload at a defined operating voltage or frequency.].
Claim 4:
As per claim 4, which depends on claim 3, Bose discloses wherein the sensors include a first sensor generating first outputs, and the programmable circuitry is to: compare the first outputs to a temperature threshold for the coolant; and in response to the first outputs failing to satisfy the temperature threshold, determine an adjustment to the cooling parameter that redistributes a flow of the coolant between the first compute device and a second compute device [[0091] the first heat feature or the first cooling requirement is within a first threshold of the minimum of the different cooling capacities [0052] the sensors can be disposed in proximity to the inlet 120 and/or in proximity the outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108. [0061] The channels 506 can comprise flow impedance structures 502 (e.g. moveable components) for active flow redistribution. The flow impedance structures 502 can be passive, (fixed for a given channel design), or active (dynamically adjustable) based on temperature feedback from the sensors 508.]
Claim 7:
As per claim 7, which depends on claim 1, Bose discloses wherein the outputs of the sensors are associated with a first time and the programmable circuitry is to: detect a change in the property of the coolant based on outputs of the one or more sensors at a second time; and cause the cooling parameter to be adjusted based on the change [[0061] The channels 506 can comprise flow impedance structures 502 (e.g. moveable components) for active flow redistribution. The flow impedance structures 502 can be passive, (fixed for a given channel design), or active (dynamically adjustable) based on temperature feedback from the sensors 508.]. cooling parameters changed in response to temperature feedback from sensors.
Claim 8:
As per claim 8, which depends on claim 1, Bose discloses wherein the programmable circuitry includes one or more of: at least one of a central processor unit, a graphics processor unit, or a digital signal processor,[ [0080] For instance, FIG. 10 presents an IC chip 1000 comprising a cooling channel configuration that facilitates actively cooling select cores of a multi-core processor in accordance with various embodiments described herein. IC chip 1000 is similar to IC chip 700 with the substitution of controllable valves 1002 at the opening of the respective channels 506 as opposed to flow impedance structures 502] the at least one of the central processor unit, the graphics processor unit, or the digital signal processor having control circuitry to control data movement within the programmable circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to machine-readable data, and one or more registers to store a result of the one or more first operations, the machine-readable data in the apparatus [[0095] the processing unit 1514 can be or include multi-core processor 106 and vice versa. The system bus 1518 couples system components including, but not limited to, the system memory 1516 to the processing unit 1514. The processing unit 1514 can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit 1514. The system bus 1518 can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1594), and Small Computer Systems Interface (SCSI). The system memory 1516 can also include volatile memory 1520 and nonvolatile memory 1522. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer 1512, such as during start-up, is stored in nonvolatile memory 1522.]
a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and the plurality of the configurable interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations; or Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations [[0099] electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, [0095] memory to store operations [0096] computer storage medium].
Claim 9:
As per independent claim 9, Bose discloses a non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least [[0026]Computer readable medium [0083]]: identify a location of a sensor in an environment responsive to outputs of the sensor, the output of the sensor indicative of a property of a coolant associated with the location [[0046] The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. correlate the location of the sensor with a compute device in the environment [[0073] Sensors 508 can continuously or regularly provide temperature feedback identifying respective temperatures of the cores 108. For example, in some implementations, the cooling controller 906 can receive temperature feedback from sensors 508 regarding respective temperatures of the cores 108. The cooling controller 906 can further adjust the one or more chip cooling apparatus components 110 to cool those cores that become relatively hotter than others]
determine a cooling parameter for the compute device based on the outputs of the sensors and one or more workloads to be performed by the compute device [[0036] the one or more chip cooling apparatus components 110 of the computing device 102 can cool the one or more IC chips and the cores 108 in response to detection of one or more anomalous hot spots. In general, an anomalous hot spot can be caused by actual malicious activity, sensor malfunction, and/or malicious activity causing sensor malfunction. However, it should be noted that the aforementioned causes of anomalous hot spots are not restrictive and other causes can exist. The one or more chip cooling apparatus components 110 can non-uniformly cool the one or more IC chips 104 such that a first subset (including one or more) of the cores 108 that have encountered a hot spot can be cooled relative to a second subset of the one or more cores 108.] and cause a cooling distribution unit to control the coolant based on the cooling parameter for cooling the compute device [[0046] cooling of the one or more IC chips (e.g., IC chip 200 or IC chip stack 201) can be achieved via removal of heat from liquid coolant that is passed through cooling channels located on, within, or near the one or more IC chips using a liquid to liquid heat exchanger or via condensing vapor resulting from boiling of the liquid coolant within the channels (e.g., using a condenser). [0057] the amount and flow rate of the liquid coolant is controlled through the usage of one or more flow impedance structures (not shown) that are integrated within or near openings of the microchannels. The flow impedance structures physically block or impede the flow of liquid coolant through the respective micro-channels they are associated with. The flow impedance manipulators can thus be arranged to divert liquid coolant to a desired subset of the microchannels associated with an area of the one or more IC chips 104 including one or more cores 108 to be cooled, depending on the type of cooling system employed (e.g., single-phase verses two-phase). For example, in order to increase the flow of liquid coolant to a first subset of microchannels located adjacent to an area of the chip comprising a core that is to be cooled, one or more flow impedance structures can be provided near openings of a second subset of the microchannels surrounding the first subset of microchannels. In other embodiments, the amount and flow rate of the liquid coolant to respective areas of the one or more IC chips 104 comprising cores to be cooled or can be controlled via the physical configuration of the microchannels.]
Claim 10:
As per claim 10, which depends on claim 9, Bose discloses wherein the instructions cause the programmable circuitry to generate a heatmap indicative of the property of the coolant at the location relative to one or more other locations in the environment. [[0073] FIG. 8 illustrates a schematic of another example, non-limiting two-phase liquid cooling channel design for a quarter section of an electronic device in accordance with one or more embodiments described herein. FIG. 8 illustrates hot spots 510 up to 1.5 kW/cm2 for device 800. The figure also shows the expected active surface temperature profile.],
Claim 11:
As per claim 11, which depends on claim 10, Bose discloses wherein the location is a first location, the compute device is a first compute device, and the instructions cause the programmable circuitry to:identify, based on the heatmap, a second location in which the property of the coolant does not satisfy a parameter associated with at least one of performance of a second compute device at the second location or a service level agreement for the second compute device; and determine an adjustment to the cooling parameter responsive to the identification at the second location.[[0078] the cooling controller 906 can further adjust the one or more chip cooling apparatus components 110 to cool those cores that become relatively hotter than others. This can be a dynamic process wherein the cooling controller 906 regularly adapts the coolant distribution of the chip cooling apparatus components 110 (e.g., via control of the one or more flow control devices 904) to cool cores as they become relatively hotter than other cores.]
Claim 12:
As per claim 12, which depends on claim 10, Bose discloses wherein the instructions cause the programmable circuitry to meter an amount of coolant consumed by an appliance including the compute device based on the heatmap [[0051] In the embodiment shown the closed loop cooling system 400 can comprise a flow meter (FM) to measure and/or monitor the flow rate of the liquid coolant into the electronic device. The closed loop cooling system 400 can also comprise one or more pressure sensors (P) and temperature sensors (T) to measure and/or monitor fluid temperature and pressure throughout operation of the closed loop cooling system 400.].
Claim 15:
As per independent claim 15, Bose discloses a system comprising: a first sensor to generate outputs indicative of a first property of a fluid at a first location in an environment, the first location including a first compute device [[0046] the one or more chip cooling apparatus components 110, the condenser/heat exchanger 124, and the wet/dry cooler 130 together form a cooling apparatus or cooling system that can facilitate removing heat from the one or more IC chips 104, thereby cooling the one or more IC chips 104. The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.]
a second sensor to generate outputs indicative of a second property of the fluid at a second location in the environment, the second location including a second compute device, the second location different than the first location [[0046] the one or more chip cooling apparatus components 110, the condenser/heat exchanger 124, and the wet/dry cooler 130 together form a cooling apparatus or cooling system that can facilitate removing heat from the one or more IC chips 104, thereby cooling the one or more IC chips 104. The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.]
interface circuitry[[0028] computing device 102];; machine-readable instructions [0099]; and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to [0100]:
identify a first performance metric associated with the first compute device and a second performance metric associated with the second compute device [[0034] first subset of the cores 108 can include one or more first cores that are configured to operate using a higher voltage and/or operating frequency relative to a second subset of the one or more cores 108. For example, a first subset of the cores 108 can comprise high performance cores configured to operate up to about 5.0 Ghz and the second subset of cores can include low frequency or low power cores configured to operate up to about 2.0 Ghz. In this scenario, when performance of a defined computational task or workload requiring a high voltage or operating frequency is requested, the thread controller 114 can direct the one or more of the cores 108 included in the first subset to perform the defined computational task or workload using the higher operating voltage or frequency. Likewise, when performance of a defined computational task or workload requiring a low voltage or operating frequency is requested, the thread controller 114 can direct the one or more of the cores 108 included in the second subset to perform the defined computational task or workload using the lower operating voltage or frequency.]
and
cause a flow of the fluid to the first compute device to be adjusted relative to a flow of fluid to the second compute device based on the first performance metric, the second performance metric, the first fluid property, and the second fluid property [[0078] the cooling controller 906 can further adjust the one or more chip cooling apparatus components 110 to cool those cores that become relatively hotter than others. This can be a dynamic process wherein the cooling controller 906 regularly adapts the coolant distribution of the chip cooling apparatus components 110 (e.g., via control of the one or more flow control devices 904) to cool cores as they become relatively hotter than other cores.].
Claim 16:
As per claim 16, which depends on claim 15, Bose discloses further including:a third sensor to generate outputs indicative of a third property of the fluid at a third location in the environment, the third location including a fluid distribution pipe; and a fourth sensor to generate outputs associated with a cooling distribution unit, the cooling distribution unit to control the flow of the fluid [[0046] The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.]
Claim 17:
As per claim 17, which depends on claim 15, Bose discloses wherein the programmable circuitry is to generate a heatmap based on the outputs of the first sensor and the second sensor [[0073] FIG. 8 illustrates a schematic of another example, non-limiting two-phase liquid cooling channel design for a quarter section of an electronic device in accordance with one or more embodiments described herein. FIG. 8 illustrates hot spots 510 up to 1.5 kW/cm2 for device 800. The figure also shows the expected active surface temperature profile.]
Claim 18:
As per claim 18, which depends on claim 17, Bose discloses wherein, to generate the heatmap, the programmable circuitry is to: identify coordinates of the first sensor and the second sensor relative to the environment; associate locations of the first compute device and the second compute device with the outputs of the sensors; and correlate the first property of the fluid and second property of the fluid with the respective locations [[0046] The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.]. sensors are associated with different components (necessarily associated with the location of the component).
Claim 19:
As per claim 19, which depends on claim 17, Bose discloses wherein the heatmap indicates a temperature, a density, a chemical property, or a heat dissipation potential of the fluid at one or more locations in the environment, the locations including the first location and the second location [see figure 8, temperatures of multiple locations displayed.].
Claim 20:
As per claim 20, which depends on claim 15, Bose discloses wherein the first property is a first temperature of the fluid, the second property is a second temperature of the fluid, and further including a third sensor to generate outputs indicative of a third temperature of the fluid downstream of the first sensor and the second sensor [[0046] The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108].
the third temperature higher than the first temperature and the second temperature, and wherein the programmable circuitry is to determine an amount of the fluid having the third temperature to be provided to a third location in the environment, the third location different than the first location and the second location [[0056] the one or more chip cooling apparatus components 110 can be designed to provide a higher amount and flow rate of the liquid coolant to one or more areas of the one or more chips comprising cores that are desired to be cooled in response to detection of a hot spot. Alternatively, in embodiments in which in the condenser/heat exchanger 124 comprises a condenser that removes heat from liquid coolant provided in the microchannels via boiling of the liquid coolant and condensing the resulting vapor (e.g., two-phase cooling), the one or more chip cooling apparatus components 110 can be designed to provide a lower flow rate of the liquid coolant to one or more areas of the one or more chips comprising cores that are desired to be cooled. In particular, the degree of cooling associated with two-phase cooling can be directly attributed to the quality of the vapor generated from the boiled liquid coolant]. Fluid is flowed from areas with lower temperature to areas identified to have a hotspot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bose in view of Abraham Lerer et at (WO2021/214752; Published: 10/28/2021)(hereinafter: Lerer).
Claim 2:
As per claim 2, which depends on claim 1, Bose failed to disclose wherein the programmable circuitry is to determine the cooling parameter based on a service level agreement associated with the first compute device.
Lerer, in the same field of power efficiency of a hardware devices discloses this limitation in that [[0017] Without sufficient cooling, servers are typically configured to automatically reduce their speed when heat builds up beyond a given temperature threshold. [0019] While reducing server speed improves energy efficiency, servers must still be configured to meet performance levels defined by Service Level Agreements (SLAs), that is, data center commitments to customers for levels of speed and service). [0039] One measure of cooling capacity, for example, may be the rotations per minute (RPM) of cooling fans, a metric that may be provided by some operating systems and by DCM. [0041] After a model is generated, at a step 224 real-time data is collected for the target service operation. The data, including system utilization data, as well as optional data such as temperature levels and metrics on SLA compliance, is then applied to the model generated at the step 222, to determine, at a step 226 a change to power capping.]
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify cooling requirements of Bose to determine the cooling parameter based on a service level agreement associated with the first compute device as disclosed by Lerer. The motivation for doing so would have been to achieve energy savings as long as the SLAs and expected levels of QoS are achieved (0003).
Claim 13:
As per claim 13, which depends on claim 9, it is rejected under the same rationale as claim 2 above.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bose in view of Sean James et at (US20160011607; Published: 01/14/2016)(hereinafter: James).
Claim 5:
As per claim 5, which depends on claim 1, Bose failed to specifically disclose wherein the programmable circuitry is to redistribute a workload to be performed by the first compute device to a second compute device based on the cooling parameter.
James, in the same of hardware cooling discloses [[0070] Another way to address thermal impacts of workloads is by scheduling workloads on individual computing devices. For example, assume a given computing device has current utilization states of 90% for processor, memory, storage, and network, and is at a relatively high temperature. One or more executable programs can be moved from that computing device to another computing device with a lower temperature and/or with lower utilization states for one or more of the hardware resources.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify cooling of Bose to redistribute a workload to be performed by the first compute device to a second compute device based on the cooling parameter as disclosed by James. The motivation for doing so would have been to quickly and reliably cool down hardware significantly reducing energy expenditures relative to reactive approaches.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bose in view of Ali Heydari (US2022/0011834; Filed: 7/8/2020)(hereinafter: Heydari).
Claim 6:
As per claim 6, which depends on claim 1, Bose discloses wherein the programmable circuitry is to generate the heatmap based on outputs from the first sensor, the second sensor, the third sensor, and the fourth sensor [[0073] Sensors 508 can continuously or regularly provide temperature feedback identifying respective temperatures of the cores 108. For example, in some implementations, the cooling controller 906 can receive temperature feedback from sensors 508 regarding respective temperatures of the cores 108. The cooling controller 906 can further adjust the one or more chip cooling apparatus components 110 to cool those cores that become relatively hotter than others.]. See figure 8, heatmap generated based on sensor data.
Bose discloses sensors associated with different cores but failed to specifically disclose wherein the sensors include a first sensor associated with a first compute device in a first chassis, a second sensor associated with a second compute device in the first chassis, a third sensor associated with a third compute device in a second chassis, and a fourth sensor associated with a heat distribution pipe that conveys the coolant,
Heydari, in the same field of cooling systems for datacenters discloses this limitation in that [[0090] The first heat feature or the cooling requirement may be a temperature sensed by a sensor associated with the at least one first rack 254. In at least one embodiment, concurrently with the coolant-based cooling subsystem 280 cooling the at least one first rack 254 (or a server therein), the refrigerant-based cooling subsystem 282 of the multiple mode cooling subsystem 256 has associated second looping components (such as a refrigerant-based second cooling loop in row manifold 266 and in rack manifolds 296A, 296B) to guide a second cooling media (such as a refrigerant or dielectric refrigerant) to at least one second rack of the datacenter according to a second heat feature or a second cooling requirement of the at least one second rack. This type of different cooling media addressing different requiring racks is also possible to address different requiring servers within the same rack as already illustrated by rack 254 in FIG. 2C.] sensors associated with different server racks, it follows that for N number of racks there would be N number of sensors.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the sensors of Bose to include a first sensor associated with a first compute device in a first chassis, a second sensor associated with a second compute device in the first chassis, a third sensor associated with a third compute device in a second chassis, and a fourth sensor associated with a heat distribution pipe that conveys the coolant as disclosed by Heydari. The motivation for doing so would have been to enable the movement of the coolant according to temperature sensors in various locations, including in the room, in one or more racks, and/or in server boxes or server trays within the racks.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art of record, alone or in any reasonable combination discloses the limitation of dependent claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOWARD CORTES whose telephone number is (571)270-1383. The examiner can normally be reached on M-F, 8:00 am - 5:00 pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Scott T Baderman can be reached on (571)272-3644. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HOWARD CORTES/ Primary Examiner, Art Unit 2118