Prosecution Insights
Last updated: August 18, 2026
Application No. 18/313,994

TELEMETRY SYSTEMS FOR MONITORING COOLING OF COMPUTE COMPONENTS AND RELATED APPARATUS AND METHODS

Final Rejection §102
Filed
May 08, 2023
Priority
Dec 30, 2022 — IN 202241077283
Examiner
CORTES, HOWARD
Art Unit
2118
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
408 granted / 521 resolved
+23.3% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
20 currently pending
Career history
538
Total Applications
across all art units

Statute-Specific Performance

§101
11.2%
-28.8% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
13.9%
-26.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 521 resolved cases

Office Action

§102
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the communications 5/28/2026. As per the claims filed 5/26/2026: Claims 1-12, 17, 18, 20 were amended. Claims 13-14 were cancelled. Claims 37, 38 were added. Claims 1-12, 15-20, 37-38 are pending. Claim(s) 1, 9, 15 is/are independent claim(s). Note Regarding Prior Art Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Note Regarding AIA Status In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 15-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pradip Bose et al (US PG Pub No: 2022/0179465; Published: 06/09/2022)(hereinafter: Bose). Claim 15: As per independent claim 15, Bose discloses a system comprising: a first sensor to generate outputs indicative of a first property of a fluid at a first location in an environment, the first location including a first compute device [[0046] the one or more chip cooling apparatus components 110, the condenser/heat exchanger 124, and the wet/dry cooler 130 together form a cooling apparatus or cooling system that can facilitate removing heat from the one or more IC chips 104, thereby cooling the one or more IC chips 104. The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.] a second sensor to generate outputs indicative of a second property of the fluid at a second location in the environment, the second location including a second compute device, the second location different than the first location [[0046] the one or more chip cooling apparatus components 110, the condenser/heat exchanger 124, and the wet/dry cooler 130 together form a cooling apparatus or cooling system that can facilitate removing heat from the one or more IC chips 104, thereby cooling the one or more IC chips 104. The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.] interface circuitry[[0028] computing device 102];; machine-readable instructions [0099]; and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to [0100]: identify a first performance metric associated with the first compute device and a second performance metric associated with the second compute device [[0034] first subset of the cores 108 can include one or more first cores that are configured to operate using a higher voltage and/or operating frequency relative to a second subset of the one or more cores 108. For example, a first subset of the cores 108 can comprise high performance cores configured to operate up to about 5.0 Ghz and the second subset of cores can include low frequency or low power cores configured to operate up to about 2.0 Ghz. In this scenario, when performance of a defined computational task or workload requiring a high voltage or operating frequency is requested, the thread controller 114 can direct the one or more of the cores 108 included in the first subset to perform the defined computational task or workload using the higher operating voltage or frequency. Likewise, when performance of a defined computational task or workload requiring a low voltage or operating frequency is requested, the thread controller 114 can direct the one or more of the cores 108 included in the second subset to perform the defined computational task or workload using the lower operating voltage or frequency.] and cause a flow of the fluid to the first compute device to be adjusted relative to a flow of fluid to the second compute device based on the first performance metric, the second performance metric, the first fluid property, and the second fluid property [[0078] the cooling controller 906 can further adjust the one or more chip cooling apparatus components 110 to cool those cores that become relatively hotter than others. This can be a dynamic process wherein the cooling controller 906 regularly adapts the coolant distribution of the chip cooling apparatus components 110 (e.g., via control of the one or more flow control devices 904) to cool cores as they become relatively hotter than other cores.]. Claim 16: As per claim 16, which depends on claim 15, Bose discloses further including:a third sensor to generate outputs indicative of a third property of the fluid at a third location in the environment, the third location including a fluid distribution pipe; and a fourth sensor to generate outputs associated with a cooling distribution unit, the cooling distribution unit to control the flow of the fluid [[0046] The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.] Claim 17: As per claim 17, which depends on claim 15, Bose discloses wherein the programmable circuitry is to generate a heatmap based on the outputs of the first sensor and the second sensor [[0073] FIG. 8 illustrates a schematic of another example, non-limiting two-phase liquid cooling channel design for a quarter section of an electronic device in accordance with one or more embodiments described herein. FIG. 8 illustrates hot spots 510 up to 1.5 kW/cm2 for device 800. The figure also shows the expected active surface temperature profile.] Claim 18: As per claim 18, which depends on claim 17, Bose discloses wherein, to generate the heatmap, the programmable circuitry is to: identify coordinates of the first sensor and the second sensor relative to the environment; associate locations of the first compute device and the second compute device with the outputs of the sensors; and correlate the first property of the fluid and second property of the fluid with the respective locations [[0046] The sensors (although not shown will be described in greater detail with regards to FIG. 9) can be placed at various locations within the system 100 to facility non-uniform cooling of the system 100. The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108.]. sensors are associated with different components (necessarily associated with the location of the component). Claim 19: As per claim 19, which depends on claim 17, Bose discloses wherein the heatmap indicates a temperature, a density, a chemical property, or a heat dissipation potential of the fluid at one or more locations in the environment, the locations including the first location and the second location [see figure 8, temperatures of multiple locations displayed.]. Claim 20: As per claim 20, which depends on claim 15, Bose discloses wherein the first property is a first temperature of the fluid, the second property is a second temperature of the fluid, and further including a third sensor to generate outputs indicative of a third temperature of the fluid downstream of the first sensor and the second sensor [[0046] The sensors can be disposed in proximity to an inlet 120 and/or in proximity to an outlet 122 to determine a net temperature increase or decrease for the system 100 as a whole. For example, the sensors can be disposed within the inlet 120 and/or the outlet 122. Alternatively, the sensors can be disposed at various inlets and/or outlets associated with channels that are adjacent to the cores 108]. the third temperature higher than the first temperature and the second temperature, and wherein the programmable circuitry is to determine an amount of the fluid having the third temperature to be provided to a third location in the environment, the third location different than the first location and the second location [[0056] the one or more chip cooling apparatus components 110 can be designed to provide a higher amount and flow rate of the liquid coolant to one or more areas of the one or more chips comprising cores that are desired to be cooled in response to detection of a hot spot. Alternatively, in embodiments in which in the condenser/heat exchanger 124 comprises a condenser that removes heat from liquid coolant provided in the microchannels via boiling of the liquid coolant and condensing the resulting vapor (e.g., two-phase cooling), the one or more chip cooling apparatus components 110 can be designed to provide a lower flow rate of the liquid coolant to one or more areas of the one or more chips comprising cores that are desired to be cooled. In particular, the degree of cooling associated with two-phase cooling can be directly attributed to the quality of the vapor generated from the boiled liquid coolant]. Fluid is flowed from areas with lower temperature to areas identified to have a hotspot. Allowable Subject Matter Claims 1-12, 37 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Claim 9 now includes subject matter indicated as allowable (previous claim 14). Claims 37-38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 5/26/2026 regarding the claim rejection to claim 1 under USC 102 have been fully considered and are found to be persuasive. The rejection is herein withdrawn in response to amendment, the claims are now allowable over the prior art. Applicant's arguments filed 5/26/2026 regarding the claim rejection to claim 15 under USC 102 have been fully considered but they are not persuasive. Applicant submits: “However, Bose does not teach or suggest causing a flow of fluid to the first subset of the cores 108 to be adjusted relative to a flow of fluid to the second subset of the cores 108 based on a voltage or operating frequency (e.g., an alleged performance metric) of the first subset of the cores 108 and a voltage or operating frequency (e.g., an alleged performance metric) of the second subset of the cores 108. Therefore, Bose not anticipate at least one programmable circuit to cause a flow of fluid to a first compute device to be adjusted relative to a flow of fluid to a second compute device based on a first performance metric, a second performance metric, a first fluid property, and a second fluid property. Accordingly, Bose does not anticipate the system of claim 15. Thus, independent claim 15 and all claims depending therefrom are allowable over Bose. Withdrawal of the § 102 rejections therefrom is respectfully requested.” The Examiner respectfully disagrees. Bose specifically discloses at paragraph 0078 “the cooling controller 906 can further adjust the one or more chip cooling apparatus components 110 to cool those cores that become relatively hotter than others. This can be a dynamic process wherein the cooling controller 906 regularly adapts the coolant distribution of the chip cooling apparatus components 110 (e.g., via control of the one or more flow control devices 904) to cool cores as they become relatively hotter than other cores”. That is, the flow of fluid is adjusted to hotter cores (a first compute device) relative to the flow of fluid of a second device (cool cores). This can be accomplished by controlling the flow of fluid through the microchannels as disclosed in para 0056-0057. One of ordinary skill in the art would appreciate that the controller takes these decisions based on the first performance metric (temperature of the cores (0060) which is directly associated with performance (higher performance, higher temperature)), the second performance metric(temperature of the cores (0060) which is directly associated with performance (higher performance, higher temperature)), the first fluid property (each core has a sensor 508 (see fig 5, para 0062) that measures inlet and outlet fluid temperature), and the second fluid property(each core has a sensor 508 (see fig 5, para 0062) that measures inlet and outlet fluid temperature). Thus, Bose anticipates the claimed limitation. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOWARD CORTES whose telephone number is (571)270-1383. The examiner can normally be reached on M-F, 8:00 am - 5:00 pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Scott T Baderman can be reached on (571)272-3644. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HOWARD CORTES/ Primary Examiner, Art Unit 2118
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Prosecution Timeline

May 08, 2023
Application Filed
Jun 22, 2023
Response after Non-Final Action
Feb 26, 2026
Non-Final Rejection mailed — §102
May 26, 2026
Response Filed
Jun 08, 2026
Examiner Interview Summary
Jun 08, 2026
Applicant Interview (Telephonic)
Aug 04, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
93%
With Interview (+14.3%)
3y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 521 resolved cases by this examiner. Grant probability derived from career allowance rate.

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