Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3-5,7,9-11,13,15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210019082 A1 (Berman) in view of US 20200111539 A1 (Yamaguchi) and US 20240071558 A1 (Wilson).
Regarding claim 1, Berman teaches
An information handling system comprising:
a processor;(par 50 “executable by any device or machine comprising suitable architecture, such as a general purpose digital computer having a processor, memory, and input/output interfaces).”)
a memory system communicatively coupled to the processor(fig 1:126; par 22 “The access controller 125 is configured to interface with a nonvolatile memory device 126. In an exemplary embodiment, the nonvolatile memory device 126 is implemented by a phase-change memory device. The nonvolatile memory device 126 includes a main region 126-1 and a spare region 126-2.”), the memory system comprising a plurality of rows and a plurality of spare rows for post-package repair (PPR) of the memory system;(par 30 “The method of FIG. 3 further includes writing the first codeword to a row of the main region 126-2 having a location derived from the logical address Laddr.”; par 32 “The method of FIG. 3 further includes allocating a new spare address from the spare region 126-2 and writing the first codeword to a location of the spare region 126-2 associated with the new spare address (step 335).”) and
one or more instructions stored in non-transitory computer readable media and configured to, when executed, cause the processor to(par 50 “… methods may be tangibly embodied on one or more computer readable medium(s) … and executable by any device … such as a general purpose digital computer having a processor, ….”), in response to a detection of a defect in a block of a particular row of the plurality of rows: (fig 3:330; par 31 “The method of FIG. 3 further includes determining whether the written row is a bad row (step 330). In an exemplary embodiment, the determination is performed by reading data from the written row, comparing the received data against the read data to determine a number of errors, and determining that the row is bad when the number of errors exceeds a certain threshold.”)
track a number of defects in the block of the particular row;(par 31 “…the determination is performed by reading data from the written row, comparing the received data against the read data to determine a number of errors, …. “)
while the number of defects in the particular row is below a threshold, consider the row to be good,(par 31 “In an exemplary embodiment, the write/read controller 125 reads the data from the written row and performs the comparing. If the number of errors is less than or equal to the threshold, the method can exit since the row is considered to be good.”)
and in response to the number of defects in the particular row being at or above the threshold,(fig 3:330,335; par 31 “The method of FIG. 3 further includes determining whether the written row is a bad row (step 330). In an exemplary embodiment, the determination is performed by reading data from the written row, comparing the received data against the read data to determine a number of errors, and determining that the row is bad when the number of errors exceeds a certain threshold. In an exemplary embodiment, the write/read controller 125 reads the data from the written row and performs the comparing. If the number of errors is less than or equal to the threshold, the method can exit since the row is considered to be good. If the number of errors exceeds the threshold, the method continues to step 335.”) perform hardware-based PPR memory healing to replace the particular row with one of the plurality of spare rows.(fig 3:335,340,350; par 32 “The method of FIG. 3 further includes allocating a new spare address from the spare region 126-2 and writing the first codeword to a location of the spare region 126-2 associated with the new spare address (step 335). For example, as shown in FIG. 4B, the first codeword is written into a first row of the first Spare Block 1 of the spare region 126-2.”)
However, although Berman teaches in response to a number of defects in the particular row being below a threshold, Berman does not specifically teach in response to a number of defects in the particular row being below a threshold, perform software-based PPR memory healing to prevent use of the block.
On the other hand, Yamaguchi teaches
An information handling system comprising:
a processor;(fig 1:200, fig 14:601; par 43)
a memory system communicatively coupled to the processor(fig 1:100, fig 14:603; par 42), the memory system comprising a plurality of rows and a plurality of spare rows for post-package repair (PPR) of the memory system;(fig 1:100; par 43 “The DIMM 100 has a plurality of rows 112 and a plurality of spare rows 113. The row 112 is switched to the spare row 113 by the PPR upon failure.”; PPR is defined in par 5 “Repairing a fault row by switching the faulty row to the spare row is called a post package repair (PPR).”) and
one or more instructions stored in non-transitory computer readable media and configured to, when executed, cause the processor to, in response to a detection of a defect in a block of a particular row of the plurality of rows: (fig 11C:S16; par 113 “Further, as illustrated in FIG. 11C, when the memory controller 210 detects that the CE threshold of the DIMM 100 is exceeded during operation of the OS 500, the memory controller 210 generates an SMI and executes the SMI handler 420 of the BIOS 400 (operation S16).”)
track a number of defects in the block of the particular row;( fig 11C:S16; par 113“Further, as illustrated in FIG. 11C, when the memory controller 210 detects that the CE threshold of the DIMM 100 is exceeded during operation of the OS 500, the memory controller 210 generates an SMI and executes the SMI handler 420 of the BIOS 400 (operation S16).”)
while the number of defects in the particular row is below a threshold, perform software-based PPR memory healing to prevent use of the block;(fig 11B:S11; par 111 “Then, the BIOS 400 performs a monitoring setting of the row 112 to which the sPPR is applied to the row access monitoring unit 216 of the memory controller 210 (operation S11).”; par 6 “The PPR includes an hPPR and an sPPR. In the hPPR, a fuse switches a faulty row to a spare row. Therefore, the repair by the hPPR may not be undone. In the sPPR, software switches a faulty row to a spare row. Therefore, the repair by the sPPR is lost by reset.”) and
in response to the number of software-based PPR memory healing in the particular row being at or above the threshold, perform hardware-based PPR memory healing to replace the particular row with one of the plurality of spare rows(fig 1:620,630; fig 12B:S42,S43; par 83 “When Cancelcount exceeds a predetermined threshold, the sPPR effect management unit 620 notifies the hPPR data management unit 630 of the sPPR position information 621 and deletes the same information of the sPPR position information 621 and the sPPR position history 622.”; Cancelcount is defined in par 82 “The sPPR effect management unit 620 determines whether the PPR position information notified from the CE information aggregation unit 610 is in the sPPR position history 622, and when such information exists, the sPPR effect management unit 620 adds 1 to Cancelcount.”; hPPR stands for hardware based post package repair and is defined in par 6 “The PPR includes an hPPR and an sPPR. In the hPPR, a fuse switches a faulty row to a spare row. Therefore, the repair by the hPPR may not be undone. In the sPPR, software switches a faulty row to a spare row.”; par 13 “set the software repair position information as hardware repair position information” ), wherein performing hardware-based PPR includes mapping the block back into available memory.(par 6 “The PPR includes an hPPR and an sPPR. In the hPPR, a fuse switches a faulty row to a spare row. Therefore, the repair by the hPPR may not be undone.” par 83 “When Cancelcount exceeds a predetermined threshold, the sPPR effect management unit 620 notifies the hPPR data management unit 630 of the sPPR position information 621 and deletes the same information of the sPPR position information 621 and the sPPR position history 622.”. By replacing the faulty row with the spare row and deleting the position information from the software based PPR, we are essentially mapping the block back into available memory by deleting the software based re-routing that was done earlier and replacing the original faulty row.)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Berman to incorporate the software-based PPR memory healing to prevent use of the block of Yamaguchi. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Berman -- a need for a need for a solution for the issue of how to handle detected errors in a row that are below Berman’s error threshold (Berman par 31 “In an exemplary embodiment, the write/read controller 125 reads the data from the written row and performs the comparing. If the number of errors is less than or equal to the threshold, the method can exit since the row is considered to be good.”; Yamaguchi par 38 “there is a problem that an inappropriate row may be subject to the PPR.”) -- with Yamaguchi providing a known method to solve a similar problem. Yamaguchi provides “an embodiment of a technique of properly repairing a row in which a correctable error occurs in a memory module.”(Yamaguchi par 40)
However, although Berman and Yamaguchi deal with memory rows and columns, Berman and Yamaguchi do not specifically teach “perform software- based PPR memory healing to prevent use of the block by mapping the block out of available memory”.
On the other hand, Wilson teaches,
An information handling system comprising: a processor;(fig 10:1000,1002; par 84)
a memory system communicatively coupled to the processor, the memory system comprising a plurality of rows and a plurality of spare rows for post-package repair (PPR) of the memory system;(fig 10:1004; par 84,85; fig 1:120; par 31 “The illustrated memory device 100 includes a control logic circuit 110, a storage element 112, a match logic circuit 114, a row enable circuit 116, a row decoder 118, a memory array 120 comprising data rows 122, row-based redundant rows 124, and page-based redundant rows 128, and a programmable element bank 126.”) and
one or more instructions stored in non-transitory computer readable media and configured to, when executed, cause the processor to,(fig 2; par 41 “FIG. 2 is a flow chart showing operations of a method 200 performed by a circuit in remapping memory addresses, according to an embodiment. … When executed, the non-transitory computer-readable storage can cause some or all of any of the method 200 to be performed.”) in response to a detection of a defect in a block of a particular row of the plurality of rows:(fig 8:820; par 72 “The memory device 100, in operation 820, determines, based on the address, that a first page for the address in a first row of the memory device 100 is defective.”; pages are defined in par 24 “Within a group of cells (e.g., a row or column of memory cells), subgroups may be referred to as a "page" of cells, such that each group comprises multiple pages. The soft post package repair may be performed at the group or page level, such that one entry … and another entry stored in the non-volatile memory of the apparatus may indicate that a defective address is for a single page of memory cells.”; Wilson’s page is a subgroup of a row and is analogous to applicant’s block of a particular row.)
track a number of defects in the block of the particular row;(fig 9:940; par 77 “If the row for the address is determined to be defective in operation 920, the memory device 100 further determines if the entire row for the address is defective or if the row is only partially defective (operation 940).”)
while the number of defects in the particular row is below a threshold, (fig 9:940; par 77 “If the row for the address is determined to be defective in operation 920, the memory device 100 further determines if the entire row for the address is defective or if the row is only partially defective (operation 940).”) perform software-based PPR memory healing to prevent use of the block by mapping the block out of available memory;(fig 8:830“BASED ON THE FIRST PAGE BEING DEFECTIVE, ACCESS A SECOND PAGE FROM A PAGE-BASED REDUNDANT ROW OF THE MEMORY DEVICE”; par 70; par 73 “Based on the first page being defective, the memory device 100 accesses a second page from a page-based redundant row of the memory device 100 (operation 830). For example, the redundant row decoder 415 of FIG. 4 may use an output from the SPPR circuit 410 along with the Redundant Address <N:0> signal from the programmable element bank 126 to select a page of a row-based redundant row.”) and
in response to the number of defects in the particular row being at or above the threshold, (fig 9:940,960; par 77 “If the row for the address is determined to be defective in operation 920, the memory device 100 further determines if the entire row for the address is defective or if the row is only partially defective (operation 940).”; par 77 “If the row is fully defective, a row-based redundant row for the address is accessed in operation 960.”; Par 81) perform software-based PPR memory healing to replace the particular row with one of the plurality of spare rows.( par 77 “If the row is fully defective, a row-based redundant row for the address is accessed in operation 960.”; Par 81 )
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Berman and Yamaguchi to incorporate the page level defect handling of Wilson. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Berman and Yamaguchi -- a need for a way to handle defective memory cells faster than hardware based PPR(Wilson par 2 “Memory cells of memory devices such as dynamic random access memories (DRAMs ), static RAMs (SRAMs ), flash memories, or the like can experience defects leading to errors and/or failures. In some cases, memory cells can be identified as defective (hereinafter "defective memory cells") during the manufacturing process, including after the memory device (e.g., a memory chip) has been packaged, such as in cases where the memory cells were not defective before the packaging process.” par 3,4 “Certain protocols exist for performing post package repair. Post package repair can involve blowing antifuses. Blowing an antifuse can be performed in an antifuse programming time, which can be on the order of 200 milliseconds (ms). In some applications, such a delay can undesirably impact performance of a memory.”) -- with Wilson providing a known method to solve a similar problem. Wilson provides “In an embodiment, soft post package repair can repair a memory device by remapping a defective address that had been previously remapped to a defective group of redundant memory cells.”(Wilson par 21)
Regarding claim 3, Berman, Yamaguchi, and Wilson teaches
The information handling system of Claim 1,
Berman further teaches,
wherein the threshold is equal to four defects per row.(fig 3:330; par 31 “The method of FIG. 3 further includes determining whether the written row is a bad row (step 330). In an exemplary embodiment, the determination is performed by reading data from the written row, comparing the received data against the read data to determine a number of errors, and determining that the row is bad when the number of errors exceeds a certain threshold.” Although Berman does not specifically set the threshold to four defects, Berman does set a certain threshold number, and it would be obvious to try whatever defect counts are needed.)
Regarding claim 4, Berman, Yamaguchi, and Wilson teaches
The information handling system of Claim 1,
Berman further teaches,
wherein the memory system is a dynamic random access memory (DRAM) system.(fig 1:126; par 23 “ In an exemplary embodiment, the controller 125 is configured to interface with the nonvolatile memory 126 or a DRAM (not shown) using a Double data rate (DDR) protocol.”)
Regarding claim 5, Berman, Yamaguchi, and Wilson teaches
The information handling system of Claim 1,
Berman further teaches,
wherein the plurality of rows are organized into a plurality of memory banks(fig 4A; par 24 “As shown in FIGS. 4A-4B, the main region 126-1 includes M blocks and the spare region 126-2 includes N blocks.”)
Regarding claims 7,9-11, they are the method that the system of claims 1,3-5 implement and are rejected for the same reasons.
Regarding claims 13,15-17, they are the non-transitory computer-readable medium containing instructions that the system of claims 1,3-5 implement and are rejected for the same reasons.
Claim(s) 2,8,14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210019082 A1 (Berman), US 20200111539 A1 (Yamaguchi), and US 20240071558 A1 (Wilson) as applied to claims 1,7,13 above, and further in view of US 20020196687 A1 (Sauvageau).
Regarding claim 2, Berman, Yamaguchi, and Wilson teaches
The information handling system of Claim 1,
Yamaguchi also teaches,
wherein the software-based PPR is also performed(fig 11B:S11; par 111 “Then, the BIOS 400 performs a monitoring setting of the row 112 to which the sPPR is applied to the row access monitoring unit 216 of the memory controller 210 (operation S11).”; par 6 “The PPR includes an hPPR and an sPPR. In the hPPR, a fuse switches a faulty row to a spare row. Therefore, the repair by the hPPR may not be undone. In the sPPR, software switches a faulty row to a spare row.”)
However, Berman, Yamaguchi, and Wilson do not specifically teach in response to a determination that no unused spare row is available.
On the other hand, Sauvageau teaches
A system for analyzing and repairing memory with different types of memory spares (par 16 “According to one aspect, a method for analyzing and repairing memory includes the step of determining if failed memory cells detected in at least a portion of memory must be repaired using only one of a number of types of memory spares or may be repaired using any of the number of types of memory spares.”)
wherein the software-based PPR is also performed in response to a determination that no unused spare row is available. (par 29 “If a first type of the plurality of types of memory spares is available, then the identified error is repaired with a spare of the first type. Otherwise, it is determined if a second complementary type of the plurality of types of memory spares is available. If a second type of the plurality of types of memory spares is available, then the identified error is repaired with a spare of the second type.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Berman, Yamaguchi, and Wilson to incorporate the response to a determination that no unused spare row is available of Sauvageau. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Berman, Yamaguchi, and Wilson -- a need for a solution for the issue of how to use spare memory cells efficiently (Sauvageau par 9 “Limitations associated with most conventional testers require that the repair information be generated and used dynamically. This can reduce the overall memory yield by using the redundant memory cells inefficiently. These limitations have also made memory testing a most expensive and time consuming process in the development of faster and denser memory.” Par 6 “Spare I/Os, if present, are capable of simultaneously replacing a number of columns associated with a particular 1/0 bit of memory. …”) -- with Sauvageau providing a known method to solve a similar problem. Sauvageau provides “According to one aspect, a method for analyzing and repairing memory includes the step of determining if failed memory cells detected in at least a portion of memory must be repaired using only one of a number of types of memory spares or may be repaired using any of the number of types of memory spares.”(Sauvageau par 16)
Regarding claim 8 it is the method that the system of claim 2 implements and is rejected for the same reasons.
Regarding claim 14 it is the non-transitory computer-readable medium containing instructions that the system of claim 2 implements and is rejected for the same reasons.
Claim(s) 6,12,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210019082 A1 (Berman), US 20200111539 A1 (Yamaguchi), and US 20240071558 A1 (Wilson) as applied to claims 1,7,13 above, and further in view of US 20230185659 A1 (Bao).
Regarding claim 6, Berman, Yamaguchi, and Wilson teaches
The information handling system of Claim 1,
Yamaguchi further teaches,
wherein the software-based PPR memory healing is performed(fig 11B:S11; par 111 “Then, the BIOS 400 performs a monitoring setting of the row 112 to which the sPPR is applied to the row access monitoring unit 216 of the memory controller 210 (operation S11).”; par 6 “The PPR includes an hPPR and an sPPR. In the hPPR, a fuse switches a faulty row to a spare row. Therefore, the repair by the hPPR may not be undone. In the sPPR, software switches a faulty row to a spare row.”) by a memory controller of the information handling system(fig 1:620; par 77 “The sPPR effect management unit 620 responds to the sPPR position information 621 based on the request from the PPR switching unit 411. The PPR switching unit 411 applies the sPPR using the sPPR position information 621. The sPPR effect management unit 620 manages information used to confirm the effect of the applied sPPR, and when the effect of the sPPR is confirmed, notifies the sPPR position information 621 to the hPPR data management unit 630.”)
However, Berman, Yamaguchi, and Wilson do not specifically teach wherein the software-based PPR memory healing is performed by an operating system of the information handling system.
On the other hand, Bao teaches
A memory fault handling apparatus that reduces a probability of a system breakdown caused by a memory fault(par 5 “Embodiments of this application provide a memory fault handling method and apparatus, to reduce a probability of system breakdown caused by a memory fault.”)
wherein the software-based PPR memory healing is performed by an operating system of the information handling system. (fig 2 par 69 “For example, FIG. 2 shows another memory repair method. As shown in FIG. 2, after identifying a corrected error, a CPU reports the corrected error to an upper-layer operating system (OS), and the OS counts the corrected error and determines a fault severity. After a quantity of corrected errors reaches a threshold, the OS delivers a command to trigger an error isolation mechanism (for example, page offline) in the OS, to isolate virtual space of a faulty region in the OS, and a memory address of the faulty region is no longer used.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Berman, Yamaguchi, and Wilson to incorporate the memory healing being performed by an operating system of Bao. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Berman, Yamaguchi, and Wilson -- a need for a solution for the issue of how to handle memory when failure rates increase over a threshold value(Bao par 3 “As a capacity of the DRAM memory increases, a basic failure rate increases. Generally, after a memory error occurs, an error correction algorithm such as error checking and correction (ECC) may be used to correct the error. However, frequent error correction affects system performance. In addition, when a memory fault becomes more serious, the error correction algorithm is overloaded, and a probability of an uncorrected error increases greatly. As a result, the uncorrected error may occur, causing system breakdown.”) -- with Bao providing a known method to solve a similar problem. Bao provides “Embodiments of this application provide a memory fault handling method and apparatus, to reduce a probability of system breakdown caused by a memory fault.”(Bao par 5)
Regarding claim 12 it is the method that the system of claim 6 implements and is rejected for the same reasons.
Regarding claim 18 it is the non-transitory computer-readable medium containing instructions that the system of claim 6 implements and is rejected for the same reasons.
Response to Arguments
Applicant’s arguments, see remarks pg. 8-9, filed 8/26/2025, with respect to the rejection(s) of claim(s) 1,7,13 under 35 U.S.C. 103 as being unpatentable over US 20210019082 A1 (Berman) in view of US 20200111539 A1 (Yamaguchi) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in under 35 U.S.C. 103 as being unpatentable over US 20210019082 A1 (Berman) in view of US 20200111539 A1 (Yamaguchi) and US 20240071558 A1 (Wilson).
With respect to the independent claims, the applicant has argued that US 20210019082 A1 (Berman) in view of US 20200111539 A1 (Yamaguchi) does not teach limitations “perform software-based PPR memory healing to prevent use of the block by mapping the block out of available memory;” and “wherein performing hardware-based PPR includes mapping the block back into available memory.”.
Regarding limitation “perform software-based PPR memory healing to prevent use of the block by mapping the block out of available memory;” The newly cited Wilson teaches in the cited (fig 8:830“BASED ON THE FIRST PAGE BEING DEFECTIVE, ACCESS A SECOND PAGE FROM A PAGE-BASED REDUNDANT ROW OF THE MEMORY DEVICE”; par 70; par 73 “Based on the first page being defective, the memory device 100 accesses a second page from a page-based redundant row of the memory device 100 (operation 830). For example, the redundant row decoder 415 of FIG. 4 may use an output from the SPPR circuit 410 along with the Redundant Address <N:0> signal from the programmable element bank 126 to select a page of a row-based redundant row.” pages are defined in par 24 “Within a group of cells (e.g., a row or column of memory cells), subgroups may be referred to as a "page" of cells, such that each group comprises multiple pages. The soft post package repair may be performed at the group or page level, such that one entry … and another entry stored in the non-volatile memory of the apparatus may indicate that a defective address is for a single page of memory cells.”; Wilson’s page is a subgroup of a row and is analogous to applicant’s block of a particular row.). The examiner interprets this as limitations “perform software-based PPR memory healing to prevent use of the block by mapping the block out of available memory;”
Regarding limitation “wherein performing hardware-based PPR includes mapping the block back into available memory.”, the examiner respectfully disagrees. Yamaguchi teaches, in the cited (par 6 “The PPR includes an hPPR and an sPPR. In the hPPR, a fuse switches a faulty row to a spare row. Therefore, the repair by the hPPR may not be undone.” par 83 “When Cancelcount exceeds a predetermined threshold, the sPPR effect management unit 620 notifies the hPPR data management unit 630 of the sPPR position information 621 and deletes the same information of the sPPR position information 621 and the sPPR position history 622.”. By replacing the faulty row with the spare row and deleting the position information from the software based PPR, we are essentially mapping the block back into available memory by deleting the software based re-routing that was done earlier and replacing the original faulty row.). Examiner interprets this as limitation “wherein performing hardware-based PPR includes mapping the block back into available memory.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210263646 A1 - Chin - memory controller determines an exact number of un-remapped redundant rows for a post-package repair. Same company Dell - 2021.
US 20220027229 A1 - Chao - post package repair failure memory location reporting system. Also Dell.
US 20150234707 A1 - Vogelsang - par 36 takes into account availability of repair resources like spare rows and ECC storage memory cells when deciding which repair mechanism to use.
US 20170098480 A1 - Wilson - soft post package repair in memory. Does address matching
US 20130254474 A1 - Berke - tracks and reports on units of memory systems that are in use
US 20170200511 A1 - Warnes - does post package repair (PPR) data in non-volatile memory
US 20150277790 A1 - Mozak - memory device mode registers that disable commands
US 20240330133 A1 - Shukla - row error count threshold. Filed mar 2024
US 20140351673 A1 - Ware - bit and data word level row repair. Threshold is based either on bit or multi-bit errors.
US 6480982 B1 - Chan - replaces DRAM when threshold number of errors found. Patented 2002.
US 20240385754 A1 - Wu - operating system provides repair handler, which performs the PPR.
US 20190108896 A1 - Berke - from the abstract: "communicate a command to the memory system requesting information associated with an availability of spare rows for post-package repair of the memory system and receive a response to the command, the command comprising the information associated with the availability" - also Dell, published 2019. Does not contain any error threshold limitations.
US 20160162196 A1 - Camp - retires the page after the first threshold is met, retires the region if the region has too many errors, and retires the larger region if the larger region has too many errors.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL XU whose telephone number is (571)272-5688. The examiner can normally be reached Monday-Friday 8:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571) 272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.X./Examiner, Art Unit 2113
/MARC DUNCAN/Primary Examiner, Art Unit 2113
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