Prosecution Insights
Last updated: October 23, 2026
Application No. 18/314,230

BIDIRECTIONAL POWER TRANSISTOR AND METHOD FOR PRODUCING A BIDIRECTIONAL POWER TRANSISTOR

Final Rejection §102
Filed
May 09, 2023
Priority
May 19, 2022 — DE 10 2022 205 006.1
Examiner
ANYA, IGWE U
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Robert Bosch GmbH
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
820 granted / 964 resolved
+17.1% vs TC avg
Minimal -4% lift
Without
With
+-3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
30 currently pending
Career history
998
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 964 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 3 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato (US 2009/0008676). PNG media_image1.png 272 608 media_image1.png Greyscale (Claim 1) Sato teaches a bidirectional power transistor, comprising: an AlGaN/GaN structure (10/3, paragraphs 48, 43); a first gate structure (28a); and a second gate structure (28b); a first p-doped region (18’a under 28a, paragraph 120); and a second p-doped region (18’a under 28b, paragraph 120); wherein a surface of the AlGaN/GaN structure has a depression having a first slanting sidewall (16a) and a second slanting sidewall (17a), the depression having a width that is greater than a height of the depression (fig. 13, at theta equals 60 degrees the height = √3a, and width = 2a, paragraph 54); wherein the first gate structure (28a) is situated on top of the first p-doped region (18’a) and the second gate structure (28b) is situated on top of the second p-doped region (18’a), wherein the first p-doped region is situated on top of the first slanting sidewall such that the first p-doped region is situated between the first gate structure and the first slanting sidewall, and wherein the second p-doped region is situated on top of the second slanting sidewall such that the second p-doped region is situated between the second gate structure and the second slanting sidewall. (Claim 2) Sato teaches wherein an angle of the first slanting sidewall and an angle of the second slanting sidewall each has a value ranging from 30 degrees to 60 degrees to a transverse direction (paragraph 54). (Claim 3) Sato teaches wherein the angle of the first slanting sidewall and the angle of the second slanting sidewall are equal in terms of their absolute value. (Claim 6) Sato teaches a method for producing a bidirectional power transistor, the method comprising the following steps: producing, along a transverse direction, a depression on an undoped GaN layer (10, paragraph 48), the depression having a first slanting sidewall (16) and a second slanting sidewall (7) on an undoped GaN layer and having a width that is greater than a height of the depression (fig. 13, at theta equals 60 degrees the height = √3a, and width = 2a, paragraph 54); applying an undoped AlGaN layer (18, paragraph 55) to the undoped GaN layer using epitaxy, thereby forming an AlGaN/GaN structure with a surface that has the depression; and applying a first p-doped region (18’a under 28a, paragraph 120) onto the first slanting sidewall; applying a second p-doped region (18’a under 28b, paragraph 120) onto the second slanting sidewall; applying a first gate structure (28a) onto the first p-doped region (18’a) such that the first p-doped region (18’a) is situated between the first slanting sidewall (16) and the first gate structure (28a); and applying a second gate structure (28b) onto the second p-doped region (18’a) such that the second p- doped region is situated between the second slanting sidewall (17) and the second gate structure (28b). Response to Arguments Applicant's arguments filed July 22, 2026 have been fully considered but they are not persuasive. Applicant argues: Sato fails to disclose the above-recited features of amended claim 1, including "wherein the first p-doped region is situated on top of the first slanting sidewall such that the first p-doped region is situated between the first gate structure and the first slanting sidewall." Reply: Sato teaches the "wherein the first p-doped region (18, paragraph 120) is situated on top of the first slanting sidewall (16) such that the first p-doped region (18) is situated between the first gate structure (28a) and the first slanting sidewall (16)." Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IGWE U ANYA/Primary Examiner, Art Unit 2891 October 3, 2026
Read full office action

Prosecution Timeline

May 09, 2023
Application Filed
Apr 10, 2026
Non-Final Rejection mailed — §102
Jul 22, 2026
Response Filed
Oct 06, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772472
Dual Gate Power Semiconductor Device and Method of Controlling a Dual Gate Power Semiconductor Device
3y 7m to grant Granted Oct 20, 2026
Patent 12745411
SEMICONDUCTOR DEVICE
3y 0m to grant Granted Sep 22, 2026
Patent 12740076
INTEGRATED CIRCUIT DEVICE
3y 0m to grant Granted Sep 15, 2026
Patent 12740391
CONTACT STRUCTURE, SEMICONDUCTOR DEVICE WITH THE SAME, AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Sep 15, 2026
Patent 12733206
VERTICAL SHIELDED GATE ACCUMULATION FIELD EFFECT TRANSISTOR
3y 6m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
81%
With Interview (-3.8%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 964 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month