DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species B, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 8, 2026.
Claim Objections
Claim 12 is objected to because of the following informalities:
Claim 12 recites the limitation “a sixth MOS transistor” in Line 3. The line is missing a semicolon.
Claim 12, Line 3 should recite: a sixth MOS transistor;.
Claim 17 recites the limitation “a first equalization unit” in Line 27. This appears to be a typo.
Claim 17 recites the limitation “ a first equalization unit” in Line 8.
For purpose of examination the limitation of Claim 17, Line 27 is interpreted as reciting: the first equalization unit.
Claim 17 recites the limitation “a resistor unit” in Line 29. This appears to be a typo.
Claim 17 recites the limitation “ a resistor unit” in Line 22.
For purpose of examination the limitation of Claim 17, Line 29 is interpreted as reciting: the resistor unit.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN 114530910A) in view of Kunimitsu (US 2021/0083331).
Claim 1: Zhang teaches a control circuit apparatus (200) for a battery system (Fig.3) comprising m battery units connected in series (201) (Par.37), the control circuit apparatus (200) comprising:
a first port (coupled to 208-209) (Fig.3);
a switch matrix network unit (203) (Fig.3) (Par.37);
a second equalization unit (2051-2053) (Par.43); and
a second port (coupled to the power supply 207) (Fig.3);
the first port (coupled to 208-209), the switch matrix network unit (601-604), the second equalization unit (2051-2053), and the second port (coupled to the power supply) are sequentially connected (Fig.6);
the first port (coupled to 208-209) is configured to connect to the m battery units (201) (Fig3) (Par.46);
the second port is configured to connect to a power supply (207) (Par.44);
the switch matrix network unit (203) (Par.37) is configured to:
connect a to-be-discharged battery unit in the m battery units (201) to the first equalization unit (2051-2053) (Par.68); and
connect a to-be-charged battery unit in the m battery units (201) to the second equalization unit (2051-2053) (Par.66); and
the second equalization unit is configured to charge the to-be-charged battery unit through the power supply (207) (Par.66).
Zhang does not explicitly teach a first equalization unit; the first equalization unit and the second equalization unit are connected in parallel; the first equalization unit is configured to discharge the to-be-discharged battery unit through a resistor unit.
Kunimitsu teaches a first equalization unit (13) (Fig.1) (Par.16); a second equalization unit (12) (Par.27); the first equalization unit (13) and the second equalization unit (12) are connected in parallel (Fig.1) (Par.32); the first equalization unit (13) is configured to discharge the to-be-discharged battery unit through a resistor unit (R1) (Par.23).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have had the teachings of Kunimitsu in the system of Zhang to have had improved power efficiency while preventing complication of component configuration (Par.42-44).
Claim 2: Zhang in view of Kunimitsu teach the limitations of claim 1 as disclosed above. Zhang teaches the second equalization unit (2051-2053) (Fig.3) comprising:
a transformer (Par.64);
a first switch unit (601)(Fig.6)(Par.43); a second switch unit (602); and a third switch unit (2054) (Par.62);
the transformer comprises a first primary-side winding (2051) and a first secondary-side winding (2052) (Par.43);
the first primary-side winding (2051) and the third switch unit (2054) are connected in series to form a first primary-side circuit (2051/2054) (Fig.3);
the first primary-side circuit (2051/2054) is connected to the second port (coupled to power supply 207) (Fig.3) (Par.44);
a first terminal of the first primary-side winding (2051) is connected to a positive electrode of the power supply (207) when the first primary-side circuit (2051/2054) forms a loop with the power supply (207) through the second port (Fig.3) (Par.44);
the first switch unit (601), the first secondary-side winding (2052), and the second switch unit (602) are sequentially connected in series to form a first secondary-side circuit (601/2052/602) (Fig.6);
the first secondary-side circuit (601/2052/602) is connected to the switch matrix network unit (203) (Figs.3 and 6) (Par.65-66);
and the second equalization unit (2051-2053) is configured to:
turn on the second switch unit (602) when a voltage of a first connection point between the first secondary-side circuit (601/2052/602) and the switch matrix network (203) unit is greater than a voltage of a second connection point between the first secondary-side circuit (601/2052/602) and the switch matrix network unit (203) (Par.68); and
alternately turn on the first switch unit (601) and the third switch unit (2054) (Par.67 and 69), the first connection point is connected to a first terminal of the first secondary-side winding (2052), and the first terminal of the first secondary-side winding (2052) and the first terminal of the first primary-side winding (2051) are a group of dotted terminals (Fig.6).
Claim 3: Zhang in view of Kunimitsu teach the limitations of claim 2 as disclosed above. Zhang teaches the first switch unit (601) comprising a first field-effect MOS transistor, and the first MOS transistor is connected to the first connection point through a drain (Par.18 and 63).
Claim 4: Zhang in view of Kunimitsu teach the limitations of claim 2 as disclosed above. Zhang teaches the second switch unit (602) comprising a first diode (Fig.5) (Par.28), and a positive electrode of the first diode is connected to the first connection point (Par.63) (Fig.6).
Claim 5: Zhang in view of Kunimitsu teach the limitations of claim 2 as disclosed above. Zhang teaches the third switch unit (2054) comprising a second MOS transistor, and a drain of the second MOS transistor is connected to the positive electrode of the power supply through the second port (Par.18 and 63) (Fig.6).
Claim 6: Zhang in view of Kunimitsu teach the limitations of claim 2 as disclosed above. Zhang teaches the second equalization unit (2051-2053) further comprising:
a fourth switch unit (603); and a fifth switch unit (604) (Par.62);
the transformer further comprising a second secondary-side winding (2053) (Par.43);
the fourth switch unit (603), the second secondary-side winding (2053), and the fifth switch unit (604) are sequentially connected in series to form a second secondary-side circuit (603/2053/604) (Fig.6);
the second secondary-side circuit (603/2053/604) is connected to the switch matrix network unit (203) (Par.66);
the first connection point (209) is between the second secondary-side circuit (603/2053/604) and the switch matrix network unit (203) (Fig.6);
the second connection point (208) is between the second secondary-side circuit (603/2053/604) and the switch matrix network unit (203) (Fig.6);
a first terminal of the second secondary-side winding (2053) and the first terminal of the first primary-side winding (2051) are a group of dotted terminals (Fig.6);
the second connection point (208) is connected to the first terminal of the first secondary-side winding (2052) (Fig.6); and
the second equalization unit (2051-2053) is further configured to:
when a voltage difference between the first connection point (209) and the second connection point (208) is less than zero, turn on the fifth switch unit (604) (Par.66), and
alternately turn on the fourth switch unit (603) and the third switch unit (2054) (Par.66 and 68).
Claim 7: Zhang in view of Kunimitsu teach the limitations of claim 6 as disclosed above. Zhang teaches the fourth switch unit (603) comprising a third MOS transistor (Par.63), and a drain of the third MOS transistor is connected to the second connection point (208) (Par.18 and 52).
Claim 8: Zhang in view of Kunimitsu teach the limitations of claim 6 as disclosed above. Zhang teaches the fifth switch unit (604) comprising a second diode (Fig.5) (Par.28), and a positive electrode of the second diode is connected to the second connection point (208) (Par.52 and 63) (Figs.5-6).
Claim 11: Zhang in view of Kunimitsu teach the limitations of claim 1 as disclosed above. Zhang does not explicitly teach the first equalization unit comprising: a seventh switch unit; and the resistor unit; the seventh switch unit and the resistor unit are connected in series; the first equalization unit is connected to the switch matrix network unit; and the first equalization unit is configured to turn on the seventh switch unit.
Kunimitsu teaches the first equalization unit (13) (Fig.1) comprising: a seventh switch unit (S5); and the resistor unit (R1); the seventh switch unit (S5) and the resistor unit (R1) are connected in series (Fig.1) (Par.23);
the first equalization unit (13) is connected to a switch matrix network unit (S10-S19) (Par.16) (Fig.1); and the first equalization unit (13) is configured to turn on the seventh switch unit (S5) (Par.40).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have had the teachings of Kunimitsu in the system of Zhang to have had improved power efficiency during battery equalization while preventing complication of component configuration (Par.42-44).
Claim 12: Zhang in view of Kunimitsu teach the limitations of claim 11 as disclosed above. Zhang does not explicitly teach the seventh switch unit comprising: a fifth MOS transistor; and a sixth MOS transistor; a source of the fifth MOS transistor is connected to a source of the sixth MOS transistor, or a drain of the fifth MOS transistor is connected to a drain of the sixth MOS transistor.
Zhang discloses a switch unit (Fig.5) comprising: a fifth MOS transistor (501); and a sixth MOS transistor (502); a source of the fifth MOS transistor (501) is connected to a source of the sixth MOS transistor (502) (Par.18 and 52).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have had the seventh switch unit in the combination of Zhang in view of Kunimitsu have had a configuration of a source of a fifth MOS transistor connected to a source of a sixth MOS transistor to have had allowed for bidirectional conduction (Par.18) as taught in Zhang.
Claim 13: Zhang in view of Kunimitsu teach the limitations of claim 1 as disclosed above. Zhang teaches the apparatus further comprising:
a voltage sampling circuit unit (206) (Fig.3), the voltage sampling circuit unit (206) separately forming a loop with the m battery units (201) through the switch matrix network unit (203) (Fig.3);
the switch matrix network unit (203) is further configured to connect a to-be-sampled battery unit in the m battery units (201) to the voltage sampling circuit (206) (Par.37); and
the voltage sampling circuit unit (206) is configured to sample the to-be-sampled battery unit to obtain a voltage value of the to-be-sampled battery unit (Par.37), wherein the voltage value is used to determine whether the to-be-sampled battery unit is the to-be-charged battery unit or the to-be-discharged battery unit (Par.45 and 57-58).
Claim 14: Zhang in view of Kunimitsu teach the limitations of claim 13 as disclosed above. Zhang the voltage sampling circuit unit (206) (Fig.4) comprising:
a first resistor (401); a second resistor (402); a third resistor (403); and a fourth resistor (404) (Par.49);
the first resistor (401), the second resistor (402), the third resistor (403), and the fourth resistor (404) are connected in series (Figs.3-4);
an end connecting the third resistor (403) and the fourth resistor (404) is grounded (Fig.4);
a third port is between the first resistor (401) and the third resistor (403) (Fig.4);
a fourth port is between the second resistor (402) and the fourth resistor (404) (Fig.4); and
the third port and the fourth port are configured to output an electrical signal for determining the voltage value of the to-be-sampled battery unit (Par.49; Via 2061).
Claim 15: Zhang in view of Kunimitsu teach the limitations of claim 13 as disclosed above. Zhang teaches the apparatus (Fig.3) further comprising:
a capacitor control unit (204), the capacitor control unit (204) comprising a capacitor and an eighth switch unit, and the capacitor and the eighth switch unit are connected in series (Par.42);
the eighth switch unit is turned off when the to-be-sampled battery unit in the m battery units (201) needs to be sampled, and turned on when the to-be-charged battery unit needs to be charged (Par.37 and 42); and
the capacitor control unit (204) and the second equalization unit (2051-2053) are connected in parallel (Fig.3).
Claim 16: Zhang in view of Kunimitsu teach the limitations of claim 15 as disclosed above. Zhang does not explicitly teach the eighth switch unit comprising: a seventh MOS transistor and an eighth MOS transistor; and a source of the seventh MOS transistor is connected to a source of the eighth MOS transistor, or a drain of the seventh MOS transistor is connected to a drain of the eighth MOS transistor.
Zhang discloses a control switch unit (Fig.5) comprising: a seventh MOS transistor (501); and an eight MOS transistor (502); a source of the seventh MOS transistor (501) is connected to a source of the eight MOS transistor (502) (Par.18 and 52).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have had the eight switch unit (control switch included in 204) in the system of Zhang have had a configuration that allowed for bidirectional conduction (Par.18) as taught in Zhang.
Claim 17: Zhang teaches a battery management system for a battery system including m battery units connected in series, the battery management system comprising:
a controller (202) (Par.37); and
a control circuit apparatus (200) connected to the controller (202), the control circuit apparatus (200) comprising:
a first port (coupled to 208-209) (Fig.3);
a switch matrix network unit (203) (Fig.3) (Par.37);
a second equalization unit (2051-2053) (Par.43); and
a second port (coupled to the power supply 207) (Fig.3);
the first port (coupled to 208-209), the switch matrix network unit (601-604), the second equalization unit (2051-2053), and the second port (coupled to the power supply) are sequentially connected (Fig.6);
the first port (coupled to 208-209) is configured to connect to the m battery units (201) (Fig3) (Par.46);
the second port is configured to connect to a power supply (207) (Par.44);
the switch matrix network unit (203) (Par.37) is configured to:
connect a to-be-discharged battery unit in the m battery units (201) to the first equalization unit (2051-2053) (Par.68); and
connect a to-be-charged battery unit in the m battery units (201) to the second equalization unit (2051-2053) (Par.66); and
the second equalization unit is configured to charge the to-be-charged battery unit through the power supply (207) (Par.66).
the controller (202) configured to output a second control signal to the control circuit apparatus, the second control signal controlling the switch matrix network unit (203) to connect a to-be-charged battery unit to a second equalization unit (2051-2053) in the control circuit apparatus, the second control signal further controlling the second equalization unit (2051-2053) to charge the to-be-charged battery unit through a power supply (207) (Par.65-66); and
the control circuit apparatus (200) is configured to:
receive the second control signal (Par.64-65); connect the to-be-charged battery unit to the second equalization unit (2051-2053) through the switch matrix network unit (203) under control of the second control signal (Par.64-66); and charge the to-be-charged battery unit through the power supply (207) under control of the second control signal (Par.66).
Zhang does not explicitly teach a first equalization unit; the first equalization unit and the second equalization unit are connected in parallel; the first equalization unit is configured to discharge the to-be-discharged battery unit through a resistor unit; the controller is configured to output a first control signal to the control circuit apparatus, the first control signal controlling the switch matrix network unit to connect a to-be-discharged battery unit to a first equalization unit in the control circuit apparatus, the first control signal further controlling the first equalization unit to discharge the to-be-discharged battery unit through a resistor unit; the control circuit apparatus is configured to: receive the first control signal; connect the to-be-discharged battery unit to the first equalization unit through the switch matrix network unit under control of the first control signal; and discharge the to-be-discharged battery unit through the resistor unit under control of the first control signal.
Kunimitsu teaches a controller (50) (Fig.1) (Par.16); a first equalization unit (13) (Fig.1) (Par.16); a second equalization unit (12) (Par.27); the first equalization unit (13) and the second equalization unit (12) are connected in parallel (Fig.1) (Par.32); the first equalization unit (13) is configured to discharge the to-be-discharged battery unit through a resistor unit (R1) (Par.23);
the controller (50) is configured to output a first control signal to a control circuit apparatus (10), the first control signal controlling a switch matrix network unit (S10-S19) to connect a to-be-discharged battery unit to the first equalization unit (13) in the control circuit apparatus (10) (Par.34), the first control signal further controlling the first equalization unit (13) to discharge the to-be-discharged battery unit through a resistor unit (R1) (Par.51-52);
the control circuit apparatus (10) is configured to: receive the first control signal; connect the to-be-discharged battery unit to the first equalization unit (13) through the switch matrix network unit (S10-S19) under control of the first control signal (Par.34); and discharge the to-be-discharged battery unit through the resistor unit (R1) under control of the first control signal (Par.40).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have had the teachings of Kunimitsu in the system of Zhang to have had improved power efficiency during battery equalization while preventing complication of component configuration (Par.42-44).
Claim 18: Zhang in view of Kunimitsu teach the limitations of claim 17 as disclosed above. Zhang teaches the second equalization unit (2051-2053) (Fig.3) comprising:
a transformer (Par.64);
a first switch unit (601)(Fig.6)(Par.43); a second switch unit (602); and a third switch unit (2054) (Par.62);
the transformer comprises a first primary-side winding (2051) and a first secondary-side winding (2052) (Par.43);
the first primary-side winding (2051) and the third switch unit (2054) are connected in series to form a first primary-side circuit (2051/2054) (Fig.3);
the first primary-side circuit (2051/2054) is connected to the second port (coupled to power supply 207) (Fig.3) (Par.44);
a first terminal of the first primary-side winding (2051) is connected to a positive electrode of the power supply (207) when the first primary-side circuit (2051/2054) forms a loop with the power supply (207) through the second port (Fig.3) (Par.44);
the first switch unit (601), the first secondary-side winding (2052), and the second switch unit (602) are sequentially connected in series to form a first secondary-side circuit (601/2052/602) (Fig.6);
the first secondary-side circuit (601/2052/602) is connected to the switch matrix network unit (203) (Figs.3 and 6) (Par.65-66);
and the second equalization unit (2051-2053) is configured to:
turn on the second switch unit (602) when a voltage of a first connection point between the first secondary-side circuit (601/2052/602) and the switch matrix network (203) unit is greater than a voltage of a second connection point between the first secondary-side circuit (601/2052/602) and the switch matrix network unit (203) (Par.68); and
alternately turn on the first switch unit (601) and the third switch unit (2054) (Par.67 and 69), the first connection point is connected to a first terminal of the first secondary-side winding (2052), and the first terminal of the first secondary-side winding (2052) and the first terminal of the first primary-side winding (2051) are a group of dotted terminals (Fig.6).
Claim 19: Zhang in view of Kunimitsu teach the limitations of claim 18 as disclosed above. Zhang teaches the first switch unit (601) comprising a first field-effect MOS transistor, and the first MOS transistor is connected to the first connection point through a drain (Par.18 and 63).
Claim 20: Zhang in view of Kunimitsu teach the limitations of claim 18 as disclosed above. Zhang teaches the second switch unit (602) comprising a first diode (Fig.5) (Par.28), and a positive electrode of the first diode is connected to the first connection point (Par.63) (Fig.6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHALI ALEJANDRA TORRES RUIZ whose telephone number is (571)270-1262. The examiner can normally be reached M-F 10:00am-6:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julian D Huffman can be reached at 571-272-2147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHALI A TORRES RUIZ/ Examiner, Art Unit 2859
/JULIAN D HUFFMAN/ Supervisory Patent Examiner, Art Unit 2859
