Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/02/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-7, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable by Hegblom (U.S. Patent No. 10,205,303) in view of Yokozeki et al. (U.S. Patent Application No. 2025/0070531), hereinafter Yokozeki, in view of Wang et al., (U.S. Patent Application No. 2022/0013992) hereinafter Wang.
Regarding Claim 1, Hegblom teaches a vertical-cavity surface-emitting laser (VCSEL) array (Col. 2, lines 28-30) comprising : a substrate (Fig. 1A, “104”; Col. 4, lines 5-11) a first metal layer (Col. 4, lines 19-26; Fig 1A, “102”), the first metal layer including a plurality of first electrodes (Col. 2, lines 33-37, “cathode layers”); an epitaxial region (Fig. 1A, “106”; Col. 4, lines 5-11) over the first metal layer; and a second metal layer over the epitaxial region (Fig. 1A, “122”), the second metal layer including a plurality of second electrodes (Col. 2, lines 33-37, “anode layers”). Hegblom does not teach: a wafer bonding layer over the substrate; that the first metal layer is on or within the wafer bonding layer; the epitaxial region is over the wafer bonding layer, the epitaxial region being bonded to the wafer bonding layer; the plurality of first electrodes and the plurality of second electrodes form a plurality of matrix addressable subarrays of the VCSEL array, each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters.
Yokozeki teaches: a wafer bonding layer (paragraph [0148], “solder or Ag paste”) over the substrate (paragraph [0148]); that the first metal layer (paragraph [0148], “102”) is on or within the wafer bonding layer (paragraph [0148], “102” is on the “solder or Ag paste” above the substrate “101”); the epitaxial region (Fig. 1A, portion of device above “102”) is over the wafer bonding layer (Fig. 1A, portion of device above “102” is above the wafer bonding layer between “102” and “101”). It can be necessarily understood to someone having ordinary skill that the solder or Ag paste bonding the substrate and epitaxial region as taught by Yokozeki (paragraph [0148]) is a wafer bonding layer, in the sense that the device as taught by Yokozeki is formed on a single wafer which comprises the substrate (paragraph [0140]). It would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: utilize a wafer bonding layer over the substrate as taught by Yokozeki in the device of Hegblom, for the benefit of securing a multilayer epitaxial wafer structure to the substrate; have the first metal layer on or within the wafer bonding layer as taught by Yokozeki as taught by Hegblom, the benefit of maximizing electrical connectivity between the epitaxial region and the first metal layer and to minimize necessary surface preparation to only one side of the substrate; have the epitaxial region over the wafer bonding layer, as taught by Yokozeki in the device of Hegblom, for the benefit of securing the epitaxial region to a suitable carrier substrate for the VCSEL array. It can be necessarily understood to someone of ordinary skill that the epitaxial region is bonded to the wafer bonding layer in the device of Hegblom and Yokozeki, in the sense that the plurality of first electrodes as taught by Hegblom is in contact with part but not all of the substrate, such that in between the plurality of first electrodes a portion of the epitaxial region is in contact with the wafer.
Hegblom and Yokozeki do not teach: the plurality of first electrodes and the plurality of second electrodes form a plurality of matrix addressable subarrays of the VCSEL array, each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters.
Wang teaches: the plurality of first electrodes (Fig. 9, “902” and “904”) and the plurality of second electrodes (Fig. 9, “901” and “903”) form a plurality of matrix addressable subarrays (Fig. 9, see “909” connecting “VCSEL 1” and “VCSEL 3” by , subarray of “VCSEL 2”) of the VCSEL array (paragraph [0004]), each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters (paragraph [0035]; subarray connecting “VCSEL 1” and “VCSEL 3” has “VCSEL 1” and “VCSEL 3” as more than one emitter, the subarray of “VCSEL 2” has “VCSEL 2 as one emitter; Fig. 9). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: have the plurality of first electrodes and the plurality of second electrodes form a plurality of matrix addressable subarrays of the VCSEL array, each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters as taught by Wang in the device of Hegblom and Yokozeki, for the benefit of selecting and connecting VCSELs with an irregular pattern as taught by Wang (paragraph [0035]).
Regarding Claim 2, Hegblom, Yokozeki, and Wang teach the device of Claim 1.
Yokozeki further teaches that the wafer bonding layer comprises an adhesive bonding material (paragraph [0148]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an adhesive bonding material for the wafer bonding layer, for the benefit of bonding at lower temperature conditions.
Regarding Claim 3, Hegblom, Yokozeki, and Wang teach the device of Claim 1.
Yokozeki further teaches the wafer bonding layer comprises a solder bonding material (paragraph [0148]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize a solder bonding material for the wafer bonding layer, for the benefit of allowing heat dissipation of the epitaxial region into the wafer bonding layer.
Regarding Claim 5, Hegblom, Yokozeki, and Wang teach the device of Claim 1.
Hegblom further teaches the epitaxial region comprises an isolation region (Fig. 1a, “118”) associated with separating a second electrode of the plurality of second electrodes (Fig. 1a, see “122” on left of “118” in center) from a second electrodes of the plurality of second electrodes (Fig. 1a, see “122” on right of “118” in center). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an isolation region associated with separating a first electrode of the plurality of first electrodes from a second electrodes of the plurality of first electrodes, for the benefit of keeping the respective first electrode of each VCSEL in the device of Hegblom, Yokozeki, and Wang electrically connected to only its respective VCSEL.
Regarding Claim 6, Hegblom, Yokozeki, and Wang teach the device of Claim 5.
Hegblom further teaches an isolation region (Fig. 1b, “116” ) is an ion implantation region (fifth column, lines 36-39). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an ion implanted region, for the benefit preventing current leakage between a first electrode of the plurality of first electrodes from a second electrodes of the plurality of first electrodes in the device of Hegblom, Yokozeki, and Wang.
Regarding Claim 7, Hegblom, Yokozeki, and Wang teach the device of Claim 5.
Hegblom further teaches an isolation region (Fig. 1a, “118”) is an etched region (Col. 5, lines 64-67). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an etched isolation region, for the benefit of physically separating a first electrode of the plurality of first electrodes from a second electrodes of the plurality of first electrodes in the device of Hegblom, Yokozeki, and Wang.
Regarding Claim 9, Hegblom, Yokozeki, and Wang teach the device of Claim 1.
As taught in Claim 1 by Hegblom, the plurality of first electrodes is a plurality of cathodes (Col. 2, lines 33-37, “cathode layers”) and the plurality of second electrodes is a plurality of anodes (Col. 2, lines 33-37, “anode layers”).
Regarding Claim 10, Hegblom, Yokozeki, and Wang teach the device of Claim 1.
Hegblom further teaches the VCSEL array is a top-emitting VCSEL array (Col. 5, lines 55-58).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable by Hegblom, Yokozeki, and Wang, in view of Furuse (U.S. Patent Application No. 2025/0202187).
Regarding Claim 4, Hegblom, Yokozeki, and Wang teach the device of Claim 1. Hegblom, Yokozeki, and Wang do not teach: the wafer bonding layer comprises a thermocompression material.
Furuse teaches the wafer bonding layer comprises a thermocompression material (paragraph [0082]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize a thermocompression material for the wafer bonding layer as taught by Furuse in the device of Hegblom, Yokozeki, and Wang, for the benefit of achieving a flatter direct bond as taught by Furuse (paragraph [0086]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable by Hegblom, Yokozeki, and Wang, in view of Halbritter et al. (U.S. Patent Application No. 2019/0245326), hereinafter Halbritter.
Regarding Claim 8, Hegblom, Yokozeki, and Wang teach the device of Claim 1. Hegblom, Yokozeki, and Wang do not teach: the VCSEL array further includes an isolation layer between the substrate and the wafer bonding layer.
Halbritter teaches: the VCSEL array (paragraph [0103]) further includes an isolation layer (Fig. 1A, “34”; paragraph [0061]; paragraph [0068], “dielectric”) between the substrate (Fig. 1A, “32”; paragraph [0060], “sapphire”; paragraph [0061], “34” on “32”) and the wafer bonding layer (Fig. 1A, “35”; paragraph [0061], “35” on “34” on “32”). It can be necessarily understood to someone having ordinary skill in the art that a sapphire substrate is a wafer, in the sense that sapphire substrates are thin and epitaxially grown. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: include an isolation layer between the substrate and wafer bonding layer, for the benefit of absorbing electromagnetic, ion, and/or thermal radiation from bonding as a buffer for the substrate in the device of Hegblom, Yokozeki, and Wang.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable by Yokozeki, in view of Hegblom, in view of Wang.
Regarding Claim 11, Yokozeki teaches a method (paragraph [0036]), comprising: forming an epitaxial region on a first substrate (Fig. 7A, “SB”; paragraph [0141]; Fig. 5A); forming a first metal layer on a first side of the epitaxial region (Fig. 8A, “102”, first side below “103”, paragraph [0114], paragraph [0147]), bonding (paragraph [0148]), using a wafer bonding material (paragraph [0148], “solder or Ag paste”), the first metal layer (Fig. 8B, “102”) and the first side of the epitaxial region (Fig. 8B, see side below “103”) to a second substrate (Fig. 8B, “101”) such that the first metal layer is between the first side of the epitaxial region and the second substrate (Fig. 8B, see “102” between “101” and 103”, “104”, “105”, “106” “107” “108”); removing the first substrate (paragraph [0149]) to expose a portion of a second side of the epitaxial region (Fig. 9; top of “108”); and forming a second metal layer (Fig. 9, “108”) on the second side of the epitaxial region (Fig. 9, “108” on top of “109”). Yokozeki does not teach: the first metal layer including a plurality of first electrodes; the second metal layer including a plurality of second electrodes; the plurality of first electrodes and the plurality of second electrodes form a plurality of matrix addressable subarrays of an emitter array, each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters.
Hegblom teaches the first metal layer including a plurality of first electrodes (Col. 2, lines 34-37, “cathode layers”); the second metal layer including a plurality of second electrodes (Col. 2, lines 34-37, “anode layers”). Therefore, to would have been obvious to someone having ordinary skill in the art to: have the first metal layer include a plurality of first electrodes as taught by Hegblom in the method of Yokozeki, for the benefit for the benefit of providing each VCSEL with a first electrode that is separate from those of another adjacent VCSEL as taught by Hegblom (Col. 2, lines 34-37); have the second metal layer include a plurality of second electrodes in the method of Yokozeki, for the benefit of providing each VCSEL with a second electrode that is separate from those of another adjacent VCSEL as taught by Hegblom (Col. 2, lines 34-37). Yokozeki and Hegblom do not teach: the plurality of first electrodes and the plurality of second electrodes form a plurality of matrix addressable subarrays of an emitter array, each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters.
Wang teaches: the plurality of first electrodes (Fig. 9, “902” and “904”) and the plurality of second electrodes (Fig. 9, “901” and “903”) form a plurality of matrix addressable subarrays (Fig. 9, see “909” connecting “VCSEL 1” and “VCSEL 3” by , subarray of “VCSEL 2”) of the VCSEL array (paragraph [0004]), each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters (paragraph [0035]; subarray connecting “VCSEL 1” and “VCSEL 3” has “VCSEL 1” and “VCSEL 3” as more than one emitter, the subarray of “VCSEL 2” has “VCSEL 2 as one emitter; Fig. 9). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: have the plurality of first electrodes and the plurality of second electrodes form a plurality of matrix addressable subarrays of the VCSEL array, each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters as taught by Wang in the method of Yokozeki and Hegblom, for the benefit of selecting and connecting VCSELs with an irregular pattern as taught by Wang (paragraph [0035]).
Regarding Claim 12, Yokozeki, Hegblom, and Wang teach the method of Claim 11.
Yokozeki further teaches: the wafer bonding layer comprises at least one of an adhesive bonding material, a solder bonding material, or a thermocompression bonding material (paragraph [0148]).
Regarding Claim 13, Yokozeki, Hegblom, and Wang teach the method of Claim 11.
Hegblom further teaches: forming an isolation region (Fig. 1a, “118”) associated with separating a first electrode of the plurality of second electrodes (Fig. 1a, see “122” on left of “118” in center) from a second electrodes of the plurality of second electrodes (Fig. 1a, see “122” on right of “118” in center). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: form an isolation region associated with separating a first electrode of the plurality of first electrodes from a second electrodes of the plurality of first electrodes as taught by Hegblom in the method of Yokozeki, Hegblom, and Wang, for the benefit of keeping the respective first electrode of each VCSEL electrically connected to only its respective VCSEL.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Higa et al. WO 2022/130825 A1
Watanabe et al. WO 2022/044886 A1
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/J.K.M./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828