Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Examiner acknowledges the amending of claims 1 and 11.
The Examiner acknowledges the cancellation of claims 14-20.
The examination acknowledges the addition of claims 21-27.
Response to Arguments
The Applicant has argued that the claim amendments overcome the previous rejection.
The Examiner agrees. However, a new grounds of rejection necessitated by the claim amendments has been issued, as presented below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Schleuning et al. (U.S. Patent Application No. 2022/0137230 A1), hereinafter Schleuning, in view of Zou et al. (U.S. Patent Application No. 2019/0386454 A1), hereinafter Zou.
Regarding Claim 1, Schleuning teaches a vertical-cavity surface-emitting laser array (Fig. 5A, “500”) comprising: a substrate (Fig. 5A, “502”); a first metal layer (Fig. 5B, “504”, “505”), the first metal layer including a plurality of first electrodes (Fig. 5A, “504”); an epitaxial region (Fig. 5B, “508”) over the first metal layer (Fig. 5B, “508” over “504” and “505”); and a second metal layer (Fig. 5B, “506”) over the epitaxial region (Fig. 5B, see portion of “506” above “508”), the second metal layer including a plurality of second electrodes (Fig. 5A, “506”), wherein the plurality of first electrodes and the plurality of second electrodes are arranged to provide a plurality of row electrodes (Fig. 5A, see “506” defining 5 rows; paragraph [0152], “row-anode”) and a plurality of column electrodes (Fig. 5A, see “504” defining 4 columns; paragraph [0152], “column-cathode”), the plurality of row electrodes and the plurality of column electrodes intersecting to form a plurality of matrix addressable subarrays of the vertical-cavity surface-emitting laser array (paragraph [0152], “individual addressability of each VCSEL”), each matrix addressable subarray being disposed at an intersection between one of the row electrodes and one of the column electrodes (Fig. 5A, see each “512” at intersection of each “504” and each “506”), and each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters (Fig. 5A, one “512” at each intersection of “504” and “506”; paragraph [0152], “VCSELs”). Schleuning does not teach: a wafer bonding layer over the substrate; that the first metal layer on or within the wafer bonding layer; that the epitaxial region is over the first metal layer and the wafer bonding layer, the epitaxial region being bonded to the wafer bonding layer.
Zou teaches: a wafer bonding layer (Fig. 3, “215”, see explanation below) over the substrate (Fig. 3, see “214” over “213”); that the first metal layer (Fig. 1, “214”) is on or within the wafer bonding layer (Fig. 3, see “214” on “215”); that the epitaxial region is over the first metal layer (Fig. 3, see “200r”, “200g”, “200b” over “214”) and the wafer bonding layer (Fig. 3, see “200r”, “200g”, “200b” over “215”), the epitaxial region being bonded to the wafer bonding layer (Fig. 3, see “200r”, “200g”, “200b” bonded to “215”). It can be necessarily understood to someone having ordinary skill in the art that the bonding layer as disclosed by Zou is a wafer bonding layer, in the sense that the substrate as taught by Zou (paragraph [0038], “silicon substrate”) is a wafer structure. Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: utilize the substrate as taught by Zou in the device of Schleuning, for the benefit of providing driving circuitry (paragraph [0038]); have the wafer bonding layer as taught by Zou in the device of Schleuning, for the benefit of securing the lower metal layer as taught by Schleuning to the substrate as taught by Zou.
Regarding Claim 5, Schleuning and Zou teach the device of Claim 1. Schleuning further teaches: the epitaxial region comprises an isolation region (Fig. 5B, “503”) associated with isolating a first electrode of the plurality of first electrodes from a second electrode of the plurality of first electrodes (paragraph [0136], “electrically isolated”).
Regarding Claim 9, Schleuning and Zou teach the device of Claim 1. Schleuning further teaches: the plurality of first electrodes (Fig. 5A, “504”) is a plurality of cathodes (paragraph [0140]) and the plurality of second electrodes (Fig. 4, “506”) is a plurality of anodes (paragraph [0140)].
Regarding Claim 10, Schleuning and Zou teach the device of Claim 1. Schleuning further teaches: the VCSEL array is a top-emitting VCSEL array (paragraph [0142]).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Schleuning and Zou, in view of Yokozeki et al. (U.S. Patent Application No. 2025/0070531 A1).
Regarding Claim 2, Schleuning and Zou teach the device of Claim 1. Schleuning and Zou do not teach: that the wafer bonding layer comprises an adhesive bonding material.
Yokozeki teaches: that the wafer bonding layer comprises an adhesive bonding material (paragraph [0148]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an adhesive bonding material for the wafer bonding layer as taught by Yokozeki in the device of Schleuning and Zou, for the benefit of bonding at lower temperature conditions.
Regarding Claim 3, Schleuning and Zou teach the device of Claim 1. Schleuning and Zou do not teach: the wafer bonding layer comprises a solder bonding material.
Yokozeki teaches: the wafer bonding layer comprises a solder bonding material (paragraph [0148]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize a solder bonding material for the wafer bonding layer as taught by Yokozeki in the device of Schleuning and Zou, for the benefit of allowing heat dissipation of the epitaxial region into the wafer bonding layer.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Schleuning and Zou, in view of Furuse (U.S. Patent Application No. 2025/0202187).
Regarding Claim 4, Schleuning and Zou teach the device of Claim 1. Schleuning and Zou do not teach: the wafer bonding layer comprises a thermocompression material.
Furuse teaches: the wafer bonding layer comprises a thermocompression material (paragraph [0082]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize a thermocompression material for the wafer bonding layer as taught by Furuse in the device of Schleuning and Zou, for the benefit of achieving a flatter direct bond as taught by Furuse (paragraph [0086]).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Schleuning and Zou, in view of Hegblom et al. (U.S. Patent No. 10,205,303), hereinafter Hegblom 1.
Regarding Claim 6, Schleuning and Zou teach the device of Claim 1. Schleuning teaches: an isolation region (Fig. 5A, “503”). Schleuning and Zou do not teach: that the isolation region is an ion implantation region.
Hegblom1 teaches an isolation region (Fig. 1b, “116” ) is an ion implantation region (fifth column, lines 36-39). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to utilize an ion implanted region as taught by Hegblom1 in the device of Schleuning and Zou, as Hegblom1 demonstrates the ion implanted region is suitable for the purpose of the isolation region to electrically isolate adjacent electrodes. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Regarding Claim 7, Schleuning and Zou teach the device of Claim 1. Schleuning teaches: an isolation region (Fig. 5A, “503”). Schleuning and Zou do not teach: that the isolation region is an etched region.
Hegblom1 teaches: an isolation region (Fig. 1a, “118”) is an etched region (Col. 5, lines 64-67). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an etched isolation region as taught by Hegblom1 in the device of Schleuning and Zou, for the benefit of physically separating a first electrode of the plurality of first electrodes from a second electrode of the plurality of first electrodes.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Schleuning and Zou in view of Halbritter et al. (U.S. Patent Application No. 2019/0245326 A1), hereinafter Halbritter.
Regarding Claim 8, Schleuning and Zou teach the device of Claim 1. Schleuning teaches: an isolation layer (Fig. 5A, “503”). Schleuning and Zou do not teach: that the isolation layer is between the substrate and wafter bonding layer.
Halbritter teaches: the VCSEL array (paragraph [0103]) further includes an isolation layer (Fig. 1A, “34”; paragraph [0061]; paragraph [0068], “dielectric”) between the substrate (Fig. 1A, “32”; paragraph [0060], “sapphire”; paragraph [0061], “34” on “32”) and the wafer bonding layer (Fig. 1A, “35”; paragraph [0061], “35” on “34” on “32”). It can be necessarily understood to someone having ordinary skill in the art that a sapphire substrate is a wafer, in the sense that sapphire substrates are thin and epitaxially grown. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: include an isolation layer between the substrate and wafer bonding layer, for the benefit of absorbing electromagnetic, ion, and/or thermal radiation from bonding as a buffer for the substrate in the device of Schleuning and Zou.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Schleuning and Zou, in view of Tsau et al. (NPL, “Fabrication of Wafer-Level Thermocompression Bonds”), hereinafter Tsau.
Regarding Claim 24, Schleuning and Zou teach the device of Claim 1. Schleuning and Zou do not teach: wafer bonding layer comprises at least one of benzocyclobutane (BCB), silicon dioxide (SiO2), or SU-8.
Tsau teaches: wafer bonding layer (Fig. 2(a)) comprises at least one of benzocyclobutane (BCB), silicon dioxide (SiO2), or SU-8 (Fig. 2(a), “SiO2”).Therefore, it would have been obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to: have the wafer bonding layer comprise at least one of benzocyclobutane (BCB), silicon dioxide (SiO2), or SU-8, for the benefit of preventing hardening of the thermocompression material during the thermocompression process (Section “III. Results and Discussion”, Subsection “A. Fabrication Process”).
Claims 25 and 26 rejected under 35 U.S.C. 103 as being unpatentable over Schleuning and Zou, in view of Hegblom et al. (U.S. Patent Application 2020/0321754 A1), hereinafter Hegblom2.
Regarding Claim 25, Schleuning and Zou teach the device of Claim 1. Schleuning and Zou do not teach: the one or more emitters comprises a plurality of bottom-emitting emitters.
Hegblom2 teaches: the one or more emitters (Fig. 1, “100”) comprises a bottom-emitting emitter (paragraph [0027]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: have the one or more emitters comprises a plurality of bottom-emitting emitters in the device of Schleuning and Zou, in order to emit the light from the device in another direction.
Regarding Claim 26, Schleuning, Zou, and Hegblom2 teach the device of Claim 25. Schleuning, Zou, and Hegblom2 don’t explicitly teach: the substrate comprises a conducting material.
Zou discloses: the substrate (Fig. 2, “213”) is connected to circuitry for driving (paragraph [0038], “control and drive circuitries”). Therefore, it can be necessarily understood to someone of ordinary skill in the art that: the substrate comprises a conducting material in the device of Schleuning, Zou, and Hegblom2, as the substrate as taught by Zou in the device of Schleuning, Zou, and Hegblom2 would have to be conductive in order to conduct driving current.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Schleuning, Zou, and Hegblom2, in view of Halbritter.
Regarding Claim 27, Schleuning, Zou, and Hegblom2 teach the device of Claim 25. Schleuning teaches: an isolation region (Fig. 5A, “503”). Schleuning, Zou, and Hegblom2 do not teach: that the isolation layer is between the substrate and wafer bonding layer.
Halbritter teaches: the VCSEL array (paragraph [0103]) further includes an isolation layer (Fig. 1A, “34”; paragraph [0061]; paragraph [0068], “dielectric”) between the substrate (Fig. 1A, “32”; paragraph [0060], “sapphire”; paragraph [0061], “34” on “32”) and the wafer bonding layer (Fig. 1A, “35”; paragraph [0061], “35” on “34” on “32”). It can be necessarily understood to someone having ordinary skill in the art that a sapphire substrate is a wafer, in the sense that sapphire substrates are thin and epitaxially grown. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: include an isolation layer between the substrate and wafer bonding layer, for the benefit of absorbing electromagnetic, ion, and/or thermal radiation from bonding as a buffer for the substrate in the device of Schleuning, Zou, and Hegblom2.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yokozeki, in view of Schleuning.
Regarding Claim 11, Yokozeki teaches a method (paragraph [0036]), comprising: forming an epitaxial region (Fig. 7A, 103”, “104”, “105”, “106” “107” “108”); on a first substrate (Fig. 7A, “SB”; paragraph [0141]; Fig. 5A); forming a first metal layer on a first side of the epitaxial region (Fig. 8A, “102”, first side below “103”, paragraph [0114], paragraph [0147]), bonding (paragraph [0148]), using a wafer bonding material (paragraph [0148], “solder or Ag paste”), the first metal layer (Fig. 8B, “102”) and the first side of the epitaxial region (Fig. 8B, see side below “103”) to a second substrate (Fig. 8B, “101”) such that the first metal layer is between the first side of the epitaxial region and the second substrate (Fig. 8B, see “102” between “101” and “103”, “104”, “105”, “106” “107” “108”); removing the first substrate (paragraph [0149]) to expose a portion of a second side of the epitaxial region (Fig. 9; top of “108”); and forming a second metal layer (Fig. 9, “109”) on the second side of the epitaxial region (Fig. 9, “109” on top of “108”). Yokozeki does not teach: the first metal layer including a plurality of first electrodes; the second metal layer including a plurality of second electrodes; the plurality of first electrodes and the plurality of second electrodes are arranged to provide a plurality of row electrodes and a plurality of column electrodes, the plurality of row electrodes and the plurality of column electrodes intersecting to form a plurality of matrix addressable subarrays of an emitter array, each matrix addressable subarray being disposed at an intersection between one of the row electrodes and one the column electrodes, and each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters.
Schleuning teaches: a first metal layer (Fig. 5B, “504”, “505”) including a plurality of first electrodes (Fig. 5B, “504”); a second metal layer (Fig. 5B, see region of all elements “506”) including a plurality of second electrodes (Fig. 5B, each “506” in the region of all elements “506”); the plurality of first electrodes and the plurality of second electrodes are arranged to provide a plurality of row electrodes Fig. 5A, see “506” defining 5 rows; paragraph [0152], “row-anode”) and a plurality of column electrodes (Fig. 5A, see “504” defining 4 columns; paragraph [0152], “column-cathode”), the plurality of row electrodes and the plurality of column electrodes intersecting to form a plurality of matrix addressable subarrays of an emitter array (paragraph [0152], “individual addressability of each VCSEL”), each matrix addressable subarray being disposed at an intersection between one of the row electrodes and one the column electrodes (Fig. 5A, see each “512” at intersection of each “504” and each “506”, and each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters Fig. 5A, one “512” at each intersection of “504” and “506”; paragraph [0152], “VCSELs”).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: have a plurality of first electrodes and a plurality of second electrodes in the method of Yokozeki, for the benefit of forming a matrix addressable connection structure; that the plurality of first electrodes and the plurality of second electrodes are arranged to provide a plurality of row electrodes and a plurality of column electrodes, the plurality of row electrodes and the plurality of column electrodes intersecting to form a plurality of matrix addressable subarrays of an emitter array, each matrix addressable subarray being disposed at an intersection between one of the row electrodes and one the column electrodes, and each matrix addressable subarray of the plurality of matrix addressable subarrays including one or more emitters in the method of Yokozeki, for the benefit of producing separately addressable VCSELs (paragraph [0152]).
Regarding Claim 12, Yokozeki and Schleuning teach the method of Claim 11. Yokozeki further teaches: the wafer bonding layer comprises at least one of an adhesive bonding material, a solder bonding material, or a thermocompression bonding material (paragraph [0148]).
Regarding Claim 13, Yokozeki and Schleuning teach the method of Claim 11. Schleuning further teaches: forming an isolation region (Fig. 5B, “503”) associated with isolating a first electrode of the plurality of first electrodes from a second electrode of the plurality of first electrodes (paragraph [0136], “electrically isolated”). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: form an isolation region associated with isolating a first electrode of the plurality of first electrodes from a second electrode of the plurality of first electrode as taught by Schleuning in the method of Yokozeki and Schleuning, for the benefit of preventing current leakage between a first electrode of the plurality of first electrodes from a second electrode of the plurality of first electrodes.
Claims 21 is rejected under 35 U.S.C 103 as being unpatentable over Yokozeki and Schleuning, in view of Tsau.
Regarding Claim 21, Yokozeki and Schleuning teach the method of Claim 11. Yokozeki and Schleuning do not teach: that the wafer bonding material comprises a thermocompression bonding material including two metal layers, and wherein bonding to the second substrate comprises bringing the two metal layers into contact with simultaneous application of force and heat.
Tsau teaches: a wafer bonding material (Abstract; Fig. 2(a)) comprises a thermocompression bonding material (Fig. 2(c), “Ti/Au”) including two metal layers (Fig. 2(c), see two black “Ti/Au” layers), and wherein bonding to a second substrate (Fig. 2(a), see grey Si substrates) comprises bringing the two metal layers (Fig. 2(c) and 2(d), see two black Ti/Au layers) into contact with simultaneous application of force and heat (Section “A. Thermocompression Bonding”, first paragraph, first sentence). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize a thermocompression bonding material including two metal layers, and wherein bonding to the second substrate comprises bringing the two metal layers into contact with simultaneous application of force and heat in the method of Yokozeki and Schleuning, for the benefit of reducing packaging costs by packaging at the wafer level (Section “I. Introduction”, first paragraph, fifth sentence).
Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yokozeki and Schleuning, in view of Hegblom1.
Regarding Claim 22, Yokozeki and Schleuning teach the method of Claim 13. Yokozeki and Schleuning do not teach: that the isolation region is an ion implantation region.
Hegblom1 teaches an isolation region (Fig. 1b, “116” ) is an ion implantation region (fifth column, lines 36-39). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an ion implanted region as taught by Hegblom1 in the method of Yokozeki and Schleuning, as Hegblom1 demonstrates the ion implanted region is suitable for the purpose of the isolation region to electrically isolate adjacent electrodes. It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 277 F.2d 197, 125 USPQ 416.
Regarding Claim 23, Yokozeki and Schleuning teach the method of Claim 13. Yokozeki and Schleuning do not teach: that the isolation region is an etched region.
Hegblom1 teaches: an isolation region (Fig. 1a, “118”) is an etched region (Col. 5, lines 64-67). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to: utilize an etched isolation region as taught by Hegblom1 in the method of Yokozeki and Schleuning, for the benefit of physically separating a first electrode of the plurality of first electrodes from a second electrode of the plurality of first electrodes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Higa et al. WO 2022/130825 A1
Watanabe et al. WO 2022/044886 A1
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.K.M./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
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