DETAILED ACTION
This action is responsive to the communication filed 11 March 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Claims 7, 9-11, and 14-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 8 April 2025.
Response to Arguments
Applicant's arguments filed 11 March 2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant states:
Applicant respectfully submits that Ota discloses, e.g., that the electrostatic protection circuit 25A allows a surge current caused by the static electricity and the like to flow to common wiring and is provided between the drive circuit 30, the inspection circuit 16, and each inspection terminal 24A ([0066]), which, in Applicant’s most respectful estimation provides neither a description nor a suggestion of at least the above-discussed claimed features as recited, inter alia, in Claim 1, which pertain to protecting the plurality of unit circuits from a high voltage supplied to the first substrate.
Applicant Arguments/Remarks Made in an Amendment (filed 11 March 2026) at 3. The Examiner respectfully asserts that the claimed feature of currently amended claim 1 “a first protective circuit arranged in the first substrate, and configured to protect the plurality of unit circuits from a high voltage supplied to the first substrate, the first protective circuit being adapted to withstand a maximum voltage supplied to the first substrate” is disclosed in Ota, based on the Examiner’s understanding of the devices disclosed in each of Applicant’s disclosure, Yamamura, and Ota, consistent with the Examiner’s interpretation of the devices applied in view of the § 112(b) rejection of claim 1.
Notably, Applicant appears to disclose wherein the claimed “first protective circuit” is configured to provide electrostatic discharge resistance, as well as protection against surge voltage. See Instant Application: [0025]: “Next, some examples of the circuit arrangement of the protective circuit will be described. Each of FIGS. 3A to 3G shows the arrangement example of a protective circuit 301 in the input/output unit 108.”; [0026]: “In the examples shown in FIGS. 3A, 3B, 3C, and 3D, when a surge voltage is input to the signal lines 305 and 306, the diodes 304 or the gate-grounded transistors 308 can form a transmission path of the surge voltage to the power supply line 302 or the ground line 303. With this, the surge voltage can be hardly transmitted to the element electrically connected to the pad electrode.”; [0040]: “Hence, it is possible to obtain the Electrostatic Discharge resistance (to be referred to as the ESD withstand voltage hereinafter) that can withstand a high voltage by using the current high withstand voltage process and fine process intact without developing a new process.”; [0045]: “Hence, it is possible to obtain the ESD withstand voltage that can withstand a high voltage by using the current high withstand voltage process and fine process intact without developing a new process.” The “electrostatic protection circuits” of Ota likewise protect prevent circuit elements. See Ota FIGS. 5/7, [0066], [0109]. Moreover, the electrostatic protection circuits of Ota appear to be electrically connected to various portions of the device of Ota, including the scanning line drive circuits 14 and a signal line drive circuit 12 by wirings 26, which receive electrical signals and operate the device of Ota. Id.
Accordingly, Applicant’s arguments are unpersuasive.
Drawings
The objections to the drawings are withdrawn, responsive to Applicant’s arguments and amendments with respect to claims 6, 21, and 22.
Claim Rejections - 35 USC § 112
The rejection of claim 6 under § 112(b) is withdrawn, responsive to Applicant’s amendment of claim 6.
New rejections under § 112(b) appear below.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.' ” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014)).
Regarding Claim 1: claim 1 states, in relevant part, “a first protective circuit arranged in the first substrate, and configured to protect the plurality of unit circuits from a high voltage supplied to the first substrate, the first protective circuit being adapted to withstand a maximum voltage supplied to the first substrate . . . .” This phrase renders the scope of the claim unclear for several reasons. First, Applicant’s use of the term “high voltage” in the claims appears to contradict the manner in which the term “high voltage” is used in the rest of the disclosure. Namely, Applicant appears to disclose that various structures in the first substrate such as transistors are configured to operate at “high voltage.” See Instant Application at [0035]: “For example, a high voltage close to 10 V can be supplied to the first substrate 10. Accordingly, the circuit element such as the transistor 21 arranged in the first substrate 10 has an arrangement that can withstand a high voltage.” Accordingly, description of the protective circuit as “configured to protect the plurality of unit circuits from a high voltage” appears contrary to what Applicant’s disclosure teaches.
Second, based on the abovementioned teachings of Applicant’s disclosure, “high voltage” and “maximum voltage supplied to the first substrate” appear to describe the same voltage level, which is “high voltage,” such that the difference between the voltages as disclosed by Applicant’s amended claim language is unclear. See Instant Application at [0035]: “The maximum voltage (first voltage) in the first substrate 10 is higher than the maximum voltage (second voltage) in the second substrate 30. For example, a high voltage close to 10 V can be supplied to the first substrate 10. Accordingly, the circuit element such as the transistor 21 arranged in the first substrate 10 has an arrangement that can withstand a high voltage. Therefore, the first protective circuit 301 a can also be configured to have an arrangement that can withstand a high voltage.”
Third, it is unclear whether and to what extent Applicant’s use of the term “adapted to” further limits the claim.
“Claim scope is not limited by claim language that suggests or makes optional but does not require steps to be performed, or by claim language that does not limit a claim to a particular structure.” MPEP § 2111.04(I). “[E]xamples of claim language, although not exhaustive, that may raise a question as to the limiting effect of the language in a claim are: (A) ‘adapted to’ or ‘adapted for’ clauses . . . .” Id. “The determination of whether each of these clauses is a limitation in a claim depends on the specific facts of the case.” “In In re Giannelli, the court found that an ‘adapted to’ clause limited a machine claim where ‘the written description makes clear that “adapted to,” as used in the [patent] application, has a narrower meaning, viz., that the claimed machine is designed or constructed to be used as a rowing machine whereby a pulling force is exerted on the handles.’” Id. (quoting In re Giannelli, 739 F.3d 1375, 1378 (Fed. Cir. 2014)).
In the instant case, based on the claim language and Applicant’s use of the term “adapted to,” the phrase “the first protective circuit being adapted to withstand a maximum voltage supplied to the first substrate” does not appear to significantly limit the claim, and actually appears to contradict portions of Applicant’s disclosure describing the protective circuits. Compare, e.g., Instant Application claim 1 (“a first protective circuit arranged in the first substrate, and configured to protect the plurality of unit circuits from a high voltage supplied to the first substrate, the first protective circuit being adapted to withstand a maximum voltage supplied to the first substrate . . . .”) with, e.g., Instant Application [0025] (“The circuit arrangement of the protective circuit 301 can be selected in accordance with the kind of a signal or potential (for example, a power supply potential, an analog input/output signal, or a digital input/output signal) to be given to the pad electrode electrically connected to the protective circuit 301.”), Instant Application [0026] (“In the examples shown in FIGS. 3A, 3B, 3C, and 3D, when a surge voltage is input to the signal lines 305 and 306, the diodes 304 or the gate-grounded transistors 308 can form a transmission path of the surge voltage to the power supply line 302 or the ground line 303. With this, the surge voltage can be hardly transmitted to the element electrically connected to the pad electrode. Note that the protective circuit 301 may have an arrangement other than the arrangements shown in FIGS. 3A to 3G. As the protective circuit 301, a buffer having a hysteresis function may be employed. Alternatively, as the protective circuit 301, a pull-up resistor or a pull-down resistor may be provided between the signal lines 305 and 306 and the power supply line or the ground line.”), Instant Application [0035] (“For example, a high voltage close to 10 V can be supplied to the first substrate 10. Accordingly, the circuit element such as the transistor 21 arranged in the first substrate 10 has an arrangement that can withstand a high voltage. Therefore, the first protective circuit 301 a can also be configured to have an arrangement that can withstand a high voltage.”). Based on those cited portions of Applicant’s disclosure” and the narrow meaning of the term “adapted to,” assuming, arguendo, Applicant’s disclosure supports use of the term “adapted to,” the first protective circuit in fact appears to be “adapted to” protect the plurality of unit circuits, and “configured to” withstand a maximum voltage supplied to the first substrate, the opposite of what is claimed.
Accordingly, the scope of claim 1 is unclear.
For the purposes of examination, the Examiner has interpreted the term “high voltage” to refer to a voltage that is different from a “maximum voltage.”
Claims 2-6, 8, 12-13, 17, 19, 21, and 22, which depend from claim 1, are also rejected under § 112(b) for at least the same reasons as claim 1.
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 8, 12, 17, 19, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2022/0102452 (filed Sept. 18, 2019) (hereinafter “Yamamura”) in view of U.S. Patent Publication No. 2015/0213763 (filed Jan. 9, 2015) (hereinafter “Ota”).
Regarding independent claim 1, Yamamura discloses: A light emitting device (FIG. 6, display apparatus 200, [0094]) in which are stacked
(1) a light emitting element layer including a plurality of light emitting elements (FIG. 6, light emitting unit 21 including layers 213/212/211, [0062]),
(2) a first substrate (FIG. 6, semiconductor substrate 101, [0049]) including at least a part of a plurality of unit circuits respectively connected to the plurality of light emitting elements (FIGS. 3/6, pixel circuit 22 comprising various unit circuits connected to the light emitting unit 21, [0056]), and
(3) a second substrate (FIG. 6, semiconductor substrate 102, [0049]) including at least a part of a control circuit configured to control the plurality of unit circuits (FIGS. 3/6, pixel circuit 22 comprising various control circuits configured to control the various unit circuits, [0056]),
wherein the maximum voltage in the first substrate is higher than a maximum voltage in the second substrate (FIGS. 3/6, depicting wherein pixel circuit 22 comprising various unit circuits connected to the light emitting unit 21 and various control circuits configured to control the various unit circuits receives various voltages, some higher than others, [0112]).
Yamamura does not specifically disclose wherein the device further comprises:
a first protective circuit arranged in the first substrate, and configured to protect the plurality of unit circuits.
In the same field of endeavor, Ota discloses a light emitting device (FIGS. 5/7, organic EL panel 2, [0036]) including a protective circuit configuration including a plurality of protective circuits, configured to protect a plurality of circuits from a high voltage (FIGS. 5/7, electrostatic protection circuits 25A connected between inspection terminals 24A and drive circuit 30/inspection circuit 16 configured to protect from a surge current that is different from operating conditions, [0041], [0066]), the first protective circuit being adapted to withstand a maximum voltage supplied to the first substrate (FIGS. 5/7, depicting wherein the electrostatic protection circuits 25A are connected to an inspection circuit 16, scanning line drive circuits 14, and a signal line drive circuit 12 by wiring 26, and thus adapted to withstand voltages supplied to those circuits, [0047], [0048]). Regarding the electrostatic protection circuit configuration, in [0066], Ota states: “As illustrated in FIG. 4, the electrostatic protection circuit 25A allows a surge current caused by the static electricity and the like to flow to common wiring and is provided between the drive circuit 30, the inspection circuit 16, and each inspection terminal 24A.” Ota further states in [0109]: “The transistor Tr included in the electrostatic protection circuit 25A is one in which the diode is connected between the gate and the drain, and the substrate potential is applied to the drain. Thus, the electrostatic protection circuit 25A can release the charge by the static electricity without breaking down electronic components on the substrate 10 such as the light emitting element 45, the drive circuit 30, and the inspection circuit 16 even if the charge is injected into the inspection terminal 24A by the static electricity.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed light emitting device of Yamamura by adding an electrostatic protection circuit configuration of Ota, such that the protective circuit configuration is disposed in the first substrate 101 of Yamamura in order to protect the pixel circuit including various unit circuits in the first substrate. See Ota [0066], [0109].
Regarding claim 2, Yamamura in view of Ota further discloses a first pad electrode (Ota FIGS. 5/7, inspection terminal 24A, [0079]) electrically connected to the first protective circuit (Ota FIGS. 5/7, depicting wherein the inspection terminal 24A is electrically connected to the electrostatic protection circuit 25A).
Regarding claim 8, Yamamura does not specifically disclose wherein the display device further comprises a second protective circuit configured to protect the control circuit.
In the same field of endeavor, Ota discloses a light emitting device (FIGS. 5/7, organic EL panel 2, [0036]) including a protective circuit configuration including a plurality of protective circuits, configured to protect a plurality of circuits (FIG. 5, electrostatic protection circuits 25A connected between inspection terminals 24A and drive circuit 30/inspection circuit 16, [0041]). Regarding the electrostatic protection circuit configuration, in [0066], Ota states: “As illustrated in FIG. 4, the electrostatic protection circuit 25A allows a surge current caused by the static electricity and the like to flow to common wiring and is provided between the drive circuit 30, the inspection circuit 16, and each inspection terminal 24A.” Ota further states in [0109]: “The transistor Tr included in the electrostatic protection circuit 25A is one in which the diode is connected between the gate and the drain, and the substrate potential is applied to the drain. Thus, the electrostatic protection circuit 25A can release the charge by the static electricity without breaking down electronic components on the substrate 10 such as the light emitting element 45, the drive circuit 30, and the inspection circuit 16 even if the charge is injected into the inspection terminal 24A by the static electricity.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed light emitting device of Yamamura by adding an electrostatic protection circuit configuration of Ota, such that the protective circuit configuration is also disposed in the second substrate 102 of Yamamura in order to protect the pixel circuit including control circuits configured to control the various unit circuits in the second substrate. See Ota [0066], [0109].
Regarding claim 12, Yamamura in view of Ota further discloses wherein the second protective circuit is arranged in the second substrate (Ota FIG. 5, depicting wherein the electrostatic protection circuit 25A of the protective circuit configuration is disposed in the same semiconductor substrate as the circuit the electrostatic protection circuit 25A is protecting (i.e., the drive circuit 30, for instance), such that the electrostatic protection circuit 25A would be disposed in the second semiconductor substrate 102 of Yamamura, in which the pixel circuit 22 including control circuits configured to control the various unit circuits in the second substrate is disposed).
Regarding claim 17, Yamamura in view of Ota further discloses wherein the light emitting element layer includes an organic light emitting element (FIG. 6, light emitting unit 21, [0062]: “In this embodiment, the light emitting unit 21 includes an organic EL device (OLED). The light emitting unit 21 has a known configuration or structure including an anode electrode, an organic material layer, a cathode electrode, and the like.”).
Regarding claim 19, Yamamura in view of Ota further discloses an electronic apparatus (FIG. 16, mobile phone 900, [0150]) comprising: the device according to claim 1 (FIG. 16, [0150]: “The display 940 or the sub-display 950 includes the display apparatus according to any of the above-mentioned embodiments.”); a housing provided with the light emitting device (FIG. 16, upper and lower housing 910/920, [0150]); and a communication unit provided in the housing and configured to perform external communication (FIG. 16, the sub display 950 is a communication unit configured to communicate information regarding communications of the mobile phone 900).
Regarding claim 22, Yamamura in view of Ota further discloses wherein the first protective circuit overlaps a transistor arranged in the second substrate (Ota FIG. 5, depicting wherein the protective circuit configuration including electrostatic protection circuits 25A, between inspection terminals 24A and drive circuit 30/inspection circuit 16 includes the circuits to which the protective circuit is connected, such that the protective circuit configuration disposed in the first substrate 101 of Yamamura would overlap a transistor arranged in the substrate 102, e.g., Yamamura FIG. 6, depicting wherein the TRDrv and TRsig overlap).
Claims 3-6, 13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamura in view of Ota, and further in view of in view of U.S. Patent Publication No. 2017/0033144 (filed Apr. 8, 2015) (hereinafter “Takahashi”).
Regarding claim 3, Yamamura in view of Ota discloses wherein the first substrate (FIG. 6, substrate 101) is arranged between the light emitting element layer and the second substrate (FIG. 6, depicting wherein the substrate 101 is arranged between the light emitting unit 21 and the substrate 102).
Yamamura in view of Ota does not specifically disclose wherein the first pad electrode is arranged in the second substrate.
In the same field of endeavor, Takahashi discloses an electronic device including a pad electrode configuration including a plurality of pad electrodes (FIG. 7, aluminum pads 514A-C, [0102]), the pad electrode configuration including wherein pad electrodes are exposed by corresponding openings (FIG. 7, pad holes 515A-C, [0102]) and electrically connected to various circuits disposed at various depths in various stacked substrates via various conductive paths (FIG. 7, depicting wherein the aluminum pads 514A-C are electrically connected to sensor circuits, logic circuits, and memory circuits in the first, second, and third layers 501-503), but wherein the pad electrodes are all disposed in the same substrate (FIG. 7, depicting wherein the aluminum pads 514A-C are each disposed in the same substrate layer 501). Regarding the pad electrode configuration, in [0111], Takahashi states: “functions of aluminum pads can be separately created by establishing connection configurations among the substrate of the first layer 501, the substrate of the second layer 502, and the substrate of the third layer 503 as different configurations such as the connection configuration A, the connection configuration B, and the connection configuration C. In other words, the aluminum pads 514 serving as electrodes for external connection, the aluminum pads 524 of the rear surface side and the aluminum pads 525 of the surface side serving as measuring electrodes, and the aluminum pads 534 serving as measuring electrodes are disposed in a mixed manner.” Takahashi further states in [0128]: “As described above, only a terminal necessary for measurement evaluation of an interface of the substrate of the first layer 501 itself and a product serves as the aluminum pad 514 formed in the substrate of the first layer 501 of the solid-state imaging element 500, and an electrode necessary for another measurement is built in the substrate of the second layer 502 or a subsequent layer. Thus, duplication of a pad electrode can be prevented, and thus it is possible to greatly contribute to a decrease in a chip area.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Yamamura and Ota by substituting the inspection terminals 24A of Ota with the pad electrode configuration of Takahashi such that one of the aluminum pads (e.g., 514A) is disposed in the second substrate 102 of Yamamura in order to allow the aluminum pads to serve as both measuring electrodes and external connection electrodes, and to decrease the area of the chip area. See Takahashi [0111], [0128].
Regarding claim 4, Yamamura in view of Ota and Takahashi further discloses a first opening portion (FIG. 7, pad holes 515A-C, e.g., pad hole 514A, [0102]) configured to expose the first pad electrode is provided in the second substrate (FIG. 7, depicting wherein the pad holes 515A of the pad electrode configuration of Takahashi, disposed in the light emitting device of Yamamura as modified by Ota, would expose the corresponding aluminum pad 514A and be provided in the substrate 102).
Regarding claim 5, Yamamura in view of Ota and Takahashi further discloses wherein the first substrate includes
a first semiconductor substrate (FIG. 6, semiconductor substrate 101) and
a first wiring layer (FIG. 6, first pixel circuit 421 of the pixel circuit 22) stacked on the first semiconductor substrate (FIG. 6, depicting wherein the first pixel circuit 421 is stacked on the substrate 101),
wherein the first semiconductor substrate is arranged between the light emitting element layer and the first wiring layer (FIG. 6, depicting wherein the semiconductor substrate 101 is arranged between the light emitting unit 21 and the first pixel circuit 421),
wherein each of the plurality of light emitting elements and a corresponding unit circuit among the plurality of unit circuits are electrically connected to each other via a penetrating electrode provided in the first semiconductor substrate (FIG. 6, depicting wherein the wiring layer 42w1 electrically connects the light emitting unit 21 to the unit circuits and control circuits configured to control the unit circuits of the pixel circuit 22), and
wherein the first wiring layer includes a conductive path configured to electrically connect the first protective circuit and the first pad electrode (Takahashi FIG. 7, depicting wherein the pad electrode configuration including, e.g., aluminum pad 514A discloses various wiring layers that electrically connect the circuit (e.g., the memory circuit of the third layer 503) and aluminum pad, and further wherein the protection circuit configuration, including the electrostatic protection circuit 25A, would be electrically connected between the aluminum pads 514A-C and the circuits as disclosed in Ota FIG. 4, depicting wherein the electrostatic protection circuit 25A is electrically connected between the inspection terminal 24A and a desired circuit, e.g., drive circuit 30).
Regarding claim 6, Yamamura in view of Ota and Takahashi further discloses wherein the second substrate includes (1) a second semiconductor substrate (FIG. 6, semiconductor substrate 102) and (2) a second wiring layer stacked on the second semiconductor substrate (FIG. 6, second pixel circuit 422 of the pixel circuit 22), and
wherein the second wiring layer is arranged between the first substrate and the first semiconductor substrate (FIG. 6, depicting wherein the second pixel circuit 422 is arranged between the first semiconductor substrate 101 and the semiconductor substrate 102).
Regarding claim 13, Yamamura in view of Ota does not specifically disclose wherein a first pad electrode arranged in the second substrate, and electrically connected to the first protective circuit; and a second pad electrode arranged in the second substrate, and electrically connected to the second protective circuit, wherein (1) a first opening portion configured to expose the first pad electrode and (2) a second opening portion configured to expose the second pad electrode are provided in the second substrate.
In the same field of endeavor, Takahashi discloses an electronic device including a pad electrode configuration including a plurality of pad electrodes (FIG. 7, aluminum pads 514A-C, [0102]), the pad electrode configuration including wherein pad electrodes are exposed by corresponding openings (FIG. 7, pad holes 515A-C, [0102]) and electrically connected to various circuits disposed at various depths in various stacked substrates via various conductive paths (FIG. 7, depicting wherein the aluminum pads 514A-C are electrically connected to sensor circuits, logic circuits, and memory circuits in the first, second, and third layers 501-503), but wherein the pad electrodes are all disposed in the same substrate (FIG. 7, depicting wherein the aluminum pads 514A-C are each disposed in the same substrate layer 501). Regarding the pad electrode configuration, in [0111], Takahashi states: “functions of aluminum pads can be separately created by establishing connection configurations among the substrate of the first layer 501, the substrate of the second layer 502, and the substrate of the third layer 503 as different configurations such as the connection configuration A, the connection configuration B, and the connection configuration C. In other words, the aluminum pads 514 serving as electrodes for external connection, the aluminum pads 524 of the rear surface side and the aluminum pads 525 of the surface side serving as measuring electrodes, and the aluminum pads 534 serving as measuring electrodes are disposed in a mixed manner.” Takahashi further states in [0128]: “As described above, only a terminal necessary for measurement evaluation of an interface of the substrate of the first layer 501 itself and a product serves as the aluminum pad 514 formed in the substrate of the first layer 501 of the solid-state imaging element 500, and an electrode necessary for another measurement is built in the substrate of the second layer 502 or a subsequent layer. Thus, duplication of a pad electrode can be prevented, and thus it is possible to greatly contribute to a decrease in a chip area.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device of Yamamura and Ota by substituting the inspection terminals 24A of Ota with the pad electrode configuration of Takahashi such that one of the aluminum pads (e.g., 514A) is disposed in the second substrate 102 and electrically connected to the pixel circuit 22 comprising various unit circuits connected to the light emitting unit 21, and further wherein the first protection circuit configuration, including the electrostatic protection circuit 25A in the first substrate, would be electrically connected between the aluminum pad 514A and the unit circuits such that the aluminum pad 514A is electrically connected to the electrostatic protection circuit 25A as disclosed in Ota FIG. 4, depicting wherein the electrostatic protection circuit 25A is electrically connected between the inspection terminal 24A and a desired circuit, e.g., drive circuit 30, and further wherein another one of the aluminum pads (e.g., 514B) is disposed in the second substrate 102 and electrically connected to the pixel circuit 22 comprising various control circuits configured to control the various unit circuits connected to the light emitting unit 21, and further wherein the second protection circuit configuration, including the electrostatic protection circuit 25A in the second substrate, would be electrically connected between the aluminum pad 514B and the control circuits configured to control the various unit circuits such that the aluminum pad 514B is electrically connected to the electrostatic protection circuit 25A as disclosed in Ota FIG. 4, depicting wherein the electrostatic protection circuit 25A is electrically connected between the inspection terminal 24A and a desired circuit, e.g., drive circuit 30, and further wherein a first pad hole 515A of the electrode pad configuration of Takahashi exposes the aluminum pad 514A and a second pad hole 515B of the electrode pad configuration of Takahashi exposes the aluminum pad 514B in order to allow the aluminum pads to serve as both measuring electrodes and external connection electrodes, and to decrease the area of the chip area. See Takahashi [0111], [0128].
Regarding claim 21, Yamamura in view of Ota and Takahashi further discloses wherein a thickness of the first pad electrode is different from a thickness of the second pad electrode (FIG. 7, depicting wherein the aluminum pads, e.g., 514B and 514A are different thicknesses (i.e., widths)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights