Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/9/2026 has been entered.
In the Instant Amendment, Claim(s) 1-2, 4-5, 13 and 20-21 has/have been amended; Claim(s) 3, 12, 15, 19 and 24 was/were cancelled; Claim(s) 25-29 has/have been added; Claim(s) 1-2 and 13 is/are independent claims. Claims 1-2, 4-11, 13-14, 16-18, 20-23 and 25-29 have been examined and are pending in this application.
Response to Arguments
Applicant's arguments filed 3/9/2026 have been fully considered but they are not persuasive.
Applicant’s arguments in the remarks (pages 13-16) with respect to claim(s) with respect to the rejections under 35 U.S.C 103 being unpatentable over the combination of Stettner, Wiley and Kodavalla have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Moreover, Applicant is also arguing in the remarks along with the declaration (pages 9-13) that Odom fails to disclose or teach the four points listed in the table.
The Examiner respectfully disagrees with the Applicant. The Examiner respectfully submits that Odom does teach these four points:
Odom does teach a single board (Fig. 12A shows a single carrier board 110B) having a single board reconfigurable signal processing architecture (Figs. 8-9; para. 0154: “a "RIO" Reconfigurable I/O carrier 110D, also referred to as a generalized carrier 110D. As used herein, the term "RIO" carrier refers to a carrier which includes reconfigurable hardware, e.g., an FPGA, which is configurable with respective interface protocols for one or more cartridges”; para. 0230: “a programmable hardware element, e.g., an FPGA, deploying the program on the functional unit of the device may include converting the program into a hardware description, such as a VHDL file, which may be compiled and used to program the FPGA to perform the measurement function”).
Odom clearly shows a single carrier board 110 connected to ROIC 108 connected to camera 112 (Figs. 2, 8A; para. 0081). Odom does teach the target ROIC (108) being configured to operate as an optical frontend to a respective separate optical detector array (para. 0081; of camera 112) (Figs. 2, 6, 8, 31, 33), and configured to interface with one of a plurality of different ones of the separate ROICs (measurement modules 108’s) to extract intensity data of the separate optical detector array, format the extracted intensity data of the separate optical detector array, and send the extracted and formatted intensity data of the separate optical detector array to the separate DAQ system for further analysis (Figs. 2, 6, 8, 31, 33; para. 0084: “the carrier 110 may receive signal data in a proprietary format from the measurement module 108 and format the data for transmission over wireless Ethernet to the computer system 102”; para. 0447: “As indicated above, the carrier may include one or more cartridge controllers for controlling one or more cartridges to perform various functions, e.g., industrial functions, e.g., for measurement, control, automation, image acquisition, etc”; para. 0094: “The computer system 102 may be operable to execute the measurement program to perform the one or more measurement functions, preferably in conjunction with operation of the carrier 110 and/or measurement module 108. For example, the measurement program may be executable to perform one or more of measurement or control functions, including analysis of data or signals received from the carrier, control of carrier and/or measurement module operations, user interface functions, image processing or machine vision functions, and motion control functions, among others”).
Odom does teach a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels configured to receive respective analog signals from the optical frontend of the imaging sensor consisting of the detector array (of the camera 112) and the ROIC (108) (Figs. 5C, 8A, 31, 33’s, 34’s; paras. 0004, 0137, 0434; para. 0004: “Input modules are typically provided for conditioning the raw field voltage signals by amplifying, isolating, filtering or otherwise converting the signals to the appropriate digital signals for the computer system”; para. 0137: “the carrier 110 may be operable to communicate with each measurement module 108 and be programmed or configured (e.g., by a computer system 102 or by a processor/memory on the carrier 110) to implement the respective interface of each measurement module”, para. 0170: “cartridge controller 508 may communicate over the SPI port 527 and use pins for converting data, indicating busy, and exchanging triggers and clocks. In another mode, the cartridge controller 508 may use eight pins for digital input and output. Upon power up or upon a cartridge change, the controller 508 may enter a tristate (high-Z) mode in which all the pins are tristate for protection”; para. 0364: “communications with a measurement module 108 may include sending setup information (e.g., a channel number or, in the case of an output module, data) sending a trigger, waiting for a busy line, sending commands (e.g., to read data) and reading the response”).
Odon’s reconfigurable FPGA single carrier board 110 for image processing or machine vision functions clearly teaches the features as claimed in claims 1, 22 and 13 as presented.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4-11, 13-14, 16-18, 20-23 and 25-29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, claim 1 recites “a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels configured to receive respective analog signals from the optical frontend of the imaging sensor consisting of the detector array and the ROIC” in lines 6-9 which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Paragraph 0067 recites “Various embodiments of the invention provide a single board reconfigurable signal processing architecture, comprising: an analog input stage comprising a plurality of available amplification and signal isolation channels configured to receive respective analog signals from an optical frontend of an imaging sensor consisting of a detector array and a ROIC”. However, there is no explicit support for “a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels”. If the Applicant believe otherwise, the Applicant is welcome to point out where in the specification the support for the feature as claimed.
Regarding claim 2, claim 2 recites “a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels configured to receive respective analog signals from the optical frontend of the separate imaging sensor” in lines 6-9 which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Paragraph 0067 recites “Various embodiments of the invention provide a single board reconfigurable signal processing architecture, comprising: an analog input stage comprising a plurality of available amplification and signal isolation channels configured to receive respective analog signals from an optical frontend of an imaging sensor consisting of a detector array and a ROIC”. However, there is no explicit support for “a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels”. If the Applicant believe otherwise, the Applicant is welcome to point out where in the specification the support for the feature as claimed.
Regarding claim 13, claim 13 recites “a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels configured to receive respective analog signals from the optical frontend of the imaging sensor consisting of the detector array and the ROIC” in lines 6-9 which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Paragraph 0067 recites “Various embodiments of the invention provide a single board reconfigurable signal processing architecture, comprising: an analog input stage comprising a plurality of available amplification and signal isolation channels configured to receive respective analog signals from an optical frontend of an imaging sensor consisting of a detector array and a ROIC”. However, there is no explicit support for “a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels”. If the Applicant believe otherwise, the Applicant is welcome to point out where in the specification the support for the feature as claimed.
Claims 4-11 are also rejected for being dependent of the base claim 2.
Claims 14, 16-18 and 20-23 are also rejected for being dependent of the base claim 13.
Claims 25-29 are also rejected for being dependent of the base claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-11, 13-14, 16-18, 20-23 and 25-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the imaging sensor" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the separate imaging sensor" in lines 9-10. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the signal processor" in line 4 on page 6. There is insufficient antecedent basis for this limitation in the claim.
Claims 4-11 are also rejected for being dependent of the base claim 2.
Claims 14, 16-18 and 20-23 are also rejected for being dependent of the base claim 13.
Claims 25-29 are also rejected for being dependent of the base claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-11, 13-14, 16-18, 20-23 and 25-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Odom (US 20060184335 A1).
Regarding claim 1, Odom teaches A Pulse Capture Electronics (PCE) system (Fig. 8A; para. 0154: “a "RIO" Reconfigurable I/O carrier 110D, also referred to as a generalized carrier 110D. As used herein, the term "RIO" carrier refers to a carrier which includes reconfigurable hardware, e.g., an FPGA, which is configurable with respective interface protocols for one or more cartridges”) configured to control a separate target Read-Out Integrated Circuit (ROIC) (108A to 108C) and provide output data to a separate Data Acquisition (DAQ) system (102) in a format required by the DAQ system (Fig. 2), the target ROIC (108) being configured to operate as an optical frontend to a respective separate optical detector array (para. 0081; of camera 112) (Figs. 2, 6, 8, 31, 33), the PCE comprising:
a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels configured to receive respective analog signals from the optical frontend of the imaging sensor consisting of the detector array (of the camera 112) and the ROIC (108) (Figs. 5C, 8A, 31, 33’s, 34’s; paras. 0004, 0137, 0434; para. 0004: “Input modules are typically provided for conditioning the raw field voltage signals by amplifying, isolating, filtering or otherwise converting the signals to the appropriate digital signals for the computer system”; para. 0137: “the carrier 110 may be operable to communicate with each measurement module 108 and be programmed or configured (e.g., by a computer system 102 or by a processor/memory on the carrier 110) to implement the respective interface of each measurement module”, para. 0170: “cartridge controller 508 may communicate over the SPI port 527 and use pins for converting data, indicating busy, and exchanging triggers and clocks. In another mode, the cartridge controller 508 may use eight pins for digital input and output. Upon power up or upon a cartridge change, the controller 508 may enter a tristate (high-Z) mode in which all the pins are tristate for protection”; para. 0364: “communications with a measurement module 108 may include sending setup information (e.g., a channel number or, in the case of an output module, data) sending a trigger, waiting for a busy line, sending commands (e.g., to read data) and reading the response”);
a ROIC data receive interface (pin multiplexing 525 of SPI interface) configured to provide a plurality of available physical layer channels (Fig. 31; of SPI) for coupling to a corresponding plurality of ROIC physical layer output channels for receiving an optical intensity level representative electrical signal from the target ROIC (Figs. 10A, 31);
a clock management system comprising a plurality of programmable clock generators (3382, 3384) configured to generate clock signals enabling communication between the ROIC data receive interface and the target ROIC, and wherein the clock management system is configured to generate a clock signal for the target ROIC, the clock signal configured to enable communication between the ROIC data receive interface and the target ROIC (Figs. 31, 33F; paras. 0338-0351);
a signal processor (FPGA 308) configured to receive control information associated with the target ROIC and responsively configure the ROIC data receive interface, the clock management system, or both (Figs. 8; paras. 0188-0189); and
a power subsystem configured to selectively generate a power signal for the target ROIC, the power signal having a selected power level, and wherein the signal processor is further configured to responsively reconfigure the power subsystem (Figs. 10A, 31; paras. 0351, 0125, 0336, 0348, 0351, 0354, 0433, 0436-0446); and
wherein the ROIC data receive interface, the clock management system, and the signal processor, and the power subsystem are all located on a single board (Fig. 12A shows a single carrier board 110B) having a single board reconfigurable signal processing architecture (Figs. 8-9; para. 0154: “a "RIO" Reconfigurable I/O carrier 110D, also referred to as a generalized carrier 110D. As used herein, the term "RIO" carrier refers to a carrier which includes reconfigurable hardware, e.g., an FPGA, which is configurable with respective interface protocols for one or more cartridges”; para. 0230: “a programmable hardware element, e.g., an FPGA, deploying the program on the functional unit of the device may include converting the program into a hardware description, such as a VHDL file, which may be compiled and used to program the FPGA to perform the measurement function”) and configured to interface with one of a plurality of different ones of the separate ROICs (measurement modules 108’s) to extract intensity data of the separate optical detector array, format the extracted intensity data of the separate optical detector array, and send the extracted and formatted intensity data of the separate optical detector array to the separate DAQ system for further analysis (Figs. 2, 6, 8, 31, 33; para. 0084: “the carrier 110 may receive signal data in a proprietary format from the measurement module 108 and format the data for transmission over wireless Ethernet to the computer system 102”; para. 0447: “As indicated above, the carrier may include one or more cartridge controllers for controlling one or more cartridges to perform various functions, e.g., industrial functions, e.g., for measurement, control, automation, image acquisition, etc”).
Regarding claim 2, Odom teaches A universal Read-Out Integrated Circuit (ROIC) interface configurable to control a separate target ROIC (108) and provide output data to a separate Data Acquisition (DAQ) system (102) in a format required by the DAQ system (Fig. 2; para. 0084), the target ROIC (108) being configured to operate as an optical frontend to a respective separate optical detector array (para. 0081; of camera 112) (Figs. 2, 6, 8, 31, 33), the universal ROIC interface comprising:
a Pulse Capture Electronics (PCE) system (Fig. 8A; para. 0154: “a "RIO" Reconfigurable I/O carrier 110D, also referred to as a generalized carrier 110D. As used herein, the term "RIO" carrier refers to a carrier which includes reconfigurable hardware, e.g., an FPGA, which is configurable with respective interface protocols for one or more cartridges”), comprising:
a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels configured to receive respective analog signals from the optical frontend of the separate imaging sensor (Figs. 5C, 8A, 33’s, 34’s; paras. 0004, 0137, 0434; para. 0004: “Input modules are typically provided for conditioning the raw field voltage signals by amplifying, isolating, filtering or otherwise converting the signals to the appropriate digital signals for the computer system”; para. 0137: “the carrier 110 may be operable to communicate with each measurement module 108 and be programmed or configured (e.g., by a computer system 102 or by a processor/memory on the carrier 110) to implement the respective interface of each measurement module”, para. 0170: “cartridge controller 508 may communicate over the SPI port 527 and use pins for converting data, indicating busy, and exchanging triggers and clocks. In another mode, the cartridge controller 508 may use eight pins for digital input and output. Upon power up or upon a cartridge change, the controller 508 may enter a tristate (high-Z) mode in which all the pins are tristate for protection”; para. 0364: “communications with a measurement module 108 may include sending setup information (e.g., a channel number or, in the case of an output module, data) sending a trigger, waiting for a busy line, sending commands (e.g., to read data) and reading the response”);
a ROIC data receive interface (pin multiplexing 525 of SPI) configured to provide a plurality of available physical layer channels (Fig. 31; of SPI) for coupling to a corresponding plurality of ROIC physical layer output channels for receiving an optical intensity level representative electrical signal from the target ROIC (Figs. 10A, 31);
a clock management system comprising a plurality of programmable clock generators (3382, 3384) configured to generate clock signals enabling communication between the ROIC data receive interface and the target ROIC, and wherein the clock management system is configured to generate a clock signal for the target ROIC, the clock signal configured to enable communication between the ROIC data receive interface and the target ROIC (Figs. 31, 33F; paras. 0338-0351);
a signal processor (FPGA 308) configured to receive control information associated with the target ROIC and responsively configure the ROIC data receive interface, the clock management system, or both (Figs. 8; paras. 0188-0189); and
a power subsystem configured to selectively generate a power signal for the target ROIC, the power signal having a selected power level, and wherein the signal processor is further configured to responsively reconfigure the power subsystem (Figs. 10A, 31; paras. 0351, 0125, 0336, 0348, 0351, 0354, 0433, 0436-0446); and
wherein the ROIC data receive interface, the clock management system, the signal processor, and the power subsystem are all located on a single board having a single board (Fig. 12A shows a single carrier board 110B) reconfigurable signal processing architecture (110) (Figs. 8-9; para. 0154: “a "RIO" Reconfigurable I/O carrier 110D, also referred to as a generalized carrier 110D. As used herein, the term "RIO" carrier refers to a carrier which includes reconfigurable hardware, e.g., an FPGA, which is configurable with respective interface protocols for one or more cartridges”; para. 0230: “a programmable hardware element, e.g., an FPGA, deploying the program on the functional unit of the device may include converting the program into a hardware description, such as a VHDL file, which may be compiled and used to program the FPGA to perform the measurement function”) and configured to interface with one of a plurality of different ones of the separate ROICs (108’s) to extract intensity data of the separate optical detector array, format the extracted intensity data of the separate optical detector array, and send the extracted and formatted intensity data of the separate optical detector array to the separate DAQ system for further analysis (Figs. 2, 6, 8, 31, 33; para. 0084: “the carrier 110 may receive signal data in a proprietary format from the measurement module 108 and format the data for transmission over wireless Ethernet to the computer system 102”; para. 0447: “As indicated above, the carrier may include one or more cartridge controllers for controlling one or more cartridges to perform various functions, e.g., industrial functions, e.g., for measurement, control, automation, image acquisition, etc”).
Regarding claim 4, Odom teaches the universal ROIC interface of claim 2, wherein the generated power signal is configured to be sequenced for boot up or shut down requirements of the target ROIC (Fig. 31; paras. 0125, 0336-0340, 0348, 0351, 0354).
Regarding claim 5, Odom teaches the universal ROIC interface of claim 2, wherein the signal processor includes a processor having tangible and non-transitory computer readable memory including instructions which, when executed by the processor, configure the signal processor to receive a control information associated with the target ROIC and responsively configure the power subsystem, the ROIC data receive interface, and the clock management system (paras. 0116-0118, 0188, 0189, 0230).
Regarding claim 6, Odom teaches the universal ROIC interface of claim 5, wherein the instructions, when executed by the processor, configure the signal processor to generate signals for hardware control of the optical frontend (Figs. 20-32).
Regarding claim 7, Odom teaches the universal ROIC interface of claim 5, wherein the instructions, when executed by the processor, configure the signal processor to generate signals for hardware control of the clock management system (Figs. 20-32).
Regarding claim 8, Odom teaches the universal ROIC interface of claim 5, wherein the instructions, when executed by the processor, configure the signal processor to generate signals for instantiation of power sources required for amplifier, digitizer, heterogeneous processor, and output signal drivers (Figs. 8, 11, 21-31; paras. 0125, 0336-0340, 0348, 0351, 0354).
Regarding claim 9, Odom teaches the universal ROIC interface of claim 5, wherein the instructions, when executed by the processor, configure the signal processor to generate signals for instantiation of power sources required for multiple ROIC and optical detector array requirements for powering the optical frontend (Figs. 8, 11, 21-31; paras. 0125, 0336-0340, 0348, 0351, 0354).
Regarding claim 10, Odom teaches the universal ROIC interface of claim 2, wherein the plurality of available physical layer channels comprise digital signal input channels (Figs. 6, 31).
Regarding claim 11, Odom teaches the universal ROIC interface of claim 2, wherein the plurality of available physical layer channels comprise analog signal input channels (Figs. 6, 31).
Regarding claim 13, Odom teaches A single board (Fig. 12A shows a single carrier board 110B) reconfigurable signal processing architecture (Figs. 8-9; para. 0154: “a "RIO" Reconfigurable I/O carrier 110D, also referred to as a generalized carrier 110D. As used herein, the term "RIO" carrier refers to a carrier which includes reconfigurable hardware, e.g., an FPGA, which is configurable with respective interface protocols for one or more cartridges”; para. 0230: “a programmable hardware element, e.g., an FPGA, deploying the program on the functional unit of the device may include converting the program into a hardware description, such as a VHDL file, which may be compiled and used to program the FPGA to perform the measurement function”) for interfacing with a separate optical frontend of an imaging sensor (para. 0081; of camera 112) consisting of a detector array and a Read-Out Integrated Circuit (ROIC) (108’s) and providing output data to a separate Data Acquisition (DAQ) system (102) in a format required by the DAQ system (Fig. 2), the single board reconfigurable signal processing architecture comprising:
a reconfigurable analog input stage comprising a plurality of available amplification and signal isolation, filtering, translating, and developing differential output channels configured to receive respective analog signals from the optical frontend of the imaging sensor consisting of the detector array (of camera 112) and the ROIC (108) (Figs. 5C, 8A, 31, 33’s, 34’s; paras. 0004, 0137, 0434; para. 0004: “Input modules are typically provided for conditioning the raw field voltage signals by amplifying, isolating, filtering or otherwise converting the signals to the appropriate digital signals for the computer system”; para. 0137: “the carrier 110 may be operable to communicate with each measurement module 108 and be programmed or configured (e.g., by a computer system 102 or by a processor/memory on the carrier 110) to implement the respective interface of each measurement module”, para. 0170: “cartridge controller 508 may communicate over the SPI port 527 and use pins for converting data, indicating busy, and exchanging triggers and clocks. In another mode, the cartridge controller 508 may use eight pins for digital input and output. Upon power up or upon a cartridge change, the controller 508 may enter a tristate (high-Z) mode in which all the pins are tristate for protection”; para. 0364: “communications with a measurement module 108 may include sending setup information (e.g., a channel number or, in the case of an output module, data) sending a trigger, waiting for a busy line, sending commands (e.g., to read data) and reading the response”);
a power subsystem configured to generate for a target ROIC a power signal having a selected power level, and wherein the signal processor is further configured to responsively reconfigure the power subsystem (Figs. 10A, 31; paras. 0351, 0125, 0336, 0348, 0351, 0354, 0433, 0436-0446);
a ROIC data receive interface (pin multiplexing 525 of SPI interface) configured to provide a plurality of available physical layer channels for coupling to a corresponding plurality of ROIC physical layer output channels for receiving from the target ROIC an optical intensity level representative electrical signal;
a clock management system comprising a plurality of programmable clock generators (3382, 3384) configured to generate clock signals enabling communication between the ROIC data receive interface and the target ROIC, and wherein the clock management system is configured to generate for the target ROIC a clock signal configured to enable communication between the ROIC data receive interface and the target ROIC (Figs. 31, 33F; paras. 0338-0351); and
a signal processor (FPGA 308) configured to receive control information associated with the target ROIC and responsively configure the analog input stage, the power subsystem, the ROIC data receive interface, and the clock management system (Figs. 8; paras. 0188-0189); and
wherein the analog input stage, the power subsystem, the ROIC data receive interface, the clock management system, and the signal processor are all on a single board (Fig. 12A shows a single carrier board 110B) and configured to interface with one of a plurality of different ones (108’s) of the separate ROIC to extract intensity data of the separate optical detector array (of camera 112), format the extracted intensity data of the separate optical detector array, and send the extracted and formatted intensity data of the separate optical detector array to the separate DAQ system for further analysis (Figs. 2, 6, 8, 31, 33; para. 0084: “the carrier 110 may receive signal data in a proprietary format from the measurement module 108 and format the data for transmission over wireless Ethernet to the computer system 102”; para. 0447: “As indicated above, the carrier may include one or more cartridge controllers for controlling one or more cartridges to perform various functions, e.g., industrial functions, e.g., for measurement, control, automation, image acquisition, etc”; para. 0459).
Regarding claim 14, Odom teaches the single board reconfigurable signal processing architecture of claim 13, wherein the signal processor is implemented using a field programmable gate array (FPGA) configured to adapt the signal processing architecture in response to a target ROIC (Figs. 8; paras. 0188-0189, 0487).
Regarding claim 16, Odom teaches the single board reconfigurable signal processing architecture of claim 13, wherein the power subsystem is configured to be re-sequenced for powering up and powering down of ROIC for optical frontends having different ROIC and optical detector array combinations (Figs. 10A, 31; paras. 0351, 0125, 0336, 0348, 0351, 0354, 0433, 0436-0446).
Regarding claim 17, Odom teaches the single board reconfigurable signal processing architecture of claim 13, wherein the clock management system includes multiple timing sources that can be used to generate multiple sub-harmonic signals (Figs. 10B, 31, 33F; paras. 0338-0351).
Regarding claim 18, Odom teaches the single board reconfigurable signal processing architecture of claim 13, wherein the signal processor is capable of communicating with a computer (102) (Figs. 2, 8A).
Regarding claim 20, Odom teaches the single board reconfigurable signal processing architecture of claim 13, wherein the signal processor configures the analog input stage, the power subsystem, the ROIC data receive interface, and the clock management system in accordance with an application received from the DAQ system (Fig. 8A; paras. 0094-0096, 0139, 0447, 0458).
Regarding claim 21, Odom teaches the single board reconfigurable signal processing architecture of claim 20, wherein the application comprises at least one of an image collection application, an optical array powering application, and an optical array scanning application (Fig. 8A; paras. 0094-0096, 0139, 0447, 0458).
Regarding claim 22, Odom teaches the single board reconfigurable signal processing architecture of claim 13, wherein the signal processor is associated with memory configured to store image data (Fig. 8A, 10A; paras. 0453, 0094-0096, 0139, 0447, 0458).
Regarding claim 23, Odom teaches the single board reconfigurable signal processing architecture of claim 13, wherein the signal processor is configured to implement control signals for different types of ROICs and for different sizes of detector arrays (Figs. 6, 8; paras. 0188-0189, 0439, 0460-0466, 0487).
Regarding claims 25-29, claims 25-29 reciting features corresponding to claims 4-6 and 8-9 are rejected for the same reasons above, respectively.
Prior art
Odom (US 7478006 B2) discloses similar invention as the applied reference and also teach all claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Quan Pham whose telephone number is (571)272-4438. The examiner can normally be reached Mon-Fri 9am-7pm.
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/Quan Pham/Primary Examiner, Art Unit 2637