DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 1, 2026 has been entered. Claims 1-6, 8-18, and 20-27 are under consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6, 9-10,13-14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani et al. (US 2021/0265806 A1, herein “Siriani”) and Zheng et al. (US 2016/0248515 A1, herein “Zheng”).
Regarding claim 1, Siriani discloses A photonic integrated circuit (Fig. 6) comprising:
a silicon substrate (Si wafer 110, [0018]);
a cladding material disposed on the silicon substrate (insulator 120 can be SiO2 or SiN, Para [0019]));
PNG
media_image1.png
122
235
media_image1.png
Greyscale
a waveguide formed in the cladding material (130 formed within cladding 120, Fig. 4, fifth block);
a III-V semiconductor material grown epitaxially on the silicon substrate bordering the cladding material (III-V component 160 adjacent to cladding material 120); and
a III-V semiconductor waveguide (component 160 is an active gain medium 230 surrounded by cladding 220) formed in the III-V semiconductor material and butt-coupled to the waveguide (120, 130). The examiner considers component (160) is the semiconductor waveguide butt-coupled to the waveguide (130, Paragraphs [0018], [0029], [0031], [0038]).
However, Sirani does not disclose at least one of the waveguide or the III-V semiconductor waveguide has a central optical axis running along the waveguide or the III-V semiconductor waveguide that is oriented parallel to a [110] direction of the silicon substrate.
Zheng teaches waveguide formed by III-V material (InGaAsP) has a central optical axis running along the III-V semiconductor waveguide that is oriented parallel to a direction [-110], wherein direction [-110] and direction [110] are equal and opposite magnitude changes (Fig. 4(a) and 4(b), Para [0069]-[0070]). Zheng further teaches all III-V electro-optic modulators subject to the waveguide orientation in the x-y plane as shown in Fig. 4 can have high polarization selectivity when an extern field F is applied orthogonally (z-direction). In this orientation, when an electric field F is applied orthogonally, only TE mode is modulated and TM mode is not modulated.
PNG
media_image2.png
373
424
media_image2.png
Greyscale
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the III-V waveguide orientation with respect to the crystal direction [110] would be applicable to the photonic elements (e.g., modulator, splitters, etc.) formed on the III-V epitaxially grown platform of Siriani’s invention (Para [0020]). One skill in the art can use x-ray diffraction technique to determine the crystal direction prior to epitaxial growth. One would be motivated to form the III-V waveguide with the optical axis parallel to a [110] direction for selective polarization modulation. In this orientation, TM mode is unmodulated while the TE mode is modulated. Design for one polarization state modulation is less power intensive with less signal distortion in high-speed modulator at high frequency.
Claim 3. Siriani / Zheng teach the photonic integrated circuit of claim 1, wherein Siriani further discloses the cladding material comprises an oxide (insulator 120 is also the cladding layer includes SiO2 or SiN, Para [0019]).
Claim 4. Siriani / Zheng teach the photonic integrated circuit of claim 1, wherein Siriani further discloses the waveguide comprises silicon nitride (SiN) (Para [0019]).
Claim 6. Siriani / Zheng teach the photonic integrated circuit of claim 1. Specifically, the SiN waveguide is butt-coupled to the epitaxially grown III-V semiconductor waveguide on the offcut silicon substrate. Siriani demonstrates considerations for suppressing coupling loss by coating the coupling interface (OCI 170) with a coating that may be low-reflection or anti-reflection and the III-V waveguide is aligned with the coupling features of the passive optical layer (Para [0021])
However, Siriani / Zheng do not explicitly teach the coupling loss between the waveguide and the III-V semiconductor waveguide is less than or equal to 10dB. Therefore, it would have been obvious to one having skills in the art to recognize the photonic integrated circuit, as broadly claimed in the instant application, and the photonic integrated circuit of Siriani’s invention would have similar coupling loss. Therefore, optimizing the coupling loss to be less than or equal to 10 dB would be within the skill of Siriani since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Claim 9. Siriani / Zheng teach the photonic integrated circuit of claim 1, wherein Siriani further discloses a trench (410 in Fig. 4, 400f) containing material (210) disposed between a first end of the waveguide and a second end of the III-V semiconductor waveguide that butt-couple to each other to reduce reflections from the butt-coupled waveguide and semiconductor waveguide (Para [0042]).
Claim 10. Siriani / Zheng teach the photonic integrated circuit of claim 1, wherein Siriani further discloses the waveguide is patterned to reduce backreflection (OCI antireflective coating) to increase coupling into the III-V semiconductor waveguide (Para [0021]-[0022]).
Claim 13. Siriani / Zheng teach the photonic integrated circuit of claim 1, wherein Siriani further discloses the photonic integrated circuit further comprising: electrical contacts in electrical communications in the III-V semiconductor material (“stimulated by applied electrical current, emit photons”), wherein the III-V semiconductor material (“III-V component 160) forms at least a portion of a laser (“coherent light produced by the laser”, Paras [0029]-[0030]).
Claim 14. Siriani / Zheng teach the photonic integrated circuit of claim 1, wherein Siriani further discloses the photonic integrated circuit further comprising: electrical contacts in electrical communications in the III-V semiconductor material (“stimulated by applied electrical current, emit photons”), wherein the III-V semiconductor material (“III-V component 160) forms at least a portion of a laser (“coherent light produced by the laser”, Paras [0029]-[0030]), and
an optical component (passive optical layer 130a and first optical coupler 720a) to direct light from the semiconductor laser out of a plane of the silicon substrate to form a surface-emitting semiconductor laser (Fig. 7).
Claim 21. Siriani / Zheng teach the photonic integrated circuit of claim 1, and Siriani further discloses and end of the waveguide (Fig. 2: layers 120 and 130) formed in the cladding material (silicon dioxide insulating layer 130) contacts an end of the III-V semiconductor waveguide (III-V component 16) where the III-V semiconductor waveguide butt-couples to the waveguide (Fig. 4: 400e) formed in the cladding material (130).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Siriani / Zheng as applied to claim 1 above, and further in view of Lee et al. (US 2018/0330982 A1, herein “Lee”.
Siriani / Zheng teach the invention of claim 1 and Siriani teaches the substrate has an off-cut of 6˚ (Para [0018]). However, Siriani / Zheng do not explicitly teach the silicon substrate a (100) silicon substrate with an off-cut towards a nearest [111] direction of the silicon substrate.
The examiner takes OFFICIAL NOTICE that silicon substrate is a (100) silicon substrate means the silicon is cut along the (100) crystallographic plane, which is industry standard for epitaxial growth techniques.
Siriani / Ban do not teach offcut at an angle towards a nearest [111] direction of the silicon substrate.
Lee teaches hybrid substrate that is epitaxially ready Si wafer substrate with 6˚ off-cut towards the nearest [111] direction (Para [0051]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the 6˚ off-cut towards the nearest [111] direction creates a deliberate tilt which provides series of steps and terraces for growth material to reside. One motivation would be to create a substrate ready for epitaxial growth resulting in less defects in the grown material.
Claims 8 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Lee et al. (US 2018/0330982 A1, herein “Lee”).
Regarding claims 8 and 22, Siriani discloses a photonic integrated circuit (Fig. 6) comprising:
a silicon substrate (Si wafer 110, [0018]);
a cladding material disposed on the silicon substrate (insulator 120 can be SiO2 or SiN, Para [0019]));
a waveguide formed in the cladding material (130 formed within cladding 120, Fig. 4, fifth block);
a III-V semiconductor material grown epitaxially on the silicon substrate bordering the cladding material (III-V component 160 adjacent to cladding material 120); and
a III-V semiconductor waveguide (component 160 is an active gain medium 230 surrounded by cladding 220) formed in the III-V semiconductor material and butt- coupled to the waveguide (120, 130). The examiner considers component (160) is the semiconductor waveguide butt-coupled to the waveguide (130). See paragraphs [0013], [0018], [0029], [0031], [0038].
Siriani does not disclose the waveguide is angled by at least 2 degrees with respect to the central optical axis of the III-V semiconductor waveguide wherein the angle is out of a plane that is parallel to a surface of the silicon substrate.
Lee teaches hybrid substrate that is epitaxially ready Si wafer substrate with 6˚ off-cut towards the nearest [111] direction (Para [0051]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the 6˚ off-cut towards the nearest [111] direction creates a deliberate tilt which provides series of steps and terraces for growth material to reside. One motivation would be to create a substrate ready for epitaxial growth resulting in less defects in the grown material.
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani / Zheng as applied to claim 1 above, and further in view of Lee et al. (US 10,049,916 B2, herein “Lee”).
Regarding claim 5. Siriani / Zheng teach the photonic integrated circuit of claim 1, but Siriani / Zheng is silent to the semiconductor waveguide has a threading dislocation density of about 1 x 106 cm-2 to about 1 x 109 cm-2.
Lee teaches a method of manufacturing III-V material on silicon that improves lattice mismatch between two materials and threading dislocations—crystal defects that run from the surface of a strained layer through the layer and into the substrate or another layer—per unit area of surface (cm-2, Col. 1, lines 45-63). The method (100) disclosed by Lee have been shown to improve the threading dislocation density (TDD) to be about 2.5 x 106 cm-2 (Col. 2, lines 27-35), which is within the range of claim 5. The method (100) reduces the TDD by annealing the exposed portion to the germanium layer with misfit dislocations; the dislocations may be oxidized using oxygen annealing and the oxidized germanium layer may easily be removed using wet etch. Thus, said annealing step also helps reduce TDD (Col. 7, line 52 to Col. 8, line 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing of III-V material on silicon substrate as disclosed by Lee to reduce lattice mismatch and suppress TDD. One would be motivated to suppress TDD because the defects can impact the performance and reliability of semiconductor devices grown using epitaxial technique.
Regarding claim 11, Siriani / Zheng teach the photonic integrated circuit of claim 1, but Siriani / Zheng is silent to the germanium layer disposed between the silicon substrate and the III-V semiconductor waveguide.
Lee teaches the proposed method (100) may find useful commercial applications in integrating III-V material on silicon via germanium/silicon or GOI substrate, manufacturing silicon-based photonics such as germanium laser and/or detectors, manufacturing higher mobility channels for advanced CMOS and the like (Col. 9, line 56 to Col. 10, line 10). Lee further teaches the germanium layer disposed between the silicon substrate and the III-V semiconductor device such as in advanced circuit and photonics functions as a “passive” buffer layer (Col. 1, lines 45-49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic integrated circuit of claim 1 with the germanium layer disposed on the silicon substrate and the III-V semiconductor waveguide as suggested by Lee to function as a passive buffer layer. One motivation for using a germanium passive buffer layer is due to the high charge carrier mobility of germanium which allows for ultra-fast circuits and performance.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Siriani / Zheng in view of Zhao et al. (US 2021/0265528 A1, herein “Zhao”).
Siriani / Zheng teach the photonic integrated circuit of claim 1, but Siriani / Zheng is silent to the dislocation filter disposed on the III-V semiconductor material between the silicon substrate and the III-V semiconductor waveguide.
Zhao teaches manufacturing a silicon-based substrate for optoelectronic device. Zhao discloses placing a group III-V material buffer layer and a group III-V dislocation filter layer (InGaAs, indium gallium arsenide) on a silicon-based substrate. The buffer layer is used to make buffer lattice mismatch of the silicon-based substrate and the dislocation filter layer is used to filter dislocation of the silicon-based substrate. The combined layer would smooth out roughness on the substrate, thus a smoother surface of the structure layer (Para [0019]-[0020], and [0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of the photonic integrated circuit of Siriani by providing a buffer layer and a dislocation filter layer in the III-V semiconductor material between the silicon substrate and the III-V semiconductor waveguide. One motivation would be to provide a smooth surface for the waveguide to guide light through that substantially reduces scattering loss and increase transmission efficiency.
Claims 15-17, 23 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Ban et al. (US 2016/0293764 A1, herein “Ban”)
Claim 15. Siriani discloses a method of making a photonic integrated circuit, the method comprising:
depositing (400a) a first cladding layer (120) on a silicon substrate (110, 400a);
forming a first waveguide (400b, 130) on the first cladding layer (120, Para [0024], 400b);
depositing a second cladding layer (400c, 120) on the first waveguide (130, Para [0025]);
etching a trench (400d) through the second cladding layer, at least a portion of the first waveguide and the first cladding layer, wherein etching through the first waveguide forms a first end of the first waveguide (“etches a pit 150”, “the fabricator etches the pit 150 to expose the first end of the photonic elements to the passive optical layer 130 to the pit 150”, Para [0026]);
epitaxially growing III-V semiconductor material (gallium arsenide) in the trench (400e, Para [0018] [0028]); and
forming a second waveguide from at least a portion of the III-V semiconductor material (Para [0229]), the second waveguide having a second end that is vertically aligned with a butt-coupled to the first end of the first waveguide (400e).
However, Siriani is silent to epitaxially growing gallium arsenide at a temperature between 550 degrees Celsius and 610 degrees Celsius.
Ban teaches epitaxially grow gallium arsenide (GaAs) on silicon substrate (102) at a higher temperature about 550 – 700 degrees Celsius (Para [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize Ban’s teaching of growing GaAs at high temperature would yield a high-quality crystal layer with less point defects. One would be motivated to grow GaAs on silicon substrate at high temperature range of 550 – 700 degrees Celsius to balance high quality crystal growth with the thermal limits of the existing silicon structure.
The examiner notes the method of making a photonic integrated circuit in applicant’s invention is performed with using the same material (gallium arsenide), technique (epitaxial growth of III-V material), and performed in the same condition (temperature between 550 to 610 degrees Celsius) as the combined teaching of Siriani in view of Ban. Thus, the photonic integrated circuit produced by the method of Siriani / Ban would result in “prevent[ing] unwanted faceting of the III-V semiconductor material that forms a gap between the first waveguide and the III-V semiconductor material (MPEP § 2114(II)).
Claim 16, Siriani / Ban teach the method of claim 15, and Siriani further discloses etching the trench comprises etching the trench at least partially into the silicon substrate (Para [0013] and [0016]). Siriani teaches forming the III-V material in regions of SiPh platform (Silicon On Insulator (SOI)) wafers (Para [0016]), wherein “etching through the insulator” on the SOI substrate (Para [0016]) accesses the underlying SiO2 insulator layer.
Claim 17. Siriani / Ban teach the method of claim 15 and Siriani further discloses forming electrical contacts in electrical communications with the III-V semiconductor material (the fabricator may incorporate various contact pads 610 to the optical assembly 600 via metallization (e.g., via evaporation or sputtering processes) so to add through silicon vias (TSVs), electrical leads, and passive connection points, Para [0045]).
Claim 23. Siriani / Ban teach the method of claim 15, Siriani further discloses the III-V material is gallium arsenide (Para [0018]). However, Siriani / Ban do not explicitly teach the growth rate is between 0.7 nanometers/second and 1.4 nanometers/second. However, Siriani / Ban teach the method of epitaxially growing gallium arsenide using the same technique (epitaxial growth of III-V material on (100) Si), and performed in the same condition (temperature between 550 to 610 degrees Celsius). Therefore, the growth rate of gallium arsenide as taught by Siriani / Ban would yield similar growth rate result. Moreover, the examiner considers optimizing the growth rate would be an obvious modification in view of KSR “obvious to try” rationale because it would have been obvious to one of ordinary skill in the art before the effective filing date to optimize the growth rate for increased efficiency.
Claim 26. Siriani / Ban teach the method of claim 15, and Siriani further discloses the second waveguide, when formed, has an end that contacts an end of the first waveguide (Fig. 4: 400e).
Claim 18 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani / Ban as applied to claim 15 above, and further in view of Lee et al. (US 2018/0330982 A1, herein “Lee”.
Claim 18. Siriani / Ban teach the method of claim 15 and Siriani further discloses the silicon substrate is off-axis Si material, off-cut at 6˚ (Para [0018]).
The examiner takes OFFICIAL NOTICE that silicon substrate is a (100) silicon substrate means the silicon is cut along the (100) crystallographic plane, which is industry standard for epitaxial growth techniques.
Siriani / Ban do not teach offcut at an angle towards a nearest [111] direction of the silicon substrate.
Lee teaches hybrid substrate that is epitaxially ready Si wafer substrate with 6˚ off-cut towards the nearest [111] direction (Para [0051]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the 6˚ off-cut towards the nearest [111] direction creates a deliberate tilt which provides series of steps and terraces for growth material to reside. One motivation would be to create a substrate ready for epitaxial growth resulting in less defects in the grown material.
Regarding claim 27, Siriani / Ban teach the method of claim 15, but Siriani / Ban do not teach forming the second waveguide comprises forming a second waveguide with a central optical axis that is angled with respect to a central axis of the first waveguide.
Lee teaches hybrid substrate that is epitaxially ready Si wafer substrate with 6˚ off-cut towards the nearest [111] direction (Para [0051]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the 6˚ off-cut towards the nearest [111] direction creates a deliberate tilt which provides series of steps and terraces for growth material to reside. One motivation would be to create a substrate ready for epitaxial growth resulting in less defects in the grown material.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Ban (herein “Siriani / Ban”) as applied to claim 15 above, and further in view of Warren et al. (US 2021/0020437 A1, herein “Warren”).
Siriani /Ban teach the method of claim 15, but Siriani / Ban do not teach the microscale patterns or sub-microscale patterns in the trench to suppress anti-phase domain formation in the III-V semiconductor material.
Warren teaches patterning the III-V semiconductor grown on silicon substrate with v-grooves can eliminate antiphase domain boundary formation – the creation of planar defect within a crystalline material where two regions of the same material, with different arrangements of atoms or structural variants, meet (Para [0023], Fig. 3). The groove period is approximately 500 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a photonic integrated circuit of Siriani with the technique of forming sub-microscale grooves to suppress anti-phase domain formation in the III-V semiconductor material, specifically in the trench provided for III-V component 160. One motivation would be to remove disruptions in the periodicity and symmetry of the crystal structure in the photonic devices. By suppressing this crystal defect, the trench is provided with a higher quality substrate for photonic devices to be disposed thereon.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani / Ban as applied to claim 15 above, and further in view of Zheng.
Siriani / Ban teach the method of claim 15, but Siriani / Ban do not teach at least one of the central optical axis of the first waveguide or a central optical axis of the second waveguide parallel to a [110] direction of the silicon substrate. Siriani / Ban also do not teach the first waveguide and the second waveguide central optical axis are parallel to the [110] direction of the silicon substrate.
Zheng teaches waveguide formed by III-V material (InGaAsP) has a central optical axis running along the III-V semiconductor waveguide that is oriented parallel to a direction [-110], wherein direction [-110] and direction [110] are equal and opposite magnitude changes (Fig. 4(a) and 4(b), Para [0069]-[0070]). Zheng further teaches all III-V electro-optic modulators subject to the waveguide orientation in the x-y plane as shown in Fig. 4 can have high polarization selectivity when an extern field F is applied orthogonally (z-direction). In this orientation, when an electric field F is applied orthogonally, only TE mode is modulated and TM mode is not modulated.
PNG
media_image2.png
373
424
media_image2.png
Greyscale
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the III-V waveguide orientation with respect to the crystal direction [110] would be applicable to the photonic elements (e.g., modulator, splitters, etc.) formed on the III-V epitaxially grown platform of Siriani’s invention (Para [0020]). One skill in the art can use x-ray diffraction technique to determine the crystal direction prior to epitaxial growth. One would be motivated to form the III-V waveguide with the optical axis parallel to a [110] direction for selective polarization modulation. In this orientation, TM mode is unmodulated while the TE mode is modulated. Design for one polarization state modulation is less power intensive with less signal distortion in high-speed modulator at high frequency.
Moreover, by aligning the central optical axis of the first and second waveguide to be parallel to the [110] forms atomically smoother vertical surface which benefits optical coupling.
Response to Arguments
Applicant’s arguments with respect to claims 1-4, 8-18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. PTO-892:C-D, N, U and V cite relevant prior arts. Fitzgerald et al. teach off-cutting the silicon substrate about 2˚ to 6˚ towards the [110] direction lower surface roughness and reduce dislocation density. Lochtefeld et al. teach lattice mismatched semiconductor structures with reduced dislocation defect densities. Kanetake et al. teach substrate crystallographic direction for improved modulation. NPL University Wafer teaches standard (100) wafer and applications. NPL to Lee et al. teaches varying growth temperatures to produce high quality germanium epitaxial film.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
Prosecution Insights