DETAILED ACTION
This office action is in response to applicant’s amendment filed on December 30, 2025. Claims 1-6, 8-18, and 20 are under consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-10, 13-15, 17, and 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Siriani et al. (US 2021/0265806 A1, herein “Siriani”).
Claim 1. A photonic integrated circuit (Fig. 6) comprising:
a silicon substrate (Si wafer 110, [0018]);
a cladding material disposed on the silicon substrate (insulator 120 can be SiO2 or SiN, Para [0019]));
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a waveguide formed in the cladding material (130 formed within cladding 120, Fig. 4, fifth block);
a III-V semiconductor material grown epitaxially on the silicon substrate bordering the cladding material (III-V component 160 adjacent to cladding material 120); and
a III-V semiconductor waveguide (component 160 is an active gain medium 230 surrounded by cladding 220) formed in the III-V semiconductor material and butt- coupled to the waveguide (120, 130). The examiner considers component (160) is the semiconductor waveguide butt-coupled to the waveguide (130, Paragraphs [0018], [0029], [0031], [0038]); to a [110] direction of the silicon substrate. The examiner notes, the waveguide 130 and the III-V semiconductor waveguide 160 are formed on silicon substrate 110. As such the 3-dimensional waveguides (130 or 160) would have some part of their volume that extends in the [110] direction of the underlying silicon substrate.
Claim 2. The photonic integrated circuit of claim 1, wherein the silicon substrate is a (100) silicon substrate with a 6 degree offcut towards a nearest <111> direction of the silicon substrate (Para [0018]).
Claim 3. The photonic integrated circuit of claim 1, wherein the cladding material comprises an oxide (insulator 120 is also the cladding layer includes SiO2 or SiN, Para [0019]).
Claim 4. The photonic integrated circuit of claim 1, wherein the waveguide comprises silicon nitride (SiN) (Para [0019]).
Claim 8. Siriani discloses a photonic integrated circuit (Fig. 6) comprising:
a silicon substrate (Si wafer 110, [0018]);
a cladding material disposed on the silicon substrate (insulator 120 can be SiO2 or SiN, Para [0019]));
a waveguide formed in the cladding material (130 formed within cladding 120, Fig. 4, fifth block);
a III-V semiconductor material grown epitaxially on the silicon substrate bordering the cladding material (III-V component 160 adjacent to cladding material 120); and
a III-V semiconductor waveguide (component 160 is an active gain medium 230 surrounded by cladding 220) formed in the III-V semiconductor material and butt- coupled to the waveguide (120, 130). The examiner considers component (160) is the semiconductor waveguide butt-coupled to the waveguide (130). See paragraphs [0013], [0018], [0029], [0031], [0038].
Siriani further teaches “the III-V component 160 includes an optical gain medium that is aligned with the coupling features defined in the passive optical layer 130 at a first height relative to the substrate 110” (Para [0021]). Therefore, the examiner considers a central optical axis of the waveguide is angled with respect to a central optical axis of the III-V semiconductor waveguide for the two structure to be aligned. As to what alignment angle between the two waveguides is not specified in the claim, thus, the examiner considers Siriani’s disclosure meets the limitations of claim 8.
Claim 9. The photonic integrated circuit of claim 1, further comprising a trench (410 in Fig. 4, 400f) containing material (210) disposed between a first end of the waveguide and a second end of the III-V semiconductor waveguide that butt-couple to each other to reduce reflections from the butt-coupled waveguide and semiconductor waveguide (Para [0042]).
Claim 10. The photonic integrated circuit of claim 1, wherein the waveguide is patterned to reduce backreflection (OCI antireflective coating) to increase coupling into the III-V semiconductor waveguide (Para [0021]-[0022]).
Claim 13. The photonic integrated circuit of claim 1, further comprising: electrical contacts in electrical communications in the III-V semiconductor material (“stimulated by applied electrical current, emit photons”), wherein the III-V semiconductor material (“III-V component 160) forms at least a portion of a laser (“coherent light produced by the laser”, Paras [0029]-[0030]).
Claim 14. The photonic integrated circuit of claim 1, further comprising: electrical contacts in electrical communications in the III-V semiconductor material (“stimulated by applied electrical current, emit photons”), wherein the III-V semiconductor material (“III-V component 160) forms at least a portion of a laser (“coherent light produced by the laser”, Paras [0029]-[0030]), and
an optical component (passive optical layer 130a and first optical coupler 720a) to direct light from the semiconductor laser out of a plane of the silicon substrate to form a surface-emitting semiconductor laser (Fig. 7).
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Claim 15. Siriani discloses a method of making a photonic integrated circuit, the method comprising:
depositing (400a) a first cladding layer (120) on a silicon substrate (110, 400a);
forming a first waveguide (400b, 130) on the first cladding layer (120, Para [0024], 400b);
depositing a second cladding layer (400c, 120) on the first waveguide (130, Para [0025]);
etching a trench (400d) through the second cladding layer, at least a portion of the first waveguide and the first cladding layer, wherein etching through the first waveguide forms a first end of the first waveguide (“etches a pit 150”, “the fabricator etches the pit 150 to expose the first end of the photonic elements to the passive optical layer 130 to the pit 150”, Para [0026]);
epitaxially growing III-V semiconductor material in the trench (400e, Para [0028]); and
forming a second waveguide from at least a portion of the III-V semiconductor material (Para [0229]), the second waveguide having a second end that is vertically aligned with a butt-coupled to the first end of the first waveguide (400e).
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Claim 17. Siriani discloses the method of claim 15 and further discloses forming electrical contacts in electrical communications with the III-V semiconductor material (the fabricator may incorporate various contact pads 610 to the optical assembly 600 via metallization (e.g., via evaporation or sputtering processes) so to add through silicon vias (TSVs), electrical leads, and passive connection points, Para [0045]).
Claim 18. Siriani discloses the method of claim 15,wherein the silicon substrate is a (100) silicon substrate with a 6 degree offcut towards a nearest [111] direction of the silicon substrate (Para [0018]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 11, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Lee et al. (US 10,049,916 B2, herein “Lee”).
Claim 5. Siriani discloses the photonic integrated circuit of claim 1, but Siriani is silent to the semiconductor waveguide has a threading dislocation density of about 1 x 106 cm-2 to about 1 x 109 cm-2.
Lee teaches a method of manufacturing III-V material on silicon that improves lattice mismatch between two materials and threading dislocations—crystal defects that run from the surface of a strained layer through the layer and into the substrate or another layer—per unit area of surface (cm-2, Col. 1, lines 45-63). The method (100) disclosed by Lee have been shown to improve the threading dislocation density (TDD) to be about 2.5 x 106 cm-2 (Col. 2, lines 27-35), which is within the range of claim 5. The method (100) reduces the TDD by annealing the exposed portion to the germanium layer with misfit dislocations; the dislocations may be oxidized using oxygen annealing and the oxidized germanium layer may easily be removed using wet etch. Thus, said annealing step also helps reduce TDD (Col. 7, line 52 to Col. 8, line 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing of III-V material on silicon substrate as disclosed by Lee to reduce lattice mismatch and suppress TDD. One would be motivated to suppress TDD because the defects can impact the performance and reliability of semiconductor devices grown using epitaxial techniques.
Regarding claim 11, Siriani discloses the photonic integrated circuit of claim 1, but Siriani is silent to the germanium layer disposed between the silicon substrate and the III-V semiconductor waveguide.
Lee teaches the proposed method (100) may find useful commercial applications in integrating III-V material on silicon via germanium/silicon or GOI substrate, manufacturing silicon-based photonics such as germanium laser and/or detectors, manufacturing higher mobility channels for advanced CMOS and the like (Col. 9, line 56 to Col. 10, line 10). Lee further teaches the germanium layer disposed between the silicon substrate and the III-V semiconductor device such as in advanced circuit and photonics functions as a “passive” buffer layer (Col. 1, lines 45-49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the photonic integrated circuit of claim 1 with the germanium layer disposed on the silicon substrate and the III-V semiconductor waveguide as suggested by Lee to function as a passive buffer layer. One motivation for using a germanium passive buffer layer is due to the high charge carrier mobility of germanium which allows for ultra-fast circuits and performance.
Regarding claim 16, Siriani discloses a method of making a photonic integrated circuit of claim 15, but Siriani is silent to etching the trench comprises etching the trench at least partially into the silicon substrate.
Lee teaches the method of reducing threading dislocation density in the III-V substrate. The first step is to bond the III-V material (112), germanium as an example, between two semiconductor substrates (110, 108 in Fig. 1). Then the second semiconductor substrate (110) may be removed by etching (“submerging the combined substrate into a solution of tetramethylammonium hydroxide”, Col. 6, line 61 to Col. 7, line 14) to expose the dislocation defects on the germanium that is hidden at the interface between the germanium layer and the semiconductor layer 110) (Col. 6, lines 34-67).
obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Siriani in accordance to Lee’s disclosure by etching the trench at least partially into the silicon substrate, where the dislocations are hidden, as the trench is the location where the III-V component 160 would reside. One would be motivated to etching partially into the silicon substrate is to expose the dislocations of the III-V at the interface between the III-V and the semiconductor layer. By exposing the dislocations, the following annealing step can effectively remove the dislocations, and ultimately produce a higher performing III-V substrate for placing optoelectronic devices thereon.
Claim 6 rejected under 35 U.S.C. 103 as being unpatentable over Siriani.
Regarding claim 6, Siriani teaches the photonic integrated circuit of claim 1. Specifically, the SiN waveguide is butt-coupled to the epitaxially grown III-V semiconductor waveguide on the offcut silicon substrate. Siriani demonstrates considerations for suppressing coupling loss by coating the coupling interface (OCI 170) with a coating that may be low-reflection or anti-reflection and the III-V waveguide is aligned with the coupling features of the passive optical layer (Para [0021])
However, Siriani does not explicitly teach the coupling loss between the waveguide and the III-V semiconductor waveguide is less than or equal to 10dB. Therefore, it would have been obvious to one having skills in the art to recognize the photonic integrated circuit, as broadly claimed in the instant application, and the photonic integrated circuit of Siriani’s invention would have similar coupling loss. Therefore, optimizing the coupling loss to be less than or equal to 10 dB would be within the skill of Siriani since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Then et al. (US 2020/0105882 A1, herein “Then”).
Siriani discloses the photonic integrated circuit of claim 1, but Siriani does not disclose the waveguide or the III-V semiconductor waveguide is oriented parallel to the [11] direction of the silicon substrate.
Then teaches choosing materials such as gallium arsenide that matches crystal orientation of [110] offer the advantage of having a smaller mismatch for subsequent epitaxial growth (Para [0046]). It would have been obvious to one having ordinary skill in the art to match the substrate crystal orientation for epitaxial growth since uniformity of the lattice is critical for semiconductor devices with consistent properties, thus consistent SiPh chip productions and higher chip yield.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Zhao et al. (US 2021/0265528 A1, herein “Zhao”).
Siriani discloses the photonic integrated circuit of claim 1, but Siriani is silent to the dislocation filter disposed on the III-V semiconductor material between the silicon substrate and the III-V semiconductor waveguide.
Zhao teaches manufacturing a silicon-based substrate for optoelectronic device. Zhao discloses placing a group III-V material buffer layer and a group III-V dislocation filter layer (InGaAs, indium gallium arsenide) on a silicon-based substrate. The buffer layer is used to buffer lattice mismatch of the silicon based substrate and the dislocation filter layer is used to filter dislocation of the silicon based substrate. The combined layer would smooth out roughness on the substrate, thus a smoother surface of the structure layer (Para [0019]-[0020], and [0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of the photonic integrated circuit of Siriani by providing a buffer layer and a dislocation filter layer in the III-V semiconductor material between the silicon substrate and the III-V semiconductor waveguide. One motivation would be to provide a smooth surface for the waveguide to guide light through that substantially reduces scattering loss and increase transmission efficiency.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Ban et al. (US 2016/0293764 A1, herein “Ban”)
Claim 15. Siriani discloses a method of making a photonic integrated circuit, the method comprising:
depositing (400a) a first cladding layer (120) on a silicon substrate (110, 400a);
forming a first waveguide (400b, 130) on the first cladding layer (120, Para [0024], 400b);
depositing a second cladding layer (400c, 120) on the first waveguide (130, Para [0025]);
etching a trench (400d) through the second cladding layer, at least a portion of the first waveguide and the first cladding layer, wherein etching through the first waveguide forms a first end of the first waveguide (“etches a pit 150”, “the fabricator etches the pit 150 to expose the first end of the photonic elements to the passive optical layer 130 to the pit 150”, Para [0026]);
epitaxially growing III-V semiconductor material (gallium arsenide) in the trench (400e, Para [0018] [0028]); and
forming a second waveguide from at least a portion of the III-V semiconductor material (Para [0229]), the second waveguide having a second end that is vertically aligned with a butt-coupled to the first end of the first waveguide (400e).
However, Siriani is silent to epitaxially growing gallium arsenide at a temperature between 550 degrees Celsius and 610 degrees Celsius.
Ban teaches epitaxially grow gallium arsenide (GaAs) on silicon substrate (102) at a higher temperature about 550 – 700 degrees Celsius (Para [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize Ban’s teaching of growing GaAs at high temperature would yield a high quality crystal layer with less point defects. One would be motivated to grow GaAs on silicon substrate at high temperature range of 550 – 700 degrees Celsius to balance high quality crystal growth with the thermal limits of the existing silicon structure.
Claim 17. Siriani in view of Ban teach the method of claim 15 and Siriani further discloses forming electrical contacts in electrical communications with the III-V semiconductor material (the fabricator may incorporate various contact pads 610 to the optical assembly 600 via metallization (e.g., via evaporation or sputtering processes) so to add through silicon vias (TSVs), electrical leads, and passive connection points, Para [0045]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Ban (herein “Siriani / Ban”) as applied to claim 15 above, and further in view of Lee et al. (US 10,049,916 B2, herein “Lee”).
Regarding claim 16, Siriani / Ban teach a method of making a photonic integrated circuit of claim 15, but Siriani / Ban is silent to etching the trench comprises etching the trench at least partially into the silicon substrate.
Lee teaches the method of reducing threading dislocation density in the III-V substrate. The first step is to bond the III-V material (112), germanium as an example, between two semiconductor substrates (110, 108 in Fig. 1). Then the second semiconductor substrate (110) may be removed by etching (“submerging the combined substrate into a solution of tetramethylammonium hydroxide”, Col. 6, line 61 to Col. 7, line 14) to expose the dislocation defects on the germanium that is hidden at the interface between the germanium layer and the semiconductor layer 110) (Col. 6, lines 34-67).
It would have been obvious to one having ordinary skill at the time of filing to modify the invention of Siriani / Ban in accordance to Lee’s disclosure by etching the trench at least partially into the silicon substrate, where the dislocations are hidden, as the trench is the location where the III-V component 160 would reside. One would be motivated to etching partially into the silicon substrate is to expose the dislocations of the III-V at the interface between the III-V and the semiconductor layer. By exposing the dislocations, the following annealing step can effectively remove the dislocations, and ultimately produce a higher performing III-V substrate for placing optoelectronic devices thereon.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Siriani in view of Ban (herein “Siriani / Ban”) as applied to claim 15 above, and further in view of Warren et al. (US 2021/0020437 A1, herein “Warren”).
Siriani /Ban teach the method of claim 15, but Siriani / Ban do not teach the microscale patterns or sub-microscale patterns in the trench to suppress anti-phase domain formation in the III-V semiconductor material.
Warren teaches patterning the III-V semiconductor grown on silicon substrate with v-grooves can eliminate antiphase domain boundary formation – the creation of planar defect within a crystalline material where two regions of the same material, with different arrangements of atoms or structural variants, meet (Para [0023], Fig. 3). The groove period is approximately 500 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a photonic integrated circuit of Siriani with the technique of forming sub-microscale grooves to suppress anti-phase domain formation in the III-V semiconductor material, specifically in the trench provided for III-V component 160. One motivation would be to remove disruptions in the periodicity and symmetry of the crystal structure in the photonic devices. By suppressing this crystal defect, the trench is provided with a higher quality substrate for photonic devices to be disposed thereon.
Response to Arguments
Applicant's arguments filed 12/30/2025 have been fully considered but they are not persuasive.
Applicant argues the rejection of claim 1 do not anticipate all the limitations, in particular, Siriani do not explicitly disclose at least one of the waveguide or the III-V semiconductor waveguide is oriented parallel to a [110] direction of the silicon substrate.
The examiner addressed this limitation in the rejection above. The claim as broadly recited only requires the silicon waveguide or the III-V waveguide is oriented parallel to a [110] direction of the silicon substrate. Siriani teaches both waveguides are formed on the silicon substrate such that some part of the either waveguide volume would extends into the [110] direction of the underlying silicon substrate.
Regarding the remarks to claim 8, the rejection above addressed the new scope of claim 8. See the rejection to claim 8 for details.
Regarding the remarks to claim 15, the rejection above over Siriani in view of Ban addressed the amended limitation—epitaxially growing the III-V semiconductor material comprises growing gallium arsenide at a temperature between 550 degrees and 610 degrees Celsius—see rejection to claim 15 for details.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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