DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4 and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PG. Pub. 2012/0299888).
Regarding claim 1 – Kim teaches a circuit structure (figs. 1-4B [title] Kim states, “display panel”) for hot-press bonding (The preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.), the circuit structure comprising: a first substrate (fig. 4A, 100 [paragraph 0030] Kim states, “base substrate 100”); a first conductive layer (conductive layer including wirings CE1, DCE & CE2) comprising a plurality of connection electrodes (connection electrodes CE1 & CE2 [paragraph 0045] Kim states, “contact electrode CE1, the second contact electrode CE2”), the plurality of connection electrodes (CE1 & CE2) arranged in rows (figure 2 shows a rows of CE1 and CE2) and arranged on a planar surface of the first substrate (100); a second conductive layer (fig. 4A, conductive layer including wirings IPD1 & IPD2) comprising a plurality of backup electrodes (IPD1 & IPD2 [paragraph 0048] Kim states, “input pad IPD1…input pad IPD2”), each of the backup electrodes (IPD1 & IPD2) corresponding to one of the connection electrodes (CE1 & CE2) of the first conductive layer (see figs. 2 and 4A); an insulating layer (fig. 4A, IL [paragraph 0047] Kim states, “insulating layer IL”) arranged between the first conductive layer (conductive layer including wirings CE1, DCE & CE2) and the second conductive layer (conductive layer including wirings IPD1 & IPD2); a plurality of conductive vias (CH1 & CH2 [paragraph 0064] Kim states, “first contact hole CH1, a second contact hole CH2”) arranged in the insulating layer (IL); wherein multiple of the conductive vias (CH1 & CH2) are provided between each of the backup electrodes (IPD1 & IPD2) and a corresponding one of the connection electrodes (CE1 & CE2) such that multiple of the conductive vias (CH1 & CH2) provide current conduction paths between each of the backup electrodes (IPD1 & IPD2) and the corresponding one of the connection electrodes (CE1 & CE2; claimed structure shown in figure 4A); a second substrate (F-Sub [paragraph 0049] Kim states, “flexible substrate F-sub”); a plurality of conductive pads (F-CP [paragraph 0049] Kim states, “connecting pads F-CP”) arranged in a row (see row shown in figure 4A) and arranged on a planar surface of the second substrate (F-Sub), each of the conductive pads (fig. 4A-4B, F-CP) being corresponding to one of the connecting electrodes (CE1 & CE2) of the first substrate (100); and a conductive adhesive layer (ACL [paragraph 0049] Kim states, “anisotropic conductive adhesion layer ACL”) arranged between the plurality of connection electrodes (CE1 & CE2) of the first substrate (100) and the plurality of conductive pads (F-CP) of the second substrate (F-Sub) such that each of the connection electrodes (CE1 & CE2) is electrically connected to a corresponding one of the conductive pads (F-CP; claimed structure shown in figures 1-4B).
Regarding claim 2 – Kim teaches the circuit structure in claim 1, wherein the first substrate (fig. 4A, 100) is a rigid substrate ([paragraph 0030] Kim states, “base substrate 100 may be a glass substrate”) or a flexible substrate.
Regarding claim 4 – Kim teaches the circuit structure in claim 1, wherein the first conductive layer (fig. 4A, conductive layer including wirings CE1, DCE & CE2) is a transparent conductive layer ([paragraph 0045] Kim states, “Each of the first contact electrode CE1, the second contact electrode CE2 and the dummy contact electrode DCE may be formed of a transparent conductive material, i.e., indium-tin oxide”).
Regarding claim 10 – Kim teaches the circuit structure in claim 1, wherein the conductive adhesive layer (fig. 4A, ACL) is anisotropic conductive film (ACF) layer ([paragraph 0049] Kim states, “anisotropic conductive adhesion layer ACL”).
Regarding claim 11 – Kim teaches the circuit structure in claim 1, wherein the conductive adhesive layer (fig. 4A, ACL) is configured to bond the first substrate (100) and the second substrate (F-Sub) after pressing ([paragraph 0050] Kim states, “When the anisotropic conductive adhesion layer ACL is pressed by an external pressure”).
In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “circuit structure with bonded first and second substrates using a conductive adhesive layer”, does not depend on its method of production, i.e. “after heating and pressing”. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985).
Claim(s) 1, 3, 5-7 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaneko et al. (US Patent 5636329).
Regarding claim 1 – Kaneko teaches a circuit structure (figs. 3A-3E) for hot-press bonding ([column 5 lines 57-62] Kaneko states, “the flexible wiring substrate 31 of the tape-carrier package 300 is disposed on the provisionally bonded anisotropic conductive film 10 and then press-bonded under heating to electrically connect the copper foil wirings 31b to the terminal portions of the liquid crystals, respectively”), the circuit structure comprising: a first substrate (1 [column 3 line 24] Kaneko states, “substrate 1”); a first conductive layer (7-1 & 7-2 [column 6 lines 37-38] Kaneko states, “upper layer metal wirings 7-1 and 7-2”) comprising a plurality of connection electrodes (7-2), the plurality of connection electrodes (7-2) arranged in rows ([column line ] Kaneko states, “Referring now to FIG. 3, an actual active matrix substrate according to a first embodiment of the present invention has several hundreds of terminals arranged in parallel”) and arranged on a planar surface of the first substrate (1); a second conductive layer (2 [column 3 lines 11-12] Kaneko states, “a lower layer metal wiring 2 made of Cr”) comprising a plurality of backup electrodes (lower layer metal wiring 2 connected to each of the plurality of connection electrodes), each of the backup electrodes (2) corresponding to one of the connection electrodes (7-2) of the first conductive layer (7-1 & 7-2); an insulating layer (3 [column 3 line 11-12] Kaneko states, “an interlayer insulating film 3”) arranged between the first conductive layer (7-1 & 7-2) and the second conductive layer (2); a plurality of conductive vias (holes 6 having conductive metal therein) arranged in the insulating layer (3); wherein multiple of the conductive vias (holes 6 having conductive metal therein) are provided between each of the backup electrodes (2) and a corresponding one of the connection electrodes (7-2) such that multiple of the conductive vias provide current conduction paths between each of the backup electrodes and the corresponding one of the connection electrodes (claimed structure shown in figure 3E); a second substrate (31 [column 3 lines 29-30] Kaneko states, “copper foil wiring 31b of a flexible wiring substrate 31”); a plurality of conductive pads (see pads 31b in contact with conductive adhesive layer 10 [column 5 lines 40-42] Kaneko states, “a plurality of copper foil wirings 31b formed on a flexible insulating film 31a”) arranged in a row (row matching that of row of connection electrodes 7-2) and arranged on a planar surface of the second substrate (31), each of the conductive pads (31b) being corresponding to one of the connecting electrodes (7-2) of the first substrate (1); and a conductive adhesive layer (10 [column 5 line 37] Kaneko states, “anisotropic conductive film 10”) arranged between the plurality of connection electrodes (7-2) of the first substrate (1) and the plurality of conductive pads (31b) of the second substrate (31) such that each of the connection electrodes (7-2) is electrically connected to a corresponding one of the conductive pads (31b, claimed structure shown in figures 3A-3E).
Regarding claim 3 – Kaneko teaches the circuit structure in claim 1, wherein the second conductive layer (fig. 3E, 2) is a metal conductive layer ([column 3 lines 11-12] Kaneko states, “a lower layer metal wiring 2 made of Cr”).
Regarding claim 5 – Kaneko teaches the circuit structure in claim 1, wherein the first conductive layer (fig. 3E, 7-2) is a metal conductive layer ([column 3 line 15-16] Kaneko states, “upper layer metal wiring 7 made of Cr”).
Regarding claim 6 – Kaneko teaches the circuit structure in claim 1, further comprising a transparent conductive layer (fig. 3E, 8 [column 3 lines 18-19] Kaneko states, “transparent conductive film 8 made of Indium-Tin-Oxide (ITO)”) arranged on the first conductive layer (7-1 & 7-2), wherein the transparent conductive layer (8) comprises a plurality of transparent connection electrodes (transparent conductive layer 8 will be present on the plurality of connecting electrodes 7-2), each of the transparent connection electrodes (8) is corresponding and electrically connected to one of the connecting electrodes (7-2) of the first conductive layer (7-1 & 7-2).
Regarding claim 7 – Kaneko teaches the circuit structure in claim 1, wherein the conductive vias (figs. 3A-3E, holes 6 having conductive metal therein) are arranged along two long sides (see long sides of connecting electrode 7-2 shown in figure 3A) of each of the connecting electrodes (7-2).
Regarding claim 11 – Kim teaches the circuit structure in claim 1, wherein the conductive adhesive layer (fig. 3A-3D, 10 [column 5 line 37] Kaneko states, “anisotropic conductive film 10”) is configured to bond the first substrate (1) and the second substrate (31) after pressing ([column 5 lines 57-62] Kaneko states, “the flexible wiring substrate 31 of the tape-carrier package 300 is disposed on the provisionally bonded anisotropic conductive film 10 and then press-bonded under heating to electrically connect the copper foil wirings 31b to the terminal portions of the liquid crystals, respectively”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Lee et al. (US PG. Pub. 2019/0229446).
Regarding claim 9 – Kim teaches the circuit structure in claim 1, wherein the second substrate (fig. 4A, F-Sub) is a flexible substrate ([paragraph 0049] Kim states, “flexible substrate F-sub”) but fails to teach wherein the second substrate is a flexible polymer substrate.
Lee teaches a second substrate (fig. 2, BF) wherein the second substrate is a flexible polymer substrate ([paragraph 0092] Lee states, “The flexible board BF may be made of a flexible material, such as, e.g., polyimide”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit structure having a second substrate that is a flexible substrate as taught by Kim with the flexible substrate being made of a polymer as taught by Lee because polymer material is known to be highly flexible without cracking, lightweight and durable.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al.
Regarding claim 8 – Kaneko teaches the circuit structure in claim 7, wherein an extended length (annotated figure 3A below, D2) of the conductive vias (fig. 3A, holes 6 having conductive metal therein) is more than 70% of a length (D1) of the connecting electrode (7-2; claimed structure shown in annotated figure 3A below and appears to meet the claimed limitation).
Kaneko does not explicitly teach wherein the separation between two adjacent conductive vias is not greater than twice a diameter of the conductive vias.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the separation between two adjacent conductive vias being not greater than twice a diameter of the conductive vias, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Please note that in the instant application, paragraphs 0038 & 0044, applicant has not disclosed any criticality for the claimed limitations. Having high density via configurations allow for increased routing capacity, enhanced thermal management and reduced signal noise.
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kita et al. (US Patent 9651836) discloses a display device.
Kim (US Patent 7903222) discloses a liquid crystal display.
Aruga (US Patent 6833900) discloses an electro-optical device.
Yoo et al. (US PG. Pub. 2002/0044250) discloses a pad structure for liquid crystal display.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847