Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2, 7, 11, and 19 objected to because of the following informalities.
Regarding claim 2:
Claim 2 recites “repeating the operations to create a second blocked circuit, the second blocked circuit representing gates of the quantum circuit that is mutually exclusive from gates representing the first blocked circuit.” Examiner respectfully suggests that “is” should be “are.” As written, the verb “is” acts on the singular noun “the quantum circuit,” which means the “gates representing the first blocked circuit” are mutually exclusive of “the quantum circuit.” However, in claim 1, upon which claim 2 depends, the “gates representing the first blocked circuit” were drawn from “the quantum circuit” are therefore the circuit is not mutually exclusive from the gates. Examiner’s expectation from the specification is that the “gates representing the first blocked circuit” are intended to be mutually exclusive from the gates of “the second blocked circuit.” Claim 2 will be interpreted with this meaning in further examination below.
Regarding claims 7 and 11:
Claims 7 and 11 recite “determining whether the distance of the blocked quantum circuit and the composed block quantum circuit is below a particular threshold.” The preposition “of” used to modify a singular “distance” is non-standard English and therefore the language could suggest the determining of two separate distances. Examiner respectfully suggests using a standard form such as “distance between A and B” or “distance from A to B.”
Further, the phrase “the distance of the blocked quantum circuit and the composed block quantum circuit” lacks antecedent basis in either claim 7 or claim 11. Examiner suggests considering whether “the distance” should be “a distance.”
Regarding claim 19:
Applicant is advised that should claim 7 found allowable, claim 19 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1:
Claim 1 recites the term “bit.” A person having ordinary skill in the art cannot determine from the context of the claim whether “bit” is intended to mean a bit (binary digit) in a classical computing portion of a circuit, or whether “bit” is merely a synonym for “qubit” (quantum bit). In further examination below, “bit” in the claims will be read as “qubit.”
Further, the phrase “a one-bit or two-qubit quantum circuit,” in plain reading, with “bit” read as “qubit,” recites a circuit containing one or two qubits, which renders later phrases such as “a set of three-or-more-qubit blocks” logically inconsistent. Examiner suggests the intention was that the qubit gates in the circuit each operate on either one or two qubits, and in further examination below, the preamble will be read as such.
Further, claim 1 recites a “qubit frontier” (“for each qubit gate of a plurality of qubit gates of a quantum circuit within a qubit frontier of a circuit operation of one or more qubit gates of the circuit […]”). Neither the claim nor the specification defines “qubit frontier” to allow a person having ordinary skill in the art to determine whether something is within “a qubit frontier of a circuit operation.” Further, the wording is ambiguous as to whether the entire “quantum circuit” or merely “a plurality of qubit gates of a quantum circuit ” lies within “a qubit frontier.” In further examination below, the phrase “for each qubit gate of a plurality of qubit gates of a quantum circuit within a qubit frontier of a circuit operation of one or more qubit gates of the circuit” will be interpreted as a process that includes every qubit gate in a distinguishable group.
Further, the claim recites:
for each respective three-qubit block of the set of three-or-more-qubit blocks, determining a block family with a highest number of available operations that starts with the respective three-or-more-qubit block and adheres to restriction zones of the blocks
This limitation recites “each respective three-qubit block” but later recites “the respective three-or-more-qubit block” (emphasis added). A person having ordinary skill in the art cannot determine whether these blocks are the same block. In further examination below, “each respective three-qubit block” will be read as “each respective three-or-more-qubit block.”
Further, the claim recites “adding a three-or-more-qubit block having a highest number of operations to a blocked circuit.” Previously, the claim recited “determining a block family with a highest number of available operations that starts with the respective three-or-more-qubit block and adheres to restriction zones of the blocks.” A person having ordinary skill in the art cannot determine whether the claim recites adding A) the entire “block family” that was found to have the highest number of operations, B) a “three-or-more-qubit block” that was separately determined to have the highest number of operations, or C) the “three-or-more-qubit block” that started the “block family” that was found to have the highest number of operations.
Further, the claim language makes indefinite the interaction among the following limitations, with labels A-C added for reference:
[A] determining a number of operations of at least a subset of blocks in the set of three-or-more-qubit blocks,
[B] determining a family of blocks with a highest number of operations,
[C] for each respective three-qubit block of the set of three-or-more-qubit blocks, determining a block family with a highest number of available operations that starts with the respective three-or-more-qubit block and adheres to restriction zones of the blocks
A plain reading makes no explicit connection among limitations A, B, and C; that is, the method includes steps A, B, and C, but the performance of step A does not affect steps B or C, and the performance of step B does not affect step C. However, the intended meaning may be that C is an elaboration of the methods of steps A and B. A person having ordinary skill in the art would be unable to determine which of these interpretations is correct. Examiner notes that the meaning of dependent claims rely on this interpretation; for example, claim 10, which limits the “determining a number of operations of at least a subset of blocks,” has no effect on the which block is added to the circuit unless step A is interpreted as a sub-step of steps B and C.
In further examination below, the sequence of limitations labelled A-C above will be read as adding to the blocked circuit, the block family with the highest number of available operations that starts with the respective three-or-more-qubit block and adheres to restriction zones of the blocks.
Further, the limitation “adding a three-or-more-qubit block having a highest number of operations to a blocked circuit” is performed in the context of iteration as part of “for each qubit gate of a plurality of qubit gates of a quantum circuit within a qubit frontier of a circuit operation of one or more qubit gates of the circuit.” Thus, each iteration adds a block “to a blocked circuit,” but it is indefinite whether this is the same block for each iteration. In further examination below, the limitation will be read as adding to the same blocked circuit; that is, that the iterative process builds a blocked circuit from individual blocks.
Regarding claims 2-10:
These claims are dependent on claim 1 and are rejected by the same reasoning.
Regarding claim 11:
Claim 1 recites the term “bit.” A person having ordinary skill in the art cannot determine from the context of the claim whether “bit” is intended to mean a bit (binary digit) in a classical computing portion of a circuit, or whether “bit” is merely a synonym for “qubit” (quantum bit). In further examination below, “bit” in the claims will be read as “qubit.”
Regarding claims 12-20:
These claims are dependent on claim 11 and are rejected by the same reasoning.
Regarding claims 8 and 20:
Separately from the rejections listed above for dependency on rejected claim 1 or 11, claims 8 and 20 further recite “interfacing with a quantum computer as the computer runs a program, and iterating the operations for different instructions than the quantum computer is executing.” There is insufficient antecedent basis for “the operations” in the claims. A person having ordinary skill in the art would be unable to determine what “the operations” refers to.
Regarding claim 19:
Separately from the rejection listed above for dependency on rejected claim 11, this dependent claim uses the same indefinite language as claim 1 and is rejected by the same reasoning.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, and 9-10 rejected under 35 U.S.C. 102(a) (1) as being anticipated by Wu et al., “QGo: Scalable Quantum Circuit Optimization Using Automated Synthesis,” March 2022, arXiv:2012.09835v5 (hereafter Wu).
Regarding claim 1:
Wu teaches:
“A method of converting a one-bit or two-qubit quantum circuit to a three-or-more-qubit quantum circuit, the method comprising”: Wu, section I, paragraph 1, “Quantum circuit synthesis provides an orthogonal circuit optimization method [A method ], which generates a circuit from its high level mathematical description such as unitary matrix.”
“for each qubit gate of a plurality of qubit gates of a quantum circuit within a qubit frontier of a circuit operation of one or more qubit gates of the circuit”: Wu, section III. C, paragraph 1, “QGo partitions a circuit into multiple small circuit blocks. Each block contains gates only on a small group of qubits. Figure 1 shows an example of partitioning. Each circuit block consists of 3 qubits (Figure 1(b))”; Wu, Fig. 1:
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[showing that all qubit gates withing the original circuit, (a distinguishable group of qubits and hence interpreted as a qubit frontier, are processed as part of the partitioning operation, therefore for each qubit gate of a plurality of qubit gates of a quantum circuit within a qubit frontier of a circuit operation of one or more qubit gates of the circuit ]
“determining a set of three-or-more-qubit blocks from the qubit frontier to an interior of the circuit”: Wu, section III. C, paragraph 3, “The qubit group size k is limited to a small number due to the limitation of quantum synthesis. In this paper, we focus our analysis on the size of 3 and 4 qubits in a qubit group”; Wu, Algorithm 1,
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[showing step 5, determining a set of three-or-more-qubit blocks from the qubit frontier to an interior of the circuit]
“determining a number of operations of at least a subset of blocks in the set of three-or-more-qubit blocks”: Wu, section III. C, paragraph 8, “The heuristic cost function indicates the number of executable gates for a qubit group. The general form of our heuristic cost function for a qubit group Qi is shown as follows: Score(EQi) = NEQi, where NEQi is the number of executable CNOT gates on Qi [a number of operations]”); Wu, Algorithm 1,
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[showing step 7, determining a number of operations of at least a subset of blocks in the set of three-or-more-qubit blocks]
“determining a family of blocks with a highest number of operations”: Wu, Algorithm 1,
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[showing step 9, determining a family of blocks with a highest number of operations].
“for each respective three-qubit block of the set of three-or-more-qubit blocks, determining a block family with a highest number of available operations that starts with the respective three-or-more-qubit block and adheres to restriction zones of the blocks, and adding a three-or-more-qubit block having a highest number of operations to a blocked circuit”: Wu, section III. C, paragraph 4, “Since the input circuit for our partitioning algorithm is a physical qubit mapped circuit, all two-qubit gates are applied on the neighbor qubits. We can define valid qubit groups by considering device connectivity to reduce the search space in our algorithm. We map the qubit group onto the device connectivity graph. If a qubit group is a connected component, it is a valid qubit group; otherwise, it is an invalid group [hence, the determination of qubit groups adheres to restriction zones of the blocks]”; Wu, Algorithm 1,
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[showing step 9, determining a block family with a highest number of available operations that starts with the respective three-or-more-qubit block and adheres to restriction zones of the blocks, and step 10, adding a three-or-more-qubit block having a highest number of operations to a blocked circuit].
“wherein each of the plurality of qubit gates is a one-bit or two-bit qubit gate of fewer bits than a number of bits of the three-or-more-qubit blocks”: Wu, Fig. 1:
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; Wu, Section III. C, paragraph 6, “Executable gates on a qubit group. A single-qubit gate on can count as an executable gate on a qubit group Qi only when qi ∈ Qi and all previous gates on are executable gates on Qi. A two-qubit gate on (qi, qj) can count as an executable gate on a qubit group only when both qi, qj ∈ Qi and all previous gates on qi and qj are executable gates on Qj. [showing that the process operates on one-bit or two-bit qubit gate, each of which would have fewer bits than a number of bits of the three-or-more-qubit blocks, “bit” read as “qubit.”]
Regarding claim 2:
Wu teaches “The method of Claim 1.”
Wu further teaches “wherein the blocked circuit is a first blocked circuit, the method further comprising: repeating the operations to create a second blocked circuit, the second blocked circuit representing gates of the quantum circuit that is mutually exclusive from gates representing the first blocked circuit”: Wu, Fig. 1:
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[showing the circuit partitioning as an iterative process, in which each block, interpreted as a separate blocked circuit, is made of mutually exclusive gates from the original circuit, hence, wherein the blocked circuit is a first blocked circuit, the method further comprising: repeating the operations to create a second blocked circuit, the second blocked circuit representing gates of the quantum circuit that is mutually exclusive from gates representing the first blocked circuit].
Regarding claim 3:
Wu teaches “The method of Claim 1.”
Wu further teaches “wherein the qubit gates are at least one of a neutral atom qubit gate, a superconducting qubit gate, and a photon-based qubit gate”: Wu, section II. B, paragraph 1, “However, most current quantum devices can perform continuously varying gates. For example, superconducting qubits [a superconducting qubit gate] use virtual Z rotations, which can be performed with any angle, and trapped ion qubits can perform X and Y rotations with any angle.”
Regarding claim 5:
Wu teaches “The method of Claim 1.”
Wu further teaches “wherein the blocked circuit can change over time or for executing different instructions”: Wu, section III. D, paragraph 1, “After the circuit is partitioned into multiple blocks, QGo applies quantum synthesis for each circuit block [wherein the blocked circuit can change over time, interpreted as including changing the block over multiple process stages]. We integrate the state-of-the-art synthesis tool proposed in [21] into our QGo framework. For each circuit block, QGo computes the corresponding unitary matrix, and this matrix is the input for the synthesis process. As the synthesized circuit should respect the hardware topology, the qubit group for each block and the device connectivity are also the input parameters for the synthesis tool.”
Regarding claim 6:
Wu teaches “The method of Claim 1.”
Wu further teaches “wherein the restriction zones of the blocks are based on qubits being restricted from engaging in quantum operations depending on nearby qubit activity”: Wu, section III. C, paragraph 4, “Since the input circuit for our partitioning algorithm is a physical qubit mapped circuit, all two-qubit gates are applied on the neighbor qubits. We can define valid qubit groups by considering device connectivity to reduce the search space in our algorithm. We map the qubit group onto the device connectivity graph. If a qubit group is a connected component, it is a valid qubit group; otherwise, it is an invalid group [qubits being restricted from engaging in quantum operations depending on nearby qubit activity, interpreted as including restricting qubit selection into groups based on a qubit being available for computation to others in the group].”
Regarding claim 9:
Wu teaches “The method of Claim 1.”
Wu further teaches “wherein the set of three-or-more qubit blocks is a set of three-qubit blocks”: Wu, section III. C, paragraph 3, “The qubit group size k is limited to a small number due to the limitation of quantum synthesis. In this paper, we focus our analysis on the size of 3 [wherein the set of three-or-more qubit blocks is a set of three-qubit blocks] and 4 qubits in a qubit group.”
Regarding claim 10:
Wu teaches “The method of Claim 1.”
Wu further teaches “wherein determining a number of operations of at least a subset of blocks in the set of three-or-more-qubit blocks is determining a number of operations of all blocks in the set of three-or-more-qubit blocks”: Wu, Algorithm 1,
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[showing steps 5-7, which is determining a number of operations of all blocks in the set of three-or-more-qubit blocks].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 rejected under 35 U.S.C. 103 over Wu in view of Kempe et al., “Exact gate-sequences for universal quantum computation using the XY-interaction alone,” 2002, arXiv:quant-ph/0112014v2 (hereafter Kempe).
Wu teaches “The method of Claim 1.”
Wu does not explicitly teach “wherein the qubits are arranged in a triangular grid.”
Kempe teaches “wherein the qubits are arranged in a triangular grid”: Kempe, section V, paragraph 1, “The triangular arrangement [wherein the qubits are arranged in a triangular grid] allows for all possible interactions between the three qubits that make up an encoded truncated qubit or an encoded qutrit, using only nearest neighbor interactions. This allows application of the P3 gate on the three qubits of the triangle using only nearest neighbor interactions. The arrangement of the triangles is such, that there is always a triangular shape between two qubits of one triangle and one qubit of the next. This way we can always apply a P3 gate between two qubits of one encoded qutrit and one qubit of the other, which is sufficient to implement the entangling gates also using only nearest neighbor interactions.”
Kempe and Wu are analogous arts as they are both related to quantum computing methods. It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the triangular qubit arrangement of Kempe with the teachings of Wu to arrive at the present invention, in order to allow reliance on nearest-neighbor interactions, as stated in Kempe, section V, paragraph 1, “This way we can always apply a P3 gate between two qubits of one encoded qutrit and one qubit of the other, which is sufficient to implement the entangling gates also using only nearest neighbor interactions.”
Claim 8 rejected under 35 U.S.C. 103 over Wu in view of Thompson et al., US Pre-Grant Publication No. 2021/0398007 (hereafter Thompson).
Wu teaches “The method of Claim 1.”
Wu does not explicitly teach “interfacing with a quantum computer as the computer runs a program, and iterating the operations for different instructions than the quantum computer is executing.”
Thompson teaches “interfacing with a quantum computer as the computer runs a program, and iterating the operations for different instructions than the quantum computer is executing”: Thompson, paragraphs 0037—0038, “In managing quantum process 132 and quantum process 134 [interfacing with a quantum computer as the computer runs a program], process manager 130 may distribute the same process to these quantum computers. The same process may be run on the quantum computers for purposes of determining the performance of these quantum computers in running the same process. As another example, the same process may be used to perform tasks for shared processing such as grid computing. However, instructions 136 and instructions 138 for the same process may be different [iterating the operations for different instructions than the quantum computer is executing]. The different instructions may result from at least one of a different programming language or different hardware components in quantum computer 112 and quantum computer 114.”
Thompson and Wu are analogous arts as they are both related to quantum computing methods. It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to have combined the different instruction sets of Thompson with the teachings of Wu to arrive at the present invention, in order to tune instructions for different quantum hardware, as stated in Thompson, paragraph 0039, “In this manner, a single process can be turned into instructions for execution on different hardware systems such as quantum computer 112 and quantum computer 114 that may be of different computer types.”
Allowable Subject Matter
Claims 7 and 11-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and any objections set forth in this Office action, and further, for claim 7, if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claims 7 and 11:
Claims 7 and 11 recite an iterative method of composing a quantum circuit by adding parameterized layers until the distance of the composed quantum circuit and the original quantum circuit falls below a threshold, recited as:
(a) based on an input block quantum circuit comprising a plurality of one-qubit gates and two-qubit gates, determining a parameterized layer of three-or-more-qubit gates;
(b) adding the determined parameterized layer to a composed block quantum circuit;
(c) determining whether the distance of the input block quantum circuit and the composed block quantum circuit is below a particular threshold;
(d)(1) if the distance is below the particular threshold, outputting the composed block quantum circuit; and
(d)(2) if the distance is equal to or above the particular threshold, repeating (a)-(d)
Among the closest arts, Lee et al., US Patent No. 10,922,460, teaches a method of composing a quantum circuit by the iterative addition of parameterized layers, including a threshold comparison and performance measure, as shown in Lee, Fig. 5,
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However, the performance measure in Lee is not the distance measurement of the claims, and the threshold is related to the number of sub-circuit blocks.
Khatri et al., “Quantum-assisted quantum compiling,” 2019, arXiv:1807.00800v5, teaches a method of iterating over parameters of a trainable quantum network to approximate a target network (Khatri, page 2, “The goal of QAQC is to compile a (possibly unknown) target unitary to a trainable quantum gate sequence”; Khatri, Fig. 2 caption, “For each iteration of the continuous parameter optimization, we calculate the cost using the Hilbert-Schmidt Test (HST)”). However, the method of Khatri does not include iteratively adding parameterized layers, and the Hilbert-Schmidt Test, while related to the Hilbert-Schmidt distance measure, is not itself a distance measure.
Wu teaches that a quantum circuit synthesized from partitioned blocks may have a distance from the original, but states that the distance has negligible impact (Wu, page 6, “After the synthesis, there is an undesired synthesis distance due to numerical approximation, leading the final unitary at a
distance from the original unitary [21,51,70]. As a result, the final unitary distance is in the range of 10-10 to 10-15. In the NISQ era, when running a quantum circuit on a real machine, the unitary executed is different from the original intended unitary due to the presence of noise. Since gate errors are multiple orders of magnitudes larger than synthesis distances, these synthesis distances are insignificant”). Further, Wu does not compose circuits using three-qubit gates.
Xu et al., “Variational circuit compiler for quantum error correction,” 2021, arXiv:1911.05759v2, teaches a method of optimizing a parameterized quantum circuit to minimize the energy between the circuit and a target (Xu, page 4, “Suppose the ground state of the Hamiltonian H can be represented by the circuit ansatz, then the problem is rephrased as finding an set of parameters θmin which minimises the energy
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”). However, Xu does not compose a circuit into three-qubit blocks.
Thus the method of the claims is not taught by any prior art, nor is there any combination of prior arts that would have arrived at the presently claimed invention that would have been obvious to a person having ordinary skill in the art as of the effective filing date of the present invention.
Regarding claims 12-20:
These claims are dependent on claim 11 and therefore have allowable subject matter by the same reasoning.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gokhale, WIPO Application No. 2021/050541, discloses a quantum computing system which divides a quantum circuit into blocks for processing on a quantum computer.
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/VAS/Examiner, Art Unit 2129
/MICHAEL J HUNTLEY/Supervisory Patent Examiner, Art Unit 2129