DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because:
Contains more than 150 words.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 5 is objected to because of the following informalities:
Claim 5 recites “…, wherein the plurality of phases include…”. However, it appears that it should recite “…, wherein the plurality of phases includes….
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7 – 10 and 14 - 15 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Arno (US Pub. No. 2014/0070787 A1); (hereinafter Arno).
Regarding claim 1, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses a circuit comprising: a switched capacitor voltage converter [e.g., -- refer to Fig. 7 for multilevel converter --] that includes a plurality of phases coupled between an input terminal and an output terminal [e.g., plurality of capacitor modules 5(i) between input terminal 54 and output terminal 52], wherein the plurality of phases each include a capacitor and switches [e.g., plurality of capacitor modules 5(i) containing capacitors 7(i)], and wherein the plurality of phases include: a first phase to operate in a switching mode to generate an output voltage at the output terminal based on an input voltage at the input terminal [e.g., -- refer to Fig. 11A --, top phase containing capacitor 7(3) operated to generated intermediate output voltage VLX]; and a second phase that is selectively operable in the switching mode or in a decoupling mode [e.g., rest of capacitor modules 5(i) conducting to ground], wherein, when the second phase is in the decoupling mode [e.g., -- refer to Fig. 11A --], the capacitor of the second phase is coupled between the output terminal and ground [e.g., rest of capacitor module 5(i) coupled between node N1 and grounded terminal when capacitor module containing capacitors 7(2) and 7(1) are conducting to ground. For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected in a way that allows for the transfer of electrical energy or signals between them]; and a control circuitry coupled to the second phase [e.g., -- refer to Fig. 14 --, master module 57 coupled to all capacitor modules], the control circuitry to operate the second phase in the decoupling mode while the first phase is in the switching mode [e.g., -- refer to Fig. 11A --, top capacitor module conducting to node N1 while rest of capacitor modules are conducting to ground], and to operate the second phase in the switching mode while the first phase is in the switching mode [e.g., -- refer to Fig. 12B --, operates all capacitor modules accordingly, p. 0163 recites “During the second phase the charge pump is in discharging mode (FIG. 12B). The capacitors 7(i) are all connected between the input terminal 54 and the first circuit node N1. The switches are connected in such a way that the capacitors 7(i) are mounted in parallel with each others. The switches are connected in a way such as to create a low resistive path from the capacitors 7(i) to the first circuit node N1. The switches are further connected in such a way that the stored charge opposes the input signal Vbat. A preferable way to do it is illustrated in FIG. 12B: the first terminal 720 of each capacitor 7(i) that was connected to the input terminal during the charging mode is connected to the input terminal 54 and the second terminal 730 of each capacitor 7(i) that was connected to the ground during the charging mode is now connected to the first circuit node N1. As a consequence, the intermediate output voltage VLX node is equal to Vbat minus Vbat/3 which is 2/3Vbat.”].
Regarding claim 4, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein the output voltage is less than the input voltage [e.g., -- refer to Fig. 11A and 12B --, intermediate voltage at node N1, VLX = 2/3 Vbat].
Regarding claim 7, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein the switches of the respective phases include: a first switch coupled between the input terminal and a first terminal of the capacitor [e.g., SW1 (shown in reference drawing attached) coupled Vbat and bottom terminal capacitor 7(3)]; a second switch coupled between the output terminal and a second terminal of the capacitor [e.g., SW2 coupled between node N1 and top terminal of capacitor 7(3)]; a third switch coupled between the output terminal and the first terminal of the capacitor [e.g., SW3 coupled between node N1 and bottom terminal of capacitor 7(3)]; and a fourth switch coupled between the second terminal of the capacitor and a ground terminal [e.g., SW4 coupled between top terminal of capacitor 7(3) and ground via Vbat. For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected in a way that allows for the transfer of electrical energy or signals between them].
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Regarding claim 8, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein, in the switching mode [e.g., -- refer to Fig. 12B --], the first and second switches are responsive to a first control signal [e.g., switches SW1 and SW2 controlled by a first control signal to open] and the third and fourth switches are responsive to a second control signal [e.g., SW3 and SW4 responsive to a second control signal different than first control signal to close], and wherein, in the decoupling mode [e.g., -- refer to Fig. 11A --], the control circuitry is to maintain the first and second switches in an open state [e.g., -- refer to Fig. 11A --, switch SW1 and SW2 open] and the third and fourth switches in a closed state [e.g., SW3 and SW4 closed].
Regarding claim 9, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein, in the switching mode [e.g., -- refer to Fig. 12B --], the first and second phases are to generate the output voltage using pulse frequency modulation or pulse width modulation [e.g., master module 57 controlling switches via PWM1 – PWM4, p. 0174 recites “The master module 57 is then adapted to calculate a difference between the output signal Vout and the desired output signal Vref and dictate the switching range of the charge pump 56 or modify the duty cycle in order to reduce this difference. This difference may be processed by the way of an error signal Verror. To calculate the error signal Verror, the master module 57 makes use of an error amplifier 60 using the output signal Vout and the desired output signal Vref as inputs.”].
Regarding claim 10, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses a switched capacitor voltage converter [e.g., -- refer to Fig. 7 for multilevel converter --] comprising: a first phase coupled between an input and an output of the switched capacitor voltage converter [e.g., capacitor module 5(i) between input terminal 54 and output terminal 52], wherein the first phase includes a first capacitor and a first set of switches [e.g., top capacitor module 5(i) containing corresponding capacitor 7(i) and switches], and wherein the first phase is to operate in a switching mode in which the first set of switches open and close to generate an output voltage at the output based on an input voltage at the input [e.g., -- refer to Fig. 12B --, generates voltage VLX based on Vbat]; a second phase coupled in parallel with the first phase [e.g., second capacitor module 5(j) containing capacitor 7(j)], wherein the second phase includes a second capacitor and a second set of switches [e.g., second capacitor module 5(j) containing corresponding capacitor 7(j) with switches], wherein the second phase is to operate in a decoupling mode in which the second capacitor is maintained as coupled between the output and a ground terminal [e.g., -- refer to Fig. 11A --, top capacitor module 5(i) conducting to node N1 while rest of capacitor modules conducting to ground], and wherein the second phase is further to transition from the decoupling mode to the switching mode [e.g., -- refer to Fig. 12B --, transitions from charging and discharging modes, p. 0163 recites “During the second phase the charge pump is in discharging mode (FIG. 12B). The capacitors 7(i) are all connected between the input terminal 54 and the first circuit node N1. The switches are connected in such a way that the capacitors 7(i) are mounted in parallel with each others. The switches are connected in a way such as to create a low resistive path from the capacitors 7(i) to the first circuit node N1. The switches are further connected in such a way that the stored charge opposes the input signal Vbat. A preferable way to do it is illustrated in FIG. 12B: the first terminal 720 of each capacitor 7(i) that was connected to the input terminal during the charging mode is connected to the input terminal 54 and the second terminal 730 of each capacitor 7(i) that was connected to the ground during the charging mode is now connected to the first circuit node N1. As a consequence, the intermediate output voltage VLX node is equal to Vbat minus Vbat/3 which is 2/3Vbat.”].
Regarding claim 14, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein the second set of switches includes: a first switch coupled between the input of the switched capacitor voltage converter and a first terminal of the second capacitor [e.g., SW1 (shown in reference drawing attached) coupled to Vbat and top terminal capacitor 7(3)]; a second switch coupled between the output of the switched capacitor voltage converter and a second terminal of the second capacitor [e.g., SW2 coupled between node N1 and bottom terminal of capacitor 7(2)]; a third switch coupled between the output of the switched capacitor voltage converter and the first terminal of the second capacitor [e.g., SW3 coupled between node N1 and top terminal of capacitor 7(2)]; and a fourth switch coupled between the second terminal of the second capacitor and a ground terminal [e.g., SW4 coupled between bottom terminal of capacitor 7(2) and ground].
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Regarding claim 15, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein: when the second phase is in the switching mode [e.g., -- refer to Fig. 12B -- ], the first and second switches are responsive to a first control signal [e.g., SW1 and SW2 responsive to a first control signal to close] and the third and fourth switches are responsive to a second control signal [e.g., SW3 and SW4 responsive to a second control signal to open]; and when the second phase is in the decoupling mode [e.g., -- refer to Fig. 11A --], the first and second switches are maintained in an open state [e.g., SW1 and SW2 shown in an open state] and the third and fourth switches are maintained in a closed state [e.g., first and second switches conducting (closed) and third and fourth switch non-conducting (open)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Arno (US Pub. No. 2014/0070787 A1) in view of Yanagida et al (US Pub. No. 2007/0279021 A1); (hereinafter Arno and Yanagida et al)
Regarding claim 2, Arno discloses the claimed invention except for wherein the control circuitry transitions the second phase from the decoupling mode to the switching mode based on a voltage across the capacitor of the first phase.
Yanagida et al [e.g., Fig. 7] teaches wherein the control circuitry [e.g., controller] is to transition the second phase from the decoupling mode to the switching mode based on a voltage across the capacitor of the first phase [e.g., controller CNT control switches of charge pumps CP1 – CP3 to charge first capacitor during start-up, p. 0094 recites “Next a description will be given of a case where the output logic levels of the first and second detectors DET1 and DET2 are both low. In this case, in view of the output logic level of the second detector DET2, the controller CNT recognizes that the charge pump circuit is still in the process of start-up and therefore that there is a risk of in-rush current. Moreover, in view of the output logic level of the first detector DET1, the controller CNT recognizes that the charge level of the battery 1 (i.e., the level of the input voltage Vin) is low and therefore that there is little risk of a large in-rush current flowing in. Accordingly, based on the above recognition, the controller CNT so operates as to increase to a sufficiently but not unduly high level the on-state resistance of the current path for the charging of the first capacitor C1; to achieve that, the controller CNT produces the control signals CK1B1-3 such that, of the transistors P1 to P3, only the transistor P2--the one having the second smallest W/L ratio (i.e., the second highest on-state resistance)--is driven while the other transistors P1 and P3 are left undriven (kept off). In this operation state, the negative voltage generation circuit 21 can reduce in-rush current at start-up without causing a shortage in the output voltage Vout or a loss in efficiency even when the battery is battery is almost depleted.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein the control circuitry is to transition the second phase from the decoupling mode to the switching mode based on a voltage across the capacitor of the first phase as suggested by Yanagida et a to reduce in-rush current at start-up without causing a shortage in the output voltage Vout or a loss in efficiency even when the battery is battery is almost depleted.
Claim(s) 3, 5 – 6, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Arno (US Pub. No. 2014/0070787 A1) in view of Chen et al (US Pub. No. 2022/0166314 A1); (hereinafter Arno and Chen et al).
Regarding claim 3, Arno discloses the claimed invention except for wherein the control circuitry is to operate the second phase in the decoupling mode during startup of the switched capacitor voltage converter.
Chen et al [e.g., Fig. 11] teaches wherein the control circuitry is to operate the second phase in the decoupling mode during startup of the switched capacitor voltage converter [e.g., operates capacitor 98 with switch 100 during startup, p. 0074 recites “To achieve the maximum efficiency and power density, the VSU and the CSU should be directly connected as one submodule without a filter capacitor in between to hold the intermediate voltage bus. However, a small capacitance is needed during the startup process to ensure the capacitors of the VSUs are pre-charged to the desired voltage level needed by steady state operation. One solution is to add a capacitor 98 connected in series with a switch 100 on the intermediate bus between the VSU 12 and the CSU 14, as illustrated in FIG. 11. This capacitor 98 is connected to the intermediate bus during the startup and transient process and is disconnected from the intermediate bus during steady state operation. As a result, in steady state, the CSU 14 operate as a current source and soft-charge the capacitors in the VSU 12.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein the control circuitry is to operate the second phase in the decoupling mode during startup of the switched capacitor voltage converter as suggested by Chen et al to ensure the capacitors of the switched capacitor converter are pre-charged to the desired voltage level needed by steady state operation during startup process.
Regarding claim 5, Arno [e.g., Figs. 7, 11A, 11B and 14] discloses wherein the plurality of phases include more than two phases [e.g., contains plurality of capacitor modules 5(i)].
Arno does not disclose wherein the first phase is part of a subset of two or more of the phases that operate in the switching mode while the second phase is in the decoupling mode.
Chen et al [e.g., Fig. 11] teaches wherein the first phase is part of a subset of two or more of the phases that operate in the switching mode while the second phase is in the decoupling mode [e.g., modular voltage splitting units 12 (VSUs) operating during startup mode and disconnected when converter reaches steady state operation, p. 0074 recites “To achieve the maximum efficiency and power density, the VSU and the CSU should be directly connected as one submodule without a filter capacitor in between to hold the intermediate voltage bus. However, a small capacitance is needed during the startup process to ensure the capacitors of the VSUs are pre-charged to the desired voltage level needed by steady state operation. One solution is to add a capacitor 98 connected in series with a switch 100 on the intermediate bus between the VSU 12 and the CSU 14, as illustrated in FIG. 11. This capacitor 98 is connected to the intermediate bus during the startup and transient process and is disconnected from the intermediate bus during steady state operation. As a result, in steady state, the CSU 14 operate as a current source and soft-charge the capacitors in the VSU 12.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein the first phase is part of a subset of two or more of the phases that operate in the switching mode while the second phase is in the decoupling mode as suggested by Chen et al to ensure the capacitors of the switched capacitor converter are pre-charged to the desired voltage level needed by steady state operation during startup process.
Regarding claim 6, Arno does not disclose wherein the subset is a first subset, and wherein the second phase is part of a second subset of two or more of the phases that are selectively operable in the switching mode or the decoupling mode.
Chen et al [e.g., Fig. 11] teaches wherein the subset is a first subset [e.g., sets containing plurality of Voltage Splitting Units 12], and wherein the second phase is part of a second subset of two or more of the phases that are selectively operable in the switching mode or the decoupling mode [e.g., capacitors 98 and switches 100 connected between Voltage Splitting Units 12 and Current Splitting Units 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein the subset is a first subset, and wherein the second phase is part of a second subset of two or more of the phases that are selectively operable in the switching mode or the decoupling mode as suggested by Chen et al to ensure the capacitors of the switched capacitor converter are pre-charged to the desired voltage level needed by steady state operation during startup process.
Regarding claim 11, Arno discloses the claimed invention except for wherein the second phase is to operate in the decoupling mode during startup of the switched capacitor voltage converter.
Chen et al [e.g., Fig. 11] teaches wherein the second phase is to operate in the decoupling mode during startup of the switched capacitor voltage converter [e.g., operates capacitor 98 with switch 100 during startup, p. 0074 recites “To achieve the maximum efficiency and power density, the VSU and the CSU should be directly connected as one submodule without a filter capacitor in between to hold the intermediate voltage bus. However, a small capacitance is needed during the startup process to ensure the capacitors of the VSUs are pre-charged to the desired voltage level needed by steady state operation. One solution is to add a capacitor 98 connected in series with a switch 100 on the intermediate bus between the VSU 12 and the CSU 14, as illustrated in FIG. 11. This capacitor 98 is connected to the intermediate bus during the startup and transient process and is disconnected from the intermediate bus during steady state operation. As a result, in steady state, the CSU 14 operate as a current source and soft-charge the capacitors in the VSU 12.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with w wherein the second phase is to operate in the decoupling mode during startup of the switched capacitor voltage converter as suggested by Chen et al to ensure the capacitors of the switched capacitor converter are pre-charged to the desired voltage level needed by steady state operation during startup process.
Regarding claim 13, Arno discloses the claimed invention except for wherein the first phase is to operate in the switching mode during startup of the switched capacitor voltage converter, and wherein the first phase is to remain in the switching mode when the second phase is in the switching mode.
Chen et al [e.g., Fig. 11] teaches wherein the first phase is to operate in the switching mode during startup of the switched capacitor voltage converter [e.g., VSU 12 operates while capacitor 98 and switch 100 connected to intermediate bus during startup and transient process, p.0074 recites “One solution is to add a capacitor 98 connected in series with a switch 100 on the intermediate bus between the VSU 12 and the CSU 14, as illustrated in FIG. 11. This capacitor 98 is connected to the intermediate bus during the startup and transient process and is disconnected from the intermediate bus during steady state operation. As a result, in steady state, the CSU 14 operate as a current source and soft-charge the capacitors in the VSU 12.”], and wherein the first phase is to remain in the switching mode when the second phase is in the switching mode [e.g., VSU 12 remain operational during steady state while switch 100 opens and disconnected capacitor 98].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein the first phase is to operate in the switching mode during startup of the switched capacitor voltage converter, and wherein the first phase is to remain in the switching mode when the second phase is in the switching mode as suggested by Chen to ensure the capacitors of the VSUs are pre-charged to the desired voltage level needed by steady state operation and transition when converter is at the desired state.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Arno (US Pub. No. 2014/0070787 A1) in view of Chen et al (US Pub. No. 2022/0166314 A1) and Yanagida et al (US Pub. No. 2007/0279021 A1); (hereinafter Arno, Chen et al and Yanagida et al).
Regarding claim 12, Arno discloses the claimed invention except for wherein the second phase is to transition from the decoupling mode to the switching mode based on a voltage across the first capacitor.
Yanagida et al [e.g., Fig. 7] teaches wherein the second phase is to transition from the decoupling mode to the switching mode based on a voltage across the first capacitor [e.g., controller CNT control switches of charge pumps CP1 – CP3 to charge first capacitor during start-up, p. 0094 recites “Next a description will be given of a case where the output logic levels of the first and second detectors DET1 and DET2 are both low. In this case, in view of the output logic level of the second detector DET2, the controller CNT recognizes that the charge pump circuit is still in the process of start-up and therefore that there is a risk of in-rush current. Moreover, in view of the output logic level of the first detector DET1, the controller CNT recognizes that the charge level of the battery 1 (i.e., the level of the input voltage Vin) is low and therefore that there is little risk of a large in-rush current flowing in. Accordingly, based on the above recognition, the controller CNT so operates as to increase to a sufficiently but not unduly high level the on-state resistance of the current path for the charging of the first capacitor C1; to achieve that, the controller CNT produces the control signals CK1B1-3 such that, of the transistors P1 to P3, only the transistor P2--the one having the second smallest W/L ratio (i.e., the second highest on-state resistance)--is driven while the other transistors P1 and P3 are left undriven (kept off). In this operation state, the negative voltage generation circuit 21 can reduce in-rush current at start-up without causing a shortage in the output voltage Vout or a loss in efficiency even when the battery is battery is almost depleted.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein the second phase is to transition from the decoupling mode to the switching mode based on a voltage across the first capacitor as suggested by Yanagida et a to reduce in-rush current at start-up without causing a shortage in the output voltage Vout or a loss in efficiency.
Claim(s) 16, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Arno (US Pub. No. 2014/0070787 A1) in view of Szczeszynksi (US Patent No. 12,155,301 B2); (hereinafter Arno and Szczeszynksi)
Regarding claim 16, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses a power supply interface to receive a first power supply [e.g., -- refer to Fig. 7 --, input terminal 54 connected in parallel to capacitor modules 5(i)]; a circuit block to receive a second power supply that is less than the first power supply [e.g., voltage VLX received by switching half-bridge circuit with low pass filter 51 on node N1]; and a power conversion circuit to generate the second power supply based on the first power supply [e.g., PWM module 56 converting Vbat to intermediate voltage VLX], wherein the power conversion circuit includes: a voltage converter that includes an input terminal to receive an input voltage that corresponds to the first power supply [e.g., PWM module receiving Vbat via input terminal 54], and to generate an output voltage [e.g., intermediate voltage VLX], at an output terminal [e.g., node N1], that corresponds to the second power supply [e.g., second power supply different than Vbat], wherein the voltage converter includes a plurality of phases coupled between the input terminal and the output terminal [e.g., PWM module 56 containing plurality of capacitor modules 5(i) in parallel], and wherein the plurality of phases include: a first phase that includes a first capacitor and a first set of switches [e.g., top capacitor module 5(i) with corresponding capacitor 7(i) and switches], wherein the first phase is to operate in a switching mode in which the first set of switches alternately switch the first capacitor between a first state [e.g., -- refer to Fig. 12B --, top capacitor module 5(i) conducting to node N1], in which the first capacitor is coupled between the input terminal and the output terminal [e.g., capacitor 7(3) coupled between input terminal 54 and output terminal 52], and a second state [e.g., -- refer to Fig. 11A --, top capacitor module 5(i) conducting to node N1 while rest of phases are conducting to ground], in which the first capacitor is coupled between the output terminal and a ground terminal [e.g., capacitor 7(3) coupled to output terminal 52 and ground via capacitor modules containing capacitors 7(2) and 7(1)]; and a second phase that includes a second capacitor and a second set of switches [e.g., second capacitor module 5(j) containing capacitor 7(2) with corresponding switches], wherein the second phase is selectively operable in the switching mode or in a decoupling mode [e.g., refer to both Figs 11A and 12B for operation], and wherein the second set of switches maintain the second capacitor in the second state while the second phase is in the decoupling mode [e.g., -- refer to Fig. 11A --, second capacitor module capacitor 7(2) conducting to ground via capacitor 7(1)].
Arno does not disclose an integrated circuit.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with an integrated circuit as discloses by Szczeszynksi since it’s commonly understood and well known in the art to contain the components of similar converters within an integrated circuit [e.g., co. 4 lines 51 – 59 recites “The voltage ripple across the inductor L and the voltage swing across any one switch can be reduced by adding more series switches and charge transfer capacitors as energy storage elements to transfer charge from VIN to VOUT. Charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be internal components of an integrated circuit embodiment of a converter circuit or external components coupled to an integrated circuit embodiment of the remaining converter circuitry.”].
Regarding claim 19, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein the second set of switches includes: a first switch coupled between the input of the voltage converter and a first terminal of the second capacitor [e.g., SW1 coupled between Vbat and top terminal capacitor 7(2)]; a second switch coupled between the output of the voltage converter and a second terminal of the second capacitor [e.g., SW2 coupled between node N1 and bottom terminal of capacitor 7(2)]; a third switch coupled between the output of the voltage converter and the first terminal of the second capacitor [e.g., SW3 coupled between node N1 and top terminal of capacitor 7(2)]; and a fourth switch coupled between the second terminal of the second capacitor and a ground terminal [e.g., SW4 coupled between bottom terminal of capacitor 7(2) and ground].
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Regarding claim 20, Arno [e.g., Figs. 7, 11A, 12B and 14] discloses wherein: when the second phase is in the switching mode [e.g., -- refer to Fig. 12B --], the first and second switches are responsive to a first control signal [e.g., SW1 and SW2 responsive to a first control signal to close] and the third and fourth switches are responsive to a second control signal [e.g., SW3 and SW4 responsive to a second control signal to open]; and when the second phase is in the decoupling mode [e.g., -- refer to Fig. 11A --], the first and second switches are maintained in an open state [e.g., SW1 and SW2 maintained in an open state] and the third and fourth switches are maintained in a closed state [e.g., SW3 and SW4 maintained in a closed state].
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Arno (US Pub. No. 2014/0070787 A1) in view of Szczeszynksi (US Patent No. 12,155,301 B2) and Chen et al (US Pub. No. 2022/0166314 A1); (hereinafter Arno, Szczeszynksi and Chen et al).
Regarding claim 17, Arno discloses the claimed invention except for wherein, during startup of the voltage converter, the first phase is to operate in the switching mode and the second phase is to operate in the decoupling mode.
Chen et al [e.g., Fig. 11] teaches wherein, during startup of the voltage converter, the first phase is to operate in the switching mode and the second phase is to operate in the decoupling mode [e.g., operates capacitor 98 with switch 100 during startup, p. 0074 recites “To achieve the maximum efficiency and power density, the VSU and the CSU should be directly connected as one submodule without a filter capacitor in between to hold the intermediate voltage bus. However, a small capacitance is needed during the startup process to ensure the capacitors of the VSUs are pre-charged to the desired voltage level needed by steady state operation. One solution is to add a capacitor 98 connected in series with a switch 100 on the intermediate bus between the VSU 12 and the CSU 14, as illustrated in FIG. 11. This capacitor 98 is connected to the intermediate bus during the startup and transient process and is disconnected from the intermediate bus during steady state operation. As a result, in steady state, the CSU 14 operate as a current source and soft-charge the capacitors in the VSU 12.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein, during startup of the voltage converter, the first phase is to operate in the switching mode and the second phase is to operate in the decoupling mode as suggested by Chen et al to ensure the capacitors of the switched capacitor converter are pre-charged to the desired voltage level needed by steady state operation during startup process.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Arno (US Pub. No. 2014/0070787 A1) in view of Szczeszynksi (US Patent No. 12,155,301 B2) and Yanagida et al (US Pub. No. 2007/0279021 A1); (hereinafter Arno, Szczeszynksi and Yanagida et al).
Regarding claim 18, Arno discloses the claimed invention except for wherein the second phase is to transition from the decoupling mode to the switching mode based on a voltage across the first capacitor.
Yanagida et al [e.g., Fig. 7] teaches wherein the second phase is to transition from the decoupling mode to the switching mode based on a voltage across the first capacitor [e.g., controller CNT control switches of charge pumps CP1 – CP3 to charge first capacitor during start-up, p. 0094 recites “Next a description will be given of a case where the output logic levels of the first and second detectors DET1 and DET2 are both low. In this case, in view of the output logic level of the second detector DET2, the controller CNT recognizes that the charge pump circuit is still in the process of start-up and therefore that there is a risk of in-rush current. Moreover, in view of the output logic level of the first detector DET1, the controller CNT recognizes that the charge level of the battery 1 (i.e., the level of the input voltage Vin) is low and therefore that there is little risk of a large in-rush current flowing in. Accordingly, based on the above recognition, the controller CNT so operates as to increase to a sufficiently but not unduly high level the on-state resistance of the current path for the charging of the first capacitor C1; to achieve that, the controller CNT produces the control signals CK1B1-3 such that, of the transistors P1 to P3, only the transistor P2--the one having the second smallest W/L ratio (i.e., the second highest on-state resistance)--is driven while the other transistors P1 and P3 are left undriven (kept off). In this operation state, the negative voltage generation circuit 21 can reduce in-rush current at start-up without causing a shortage in the output voltage Vout or a loss in efficiency even when the battery is battery is almost depleted.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Arno with wherein the second phase is to transition from the decoupling mode to the switching mode based on a voltage across the first capacitor as suggested by Yanagida et a to reduce in-rush current at start-up without causing a shortage in the output Vout or a loss in efficiency.
Examiner’s Note
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2015/0180355 A1 (Freeman et al) discloses a switch capacitor voltage breakdown circuit shown in FIG. 4.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/FRED E FINCH III/Primary Examiner, Art Unit 2838
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