Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species A, Subspecies I, claims 1-10, in the reply filed on January 16, 2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 are rejected under 35 U.S.C. 103 as being obvious in view of Kim et al. (US 20200098310 A1) with respect to Orobtchouk et al. (Towards Optical Networks-on-Chip Using CMOS Compatible III-V/SOI Technology).
Regarding Claim 1, Kim et al. discloses a semiconductor device comprising:
A substrate (SUB, [0045]) including an active pattern (active pattern ACT1 [0141]);
A channel pattern (channel region [0144]) disposed on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns that are spaced apart from each other and are vertically stacked on each other;
A first source/drain pattern (drain electrode DE1, source electrode SE1) and a second source/drain pattern (drain electrode DE2, source electrode SE2) that are connected to the plurality of semiconductor patterns, wherein the first source/drain pattern is disposed on an NMOSFET region of a first active region (ACT1) and the second source/drain pattern is disposed on a PMOSFET region of a second active region (ACT2),
A gate electrode (gate electrode GE1-7) disposed on the plurality of semiconductor patterns, wherein the gate electrode includes inner electrodes disposed between neighboring semiconductor patterns of the of the plurality of semiconductor patterns and an outer electrode disposed on an uppermost semiconductor pattern; and a first active contact electrically connected to the first source/drain pattern and a second active contact electrically connected to the second source/drain pattern.
Kim et al. discloses a first recess depth but does not disclose a first recess depth of the first active contact which is about 1.2 times to about 2.5 times as deep as a second recess depth of the second active contact. However, Orobtchouk discloses ohmic contacts on both n-InP and p-InGaAs obtained without any annealing performed on the wafers (Fig. 2d).
It would have been obvious to one ordinarily skilled in the art before the effective filing date of the application to combine the disclosure of Kim along with Orobtchouk’s teaching regarding active contact design to select various recess depths as needed to optimize threshold voltage, drain current, and RF performance.
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Regarding Claim 2, Kim et al. discloses a first recess depth but does not explicitly disclose the recess depth ranges. However, it would be obvious to one ordinarily skilled in the art before the effective filing date of the application to design and select various recess depths as needed to optimize threshold voltage, drain current, and RF performance.
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Regarding Claim 3, Kim et al. discloses a second recess depth but does not explicitly disclose the recess depth ranges. However, it would be obvious to one ordinarily skilled in the art before the effective filing date of the application to design and select various recess depths as needed to optimize threshold voltage, drain current, and RF performance.
Regarding Claim 4, Kim et al. discloses a first active contact (contact hole CH1) includes a first conductive pattern (transparent conductive layer) and a first barrier pattern (gate insulating layer GI) that surrounds the first conductive pattern, wherein the first barrier pattern covers sidewalls and a bottom surface of the first conductive pattern (FIG. 4).
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Regarding Claim 5, Kim et al. discloses a first conductive pattern (conductive and reflective layer [0190-0191] which includes aluminum wherein the first barrier pattern (encapsulation layer SLM) includes a metal layer and a metal nitride layer [0201].
[0191] “For example, the reflective layer may include at least one selected from the group consisting of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and alloys thereof. The inorganic layer may include at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.
Regarding Claim 6, Kim et al. discloses a metal layer (second electrode CD [0197]) which includes “molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.” The inorganic layer may include at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.
Regarding Claim 7, Kim et al. discloses a second active contact which includes a second conductive pattern (second electrode CD [0197]) and a second barrier pattern (inorganic layer, [0201]) that surrounds the second conductive pattern, and wherein the second barrier pattern covers sidewalls and a bottom surface of the second conductive pattern.
Regarding Claim 8, Kim et al. discloses a second conductive pattern (second electrode CD [0197]) which includes aluminum wherein the second barrier pattern includes a metal layer and a metal nitride layer (inorganic layer, [0201]).
Regarding Claim 9, Kim et al. discloses a semiconductor device wherein the metal layer includes a metal layer (second electrode CD [0197]) which includes “molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.” The metal nitride layer (inorganic layer) may include at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.
Regarding Claim 10, Kim et al. discloses a semiconductor device further comprising:
A gate contact (double gate structure, [0218]) electrically connected to the outer electrode (“first electrode connected to the transistor; a pixel defining layer exposing the first electrode; a light emitting layer provided on the first electrode; and a second electrode provided on the light emitting layer”), wherein the second active contact adjacent to the gate contact includes:
A second conductive pattern;
A second barrier pattern ([0250] “an encapsulation layer SLM may be provided on the second dummy electrode DCD”) that covers sidewalls and a bottom surface of the second conductive pattern (FIG. 16);
An upper dielectric pattern (“third interlayer insulating layer IL3”) disposed on the second conductive pattern and the second barrier pattern.
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Conclusion
Any inquiry concerning this communication should be directed to JOSHUA SCOTT WYATT at telephone number (703)756-1937.
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/JOSHUA SCOTT WYATT/Examiner, Art Unit 2815
/JAY C KIM/Primary Examiner, Art Unit 2815