Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Finality of the action
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to Argument
Applicant's arguments filed on 12/18/2025 have been fully considered but they are not persuasive. Applicant pointed out that the matching circuit 317 is selectively connected through the switch 306 to the filter 311 not directly connected. Examiner agrees that the connection selective not direct. But the claim doesn’t require a direct connection to the second terminal of the switch. If it requires a direct connection then examiner agrees that the claim overcomes Frenette, but just as claimed “connected between”, the selective or switched connection can fulfil the claim requirement.
Since no substantial amendment is done to the claims, accordingly examiner considers the rejection as valid.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 7-8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Frenette et al., (US 2025/0159786 Al, effectively filed on December 2017 before the effective filing date of the current invention i.e., December 2020).
PNG
media_image1.png
276
520
media_image1.png
Greyscale
Fig. 32B of reproduced for ease of reference.
Regarding claims 1 and 11, Frenette discloses (in Fig. 1) a communication device (an IoT-enabled watch, as shown in Fig. 32A) in which there is a radio frequency module (Front end system 301 of Fig. 32B, §0605), comprising:
a first power amplifier (307) configured to amplify a first signal (B26 TX IN) and to output a first amplified signal (at the output of the first amplifier 307);
a second power amplifier (308) configured to amplify a second signal (B12 TX IN) with
a filter (311) configured to pass the first amplified signal (AB26) and the second amplified signal (AB12);
a switch (306) having a first terminal connected to an output of the first power amplifier (307) and a second terminal connected to the filter (311), and configured to change connection and disconnection of the first terminal (between one of the three possible paths see Fig. 32B of Frenette above) and the second terminal; and
a matching circuit (317) connected between an output of the second power amplifier (308) and a first signal path (designated by the examiner on the annotated Fig. 32B of Frenette), the signal path being (partly being) between the second terminal of the switch and the filter (311).
Frenette however is not explicit about the second path has a lower gain than the first path. In Fig. 61A, Frenette shows 3 different gains for three different paths (1451, 1452 and 1453 where G1451<G1452<G1453). It is, therefore, evident that the gains are different in different path.
So, a person of ordinary skill in the art would find it as an obvious design iteration to set the gains of different paths at different levels as needed and an obvious iteration could specify the second path gain as smaller than the first path gain. Which doesn’t necessarily be an innovative feature rather it would be a design choice and will be well within the purview of a person of ordinary skill in the art. Hence Frenette in an obvious design iteration would teach all limitations of claim 1.
wherein per claim 2, the matching1 circuit (both amplifiers have input, interstage and output matching circuits, §0243, §0780 as well as a band selection filter 317 to cover a very narrow band of 699-716 MHz, please refer to IoT bands attached here as a teaching reference) comprises a plurality of stages (more than one stages because there is a output matching as well as a band selection filter 317 which is essentially acting as part of the output match of the second amplifier) configured to process the second amplified signal (AB12) of the second power amplifier (308) and to output a processed signal (AB12), and a high pass filter (§1137) in a final stage of the plurality of stages (§1137).
wherein per claims 3 and 4, wherein the matching circuit further comprises:
a capacitor connected in series (since the output matching has a high pass stage it is well known in the art that a high pass match consists of a series capacitor and a shunt inductor) with the second power amplifier in a second signal path, the second signal path being different from the first signal path and being between the output of the second power amplifier and the second terminal of the switch; and
an inductor (a high pass match consists of a series capacitor and a shunt inductor, i.e., inductor to ground) connected between the second signal path and ground.
Further per claim 7, a bias current of the second power amplifier is zero in a disconnection state of the switch (§0583).
wherein per claim 8, wherein a cutoff frequency of the high pass filter is lower than a frequency of the second amplified signal outputted from the second power amplifier (it is evident that the band pass filter for the B12 TXIN band of the second amplifier is formed using a low pass filter and high pass filter where the low pass filter will decide the high end of the band while the high pass filter would set the low end of the band. Therefore, it would have been obvious to a person of ordinary skill to set the cutoff frequency of the high pass filter at a frequency lower than a frequency of the second amplified signal outputted from the second power amplifier.
wherein per claim 10, further comprising:
a third power amplifier (the second one of the two different frequency bands of 307 operation with two different input output switch combinations) configured to amplify a third signal (B13 TX IN) with an amplification factor smaller than (with the obviousness argument as discussed as claim 1 gain difference between first and second path) the amplification factor of the first power amplifier (the first one of the two different frequency bands of 307 operation with two different input output switch combinations), and to output a third amplified signal (AB13);
a second filter (306 with top two switching positions) configured to pass the first amplified signal (AB26) and the third amplified signal (AB13); and
a second matching circuit (316), wherein the switch further comprises a third terminal (T) connected to the second filter (306) and is further configured to change connection and disconnection of the first terminal (first amplified signal AB26) and the third terminal (third amplifier signal AB13), and
wherein the second matching circuit (316) is connected between an output of the third power amplifier (307 in its second configuration) and a signal path between the third terminal of the switch (306) and the second filter.
Allowable Subject Matter
Claims 5-6, 9 are objected to as being dependent upon a rejected base claim 1 but would be allowable if rewritten in independent form including all of the limitations of the base claim 1 and any intervening claims.
Claims 5-6 are allowable because the closest prior art of record, Frenette is not explicit about a phase angle representing the reflection coefficient in polar coordinates has a value of -45 degrees or more and +45 degrees or less or the real part of the reflection coefficient has a value of 0.7 or more and 1 or less as claimed.
Claim 9 is allowable because the closest prior art of record, contrary to the claim teaches that the switch is in a signal path between the output of the second power.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 FIG. 101F illustrates an example circuit board layout 3480 with example bonding configurations and example stacking configurations that reduce the form factor of the circuitry. In FIG. 101F, components L2, C2, C3 are stacked to form a first surface mount stacking assembly 3490, components L4, C6, C7 have been stacked to form a second surface mount stacking assembly 3490, and components L5, C8, C9 have been stacked to form a third surface mount stacking assembly 3490. Components C2, C3, C6, C7, C8, and C9 are capacitors. Components L2, L4, and L5 are inductors. In an embodiment, the surface mount stacking assembly 3490 is configured as the surface mount stacking assembly 3440 and the components are electrically connected as illustrated in circuit 3445. In some embodiments, the surface mount stacking assemblies 3490 include high-pass filters, low-pass filters, band pass filters, at least a portion of an output matching network, the like, or any suitable combination thereof.