DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 8, 9, 11, 15, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2023/0306180 to Sripada et al. (“Sripada”) in view of US Pub. No. 2003/0172361 to Chiu et al. (“Chiu”).
As to independent claim 8 and similarly recited independent claims 1 and 15, a system/method/CRM (¶ 0001, Fig. 8) comprising: a memory (Fig. 8: 804); and a processor communicatively coupled to the memory (Fig. 8: 804, 830, 802), wherein the processor is configured to: (¶ 0032, 0034, 0035, 0042. Sripada teaches performing timing analysis on a circuit design representation and producing timing results that include a slack value for a timing path or timing node.); calculate a credit based on the slack value (¶ 0036, 0054, 0055-0058. Sripada teaches calculating a timing credit from timing analysis slack values by determing the difference between a worst-case slack and an aggregate slack.); and update the slack value based on the credit (¶ 0043, 0059. Sripada teaches updating a slack value based on a calculated timing credit by adding the credit, or a fraction of the credit, to the slack value.).
Sripada does not explicitly teach assigning a timing margin to a non-scan latch of a circuit design or performing the timing analysis “using the timing margin for the non-scan latch”.
Sripada’s disclosed timing credit concerns pessimism introduced by combining timing values for multiple process, voltage, temperature, parasitic, and die-corner combinations. Sripada does not specifically assign a timing margin to a non-scan latch before performing the timing analysis.
Chiu teaches the missing latch specific timing margin limitations. Chiu’s timing analysis method is applicable when the flip-flops are replaced by other types of sequential logic gates such as latches and expressly states that active-high or active-low latches can be used too (¶ 0030).
Figure 7 and ¶ 0038 disclose latch device 704 as an active-high latch receiving data from combinational logic circuit 106 and a functional clock signal produced from destination clock signals. Chiu does not disclose latch 704 as a scan latch, provide it with scan-in or scan-out connections, or place it in a scan chain. Rather, the latch is used as the ordinary functional destination sequential element of the analyzed circuit.
Furthermore, Chiu teaches determining and assigning a latch specific timing margin based on the operating characteristics and clock edges of an active-high or active-low functional latch (¶ 0031, 0038).
Chiu also teaches performing static timing analysis of a circuit containing a functional latch using the source and destination clock relationship that defines the selected latch timing margin (¶ 0012, 0026, 0032, 0038).
It would have been obvious to a PHOSITA to modify Sripada’s timing analysis system to perform timing analysis for a non-scan latch using the latch specific timing margin technique taught by Chiu. A PHOSITA would have recognized Chiu’s technique produces timing results to which Sripada’s slack-credit correction can predictably be applied to provide more accurate, less pessimistic timing results for latch-based timing paths, consistent with the stated objectives of both references.
As to claim 9 and similarly recited claim 2 and 16, the system of claim 8, wherein updating the slack value comprises adding the credit to the slack value (Sripada: ¶ 0054, 0059. Sripada identifies its timing adjustment value as a timing credit value and teaches the timing adjustment value is added to slack values to reduce timing pessimism.).
As to claim 11 and similarly recited claims 4 and 18, the system of claim 8, wherein calculating the credit comprises limiting the credit based on one or more of a maximum, a minimum, or a cutoff (¶ 0052, 0054-0056. Sripada teaches calculating credit from slack values that were determined using maxima and minima.).
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sripada in view of Chiu and in further view of US Pub. No. 2021/0073456 to Nath et. al. (“Nath”).
The combination of Sripada and Chiu does teach the limitations of claims 1 and 8 from which claims 7 and 14 depend. The combination, however, does not teach the limitation of claims 7 or 14.
Nath teaches adjusting critical path slack and then uses the adjusted timing value to perform circuit design optimization, including selecting the type and extent of modifications to current circuit design (¶ 0009, 0046, 0048, 0050-0056).
It would have been obvious to a PHOSITA to further configure the system of Sripada, as modified by Chiu, to adjust the circuit design based on the updated slack value, as taught by Nath, in order to improve timing closure or avoid tapeout modifications/ECO changes.
Allowable Subject Matter
Claims 3, 5, 6, 10, 12, 13, 17, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3, 5, 6, 10, 12, 13, 17, 19, and 20 would be allowable if amended in the manner above because the prior art of record does not teach or suggest all the steps or elements recited in and required by claims 3, 5, 6, 10, 12, 13, 17, 19, or 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SURESH MEMULA/Primary Examiner, Art Unit 2851
Prosecution Insights