Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION 2 . This Office Action responds to the Application filed on 5/19/2023. Claims 1-20 are pending. Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. 4. Claim(s) 1, 9, 16-18, and 20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ruehl (U.S. Pat. No. 7,409,656 B1) . As per claim 1, Ruehl discloses: A method of performing a design rule check, comprising: clustering at least one of a plurality of rules with overlapping operations from a plurality of operations or the plurality of operations with overlapping rules from the plurality of rules into a clustered plurality of rules or a clustered plurality of operations (See Col 3; Lines 4-65, subgraph A exists which overlaps a second subgraph B at operation 460…duplicates some or all of the overlapping operations between sequences of operations, See Col 3; Line 66 to Col 5; Line 40, See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s , See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel [ prior art determine overlapping operations, group of the operations into group which is based overlapping operations is considered as the clustering of the plurality of operations as cited above , the operation are for design rule checking, therefore directed to rules ( See Col 9; Line 12 to Col 11; Line 21 ) ] ) ; at least one of transforming at least one of the clustered plurality of operations into a first operation group or a second operation group, or transforming at least one of the clustered plurality of rules into a first rule group or a second rule group (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 5; Line 48 to Col 9; Line 10) ; at least one of assigning at least one of the first operation group to a first processor or the second operation group to a second processor, or assigning at least one of the first rule group to the first processor or the second rule group to the second processor (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 5; Line 48 to Col 9; Line 10) ; and parallel processing, via the first and second processors, at least one of the first operation group and the second operation group, or the first rule group and the second rule group, to determine whether an error exists within an electronic architectural design ( See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel [ prior art directed to design rule check of design in parallel, therefore determine whether an error exists ] ). As per claim 9, Ruehl discloses: An electronic design automation (EDA) system, comprising: a first processor; a second processor; and a machine-readable medium including a clustering verification application, the clustering verification application configured (See Figure 11 & See Col 5; Lines 40-47, i.e. different CPU s) to: cluster at least one of a plurality of rules with overlapping operations from a plurality of operations or the plurality of operations with overlapping rules from the plurality of rules into a clustered plurality of rules or a clustered plurality of operations (See Col 3; Lines 4-65, subgraph A exists which overlaps a second subgraph B at operation 460…duplicates some or all of the overlapping operations between sequences of operations, See Col 3; Line 66 to Col 5; Line 40, See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel [ prior art determine overlapping operations, group of the operations into group which is based overlapping operations is considered as the clustering of the plurality of operations as cited above , the operation are for design rule checking, therefore directed to rules ( See Col 9; Line 12 to Col 11; Line 21)]) ; at least one of transform at least one of the clustered plurality of operations into a first operation group or a second operation group, or transform at least one the clustered plurality of rules into a first rule group or a second rule group (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 5; Line 48 to Col 9; Line 10) ; at least one of assign at least one of the first operation group to a first processor or the second operation group to a second processor, or assign at least one of the first rule group to the first processor or the second rule group to the second processor (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 5; Line 48 to Col 9; Line 10) ; and parallel process, via the first and second processors, at least one of the first operation group and the second operation group, or the first rule group and the second rule group, to determine whether an error exists within an electronic architectural design (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel [ prior art directed to design rule check of design in parallel, therefore determine whether an error exists ]). As per claim 16, Ruehl discloses: A non-transitory machine-readable medium having instructions stored thereon that, when executed by a computer, cause the computer to (See Figure 11) : cluster at least one of a plurality of rules with overlapping operations from a plurality of operations or the plurality of operations with overlapping rules from the plurality of rules into a clustered plurality of rules or a clustered plurality of operations (See Col 3; Lines 4-65, subgraph A exists which overlaps a second subgraph B at operation 460…duplicates some or all of the overlapping operations between sequences of operations, See Col 3; Line 66 to Col 5; Line 40, See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel [ prior art determine overlapping operations, group of the operations into group which is based overlapping operations is considered as the clustering of the plurality of operations as cited above , the operation are for design rule checking, therefore directed to rules ( See Col 9; Line 12 to Col 11; Line 21)]) ; at least one of transform at least one of the clustered plurality of operations into a first operation group or a second operation group, or transform at least one the clustered plurality of rules into a first rule group or a second rule group (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 5; Line 48 to Col 9; Line 10) ; and at least one of assign at least one of the first operation group to a first processor or the second operation group to a second processor, or assign at least one of the first rule group to the first processor or the second rule group to the second processor, to parallel process, via the first and second processors (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 5; Line 48 to Col 9; Line 10) , at least one of the first operation group and the second operation group, or the first rule group and the second rule group, to determine whether an error exists within an electronic architectural design (See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel [ prior art directed to design rule check of design in parallel, therefore determine whether an error exists ]). As per claim 17, Ruehl discloses all of the feature s of claim 16 as discloses above wherein Ruehl also discloses implement a first iteration to form at least a first cluster of operations and a second cluster of operations (See Col 3; Lines 4-65, subgraph A exists which overlaps a second subgraph B at operation 460…duplicates some or all of the overlapping operations between sequences of operations, See Col 3; Line 66 to Col 5; Line 40, See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel ) and exclude one operation if one of the clusters violates a threshold and perform the clustering again for remaining operations (See Col 4; Lines 31-44, i.e. Different applications for the invention can have different thresholds for determining which nodes can be duplicated ). As per claim 18, Ruehl discloses all of the features of claim 17 as discloses above wherein Ruehl also discloses implement a third iteration and do the clustering after excluding an extra operation from the remaining operation of iteration (See Col 3; Lines 4-65, subgraph A exists which overlaps a second subgraph B at operation 460…duplicates some or all of the overlapping operations between sequences of operations, See Col 3; Line 66 to Col 5; Line 40, See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel ). As per claim 20, Ruehl discloses all of the feature s of claim 17 as discloses above wherein Ruehl also discloses stop the iterations when none of the clusters violates the threshold (See Col 3; Lines 4-65, subgraph A exists which overlaps a second subgraph B at operation 460…duplicates some or all of the overlapping operations between sequences of operations, See Col 3; Line 66 to Col 5; Line 40, See Col 5; Lines 40-47, i.e. On output, the process has defined groups, and can assign group memberships to each node of the graph. These groups form execution tasks that can be freely mapped to different CPU s, See Col 9; Line 12 to Col 11; Line 21, i.e. o nce a rule deck is translated into a linear list of atomic operations, a dependency graph can be built, as shown in FIG. 1. The processes of FIGS. 5 and 7 can be used to identify independent sequences of rules operations that can be processed in parallel –[ prior art group based on threshold of execution time, into different group, in iteration loop (See Figure 7), end when all node considered I considered as the stop of the iterations ])). Claim Rejections - 35 USC § 103 5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 6. Claim (s) 2, 3, and 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ruehl (U.S. Pat. No. 7,409,656 B1) in view of Grudavnov et al. (U.S. Pub. No. 2023/0334216 A1). As per claim 2, Ruehl discloses all of the feature s of claim 1 as discloses above . Ruehl does not teach the limitations: wherein the electronic architectural design includes an antenna, and an error mitigation that includes adding an antenna diode to the antenna to discharge a node of the antenna. However, Grudavnov teach the limitations: wherein the electronic architectural design includes an antenna, and an error mitigation that includes adding an antenna diode to the antenna to discharge a node of the antenna (See Para [0036], i.e. Antenna check test for antenna effect violations … a ntenna errors may be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again ). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Grudavnov into the teaching of Ruehl because it would allow for using of metadata matrix minimize volume of information and resources needed for generating fillers for integrated circuit masks (See Para [0036] -[ 0037]). As per claim 3, Ruehl discloses all of the feature s of claim 1 as discloses above . Ruehl does not teach the limitations: wherein the electronic architectural design includes an antenna, and an error mitigation that includes splitting the antenna by routing the antenna to a second metal layer of the electronic architectural design and then to a first metal layer. However, Grudavnov teach the limitations: wherein the electronic architectural design includes an antenna, and an error mitigation that includes splitting the antenna by routing the antenna to a second metal layer of the electronic architectural design and then to a first metal layer. (See Para [0036], i.e. Antenna check test for antenna effect violations … a ntenna errors may be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again ). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Grudavnov into the teaching of Ruehl because it would allow for using of metadata matrix minimize volume of information and resources needed for generating fillers for integrated circuit masks (See Para [0036] -[ 0037]). As per claim 10, Ruehl discloses all of the features of claim 9 as discloses above. Ruehl does not teach the limitations: wherein the machine-readable medium further includes a correct errors application configured to modify the electronic architectural design to mitigate the error within the electronic architectural design. However, Grudavnov teach the limitations: wherein the machine-readable medium further includes a correct errors application configured to modify the electronic architectural design to mitigate the error within the electronic architectural design. (See Para [0036], i.e. Antenna check test for antenna effect violations… antenna errors may be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Grudavnov into the teaching of Ruehl because it would allow for using of metadata matrix minimize volume of information and resources needed for generating fillers for integrated circuit masks (See Para [0036] -[ 0037]). As per claim 1 1 , Ruehl and Grudavnov discloses all of the feature s of claim 10 as discloses above wherein Grudavnov also discloses wherein the EDA system provides the modified electronic architectural design to an integrated circuit (IC) manufacturing system to manufacture an integrated circuit using the modified electronic architectural design (See Para [0033], i.e. fabricating the verified circuit design , See Para [0041], i.e. f abricate an IC having the IC layout using a metadata matrix ). As per claim 1 2 , Ruehl and Grudavnov discloses all of the feature s of claim 10 as discloses above wherein Grudavnov also discloses wherein the electronic architectural design includes an antenna, the error mitigation including adding an antenna diode to the antenna to discharge a node of the antenna (See Para [0036], i.e. Antenna check test for antenna effect violations… antenna errors may be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again). As per claim 1 3 , Ruehl and Grudavnov discloses all of the feature s of claim 10 as discloses above wherein Grudavnov also discloses wherein the electronic architectural design includes an antenna, the error mitigation including splitting the antenna by routing the antenna to a second metal layer of the electronic architectural design and then down to a first metal layer (See Para [0036], i.e. Antenna check test for antenna effect violations… antenna errors may be cured by adding a small antenna diode to safely discharge the node or splitting the antenna by routing up to another metal layer and then down again). Allowable Subject Matter 7. Claims 4-8, 14, 15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 8. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claims 4, 14, and 19 – wherein claims 5-8 depend on claim 4, wherein claim 15 depend on claim 14. Conclusion 9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NHA T NGUYEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1405 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8:00AM-5:00PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NHA T NGUYEN/ Primary Examiner, Art Unit 2851