DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to U.S. Patent Application No. 18/320,578 filed on 05/19/2023 in which Claims 1 – 20 were presented for examination.
Status of the Claims
Claims 1 – 5, 7, 8, 10 – 14, 16, 17, 19 and 20 are rejected under 35 U.S.C. 103.
Examiner Note
The Examiner cites particular columns, line numbers and/or paragraph numbers in the references as applied to the claims below for the convenience of the Applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 7, 8, 10 – 14, 16, 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Burns (US 2023/0032488) (hereinafter, Burns).
Regarding Claim 1, Burns teaches a computer-implemented method (See Burns’ Abstract) comprising:
receiving monitoring data representing operations of a data publisher, a data processing unit, and [a database] (Burns in par 0019, teaches that an event management bus (EMB) is a computer system that may be arranged to monitor, manage, or compare the operations of one or more organizations. Burns in par 0048, further teaches that an event management bus (which can also be referred to as an event ingestion and processing system) may be configured to monitor various types of events depending on needs of an industry and/or technology area. For example, information technology services may generate events in response to one or more conditions, such as, computers going offline, memory overutilization, CPU overutilization, storage quotas being met or exceeded, applications failing or otherwise becoming unavailable, networking problems (e.g., latency, excess traffic, unexpected lack of traffic, intrusion attempts, or the like), electrical problems (e.g., power outages, voltage fluctuations, or the like), customer service requests, or the like, or combination thereof. Burns in par 0127 and Fig. 4, further teaches that each of the PID controllers 412A and 412B monitors a pipeline (or a portion thereof) of the system 400, without being part of the pipeline, to determine whether to throttle the rate limit at which the ingestion engine 402 accepts events);
determining a first data processing error associated with the data publisher and the data processing unit based at least in part on the monitoring data (Burns in par 0035 and 0046, teaches that the PID controller monitors the pipeline of the EMB (or a portion thereof), without being part of the pipeline, to determine whether to throttle the target rate limit (i.e., whether to use a throttled rate limit instead of the target rate limit). The PID controller monitors how events flow through the pipeline. More specifically, the PID controller determines a throttled rate limit by monitoring (e.g., comparing, etc.) the lag times (i.e., measured lag times) of events (e.g., most recently processed events for a given routing key) as compared to the target lag time. As such, the PID controller may be configured to use, as an input, an error that is a difference between the average lag time and the target lag time, such as of most recently processed events);
determining a second data processing error associated with the data processing unit and [the database] based at least in part on the monitoring data (Burns in par 0127 – 0129, teaches that each of the PID controllers 412A and 412B monitors a pipeline (or a portion thereof) of the system 400, without being part of the pipeline, to determine whether to throttle the rate limit at which the ingestion engine 402 accepts events. A pipeline of the system 400 can be defined as the set of components (e.g., modules, tools, software, processing blocks, etc.) that perform different types of processing or monitoring on an accepted event in order to progress the processing of accepted event from one stage to a next stage until the accepted event is fully processed. A PID controller (e.g., the PID controllers 412A and 412B) monitors how events flow through the pipeline (or portions thereof) of the system 400 in order to determine whether the system 400 is performing according to the target lag time, how far behind the target lag time the system 400 is performing, and how quickly the system 400 is recovering toward performing according to the target lag time. A PID controller may be configured to use, as an input, an error that is a difference between the average measured lag time and the target lag time);
causing a first controller to control the data publisher or the data processing unit based at least in part on the first data processing error (Burns in par 0127 - 0129, teaches that each of the PID controllers 412A and 412B monitors a pipeline (or a portion thereof) of the system 400, without being part of the pipeline, to determine whether to throttle the rate limit at which the ingestion engine 402 accepts events. A PID controller (e.g., the PID controllers 412A and 412B) monitors how events flow through the pipeline (or portions thereof) of the system 400 in order to determine whether the system 400 is performing according to the target lag time, how far behind the target lag time the system 400 is performing, and how quickly the system 400 is recovering toward performing according to the target lag time. A PID controller may be configured to use, as an input, an error that is a difference between the average measured lag time and the target lag time); and
causing a second controller to control the data processing unit or [the database] based at least in part on the second data processing error (Burns in par 0127 - 0129, teaches that each of the PID controllers 412A and 412B monitors a pipeline (or a portion thereof) of the system 400, without being part of the pipeline, to determine whether to throttle the rate limit at which the ingestion engine 402 accepts events. A PID controller (e.g., the PID controllers 412A and 412B) monitors how events flow through the pipeline (or portions thereof) of the system 400 in order to determine whether the system 400 is performing according to the target lag time, how far behind the target lag time the system 400 is performing, and how quickly the system 400 is recovering toward performing according to the target lag time. A PID controller may be configured to use, as an input, an error that is a difference between the average measured lag time and the target lag time).
However, Burns does not specifically disclose the determination of a processing error between the processing unit and a database.
Burns in par 0048, teaches that an event management bus may be configured to monitor various types of events depending on needs of an industry and/or technology area. For example, information technology services may generate events in response to one or more conditions, such as, computers going offline, memory overutilization, CPU overutilization, storage quotas being met or exceeded, applications failing or otherwise becoming unavailable, networking problems (e.g., latency, excess traffic, unexpected lack of traffic, intrusion attempts, or the like), or the like, or combination thereof. Burns in par 0135, further teaches that each of the incoming events 508, the processed events 510, and the events throttles 512 may be or may be implemented using a data base, a data feed, an asynchronous communication channel, a messaging queue, some other mechanism, or a combination thereof.
Accordingly, Burns clearly disclose the monitoring of events, wherein event may be associated with information technology services such as memory overutilization, storage quotas being met or exceeded or networking problems.
Therefore, It would have been obvious before the effective filing data to utilize the teachings as in Burns to monitor performance of a database. The motivation for doing so would have been to provide real time management of information to implement a PID controller for event ingestion throttling (See Burns’ Abstract par 0001 and 0005).
Regarding Claim 2, Burns teaches the limitations contained in parent Claim 1. Burns further teaches:
wherein the first controller is a first proportional-integral-derivative (PID) controller and the second controller is a second PID controller (Burns in par 0127 - 0129, teaches that each of the PID controllers 412A and 412B monitors a pipeline (or a portion thereof) of the system 400, without being part of the pipeline, to determine whether to throttle the rate limit at which the ingestion engine 402 accepts events. A PID controller (e.g., the PID controllers 412A and 412B) monitors how events flow through the pipeline (or portions thereof) of the system 400 in order to determine whether the system 400 is performing according to the target lag time, how far behind the target lag time the system 400 is performing, and how quickly the system 400 is recovering toward performing according to the target lag time. A PID controller may be configured to use, as an input, an error that is a difference between the average measured lag time and the target lag time).
Regarding Claim 3, Burns teaches the limitations contained in parent Claim 1. Burns further teaches:
wherein the monitoring data comprises one or more of a publisher data flow rate, a data processing flow rate, a computing resource consumption amount, and a data storage rate (Burns in par 0048, further teaches that an event management bus (which can also be referred to as an event ingestion and processing system) may be configured to monitor various types of events depending on needs of an industry and/or technology area. For example, information technology services may generate events in response to one or more conditions, such as, computers going offline, memory overutilization, CPU overutilization, storage quotas being met or exceeded, applications failing or otherwise becoming unavailable, networking problems (e.g., latency, excess traffic, unexpected lack of traffic, intrusion attempts, or the like), electrical problems (e.g., power outages, voltage fluctuations, or the like), customer service requests, or the like, or combination thereof. Burns in par 0128, further teaches that PID controller (e.g., the PID controllers 412A and 412B) monitors how events flow through the pipeline (or portions thereof) of the system 400 in order to determine whether the system 400 is performing according to the target lag time, how far behind the target lag time the system 400 is performing, and how quickly the system 400 is recovering toward performing according to the target lag time).
Regarding Claim 4, Burns teaches the limitations contained in parent Claim 3. Burns further teaches:
wherein the data publisher is configured to transmit publisher data to the data processing unit at the publisher data flow rate (Burns in par 0019, teaches that an event management bus (EMB) is a computer system that may be arranged to monitor, manage, or compare the operations of one or more organizations. Burns in par 0023, further teaches that the EMB may include guardrails (e.g., targets, thresholds, etc.) to ensure that the performance of the EMB does not degrade. For example, the EMB may include a target rate limit that indicates a maximum number of events that may be accepted for processing (such as per minute). In some examples, the target rate limit may be set by organization, by routing key, or according to some other granularity),
wherein the data processing unit is configured to generate data processing data based at least in part on the publisher data (Burns in par 0021, teaches receiving an event by the EMB encompasses receiving data from a transmitter that the EMB uses to create an event. Burns n par 0035, teaches that the PID controller monitors the pipeline of the EMB (or a portion thereof), without being part of the pipeline, to determine whether to throttle the target rate limit (i.e., whether to use a throttled rate limit instead of the target rate limit). The PID controller monitors how events flow through the pipeline. More specifically, the PID controller determines a throttled rate limit by monitoring (e.g., comparing, etc.) the lag times (i.e., measured lag times) of events (e.g., most recently processed events for a given routing key) as compared to the target lag time),
wherein the data processing unit is configured to transmit the data processing data to the database at the data processing flow rate (burns in par 0046, teaches that if for example the target rate limit is 120 events per minute, that the target lag time (i.e., the set point) is 2 minutes, and that the average measured lag is 2.5 minutes. As such, the current error is −0.5 (i.e., target rate limit−average measured lag). As such, the EMB is not meeting the performance criterion and throttling is required. Assume further that first events of a first routing key, which are received at exactly the rate limit (i.e., 120 events per minute), each requires a minimal processing time. As such, the error cannot not be said to be attributable to the first routing key. On the other hand, second events of a second routing key are slow events and each requires at least 10 seconds to process. As such, the error is attributable to the second routing key. While, overall, throttling is required to bring the EMB performance to within the performance criterion, the throttling response of the PID controller can be tailored to (i.e., can be proportioned by, etc.) routing keys according to their contributions to the error).
Regarding Claim 5, Burns teaches the limitations contained in parent Claim 4. Burns further teaches:
wherein causing the first controller to control the data publisher comprises causing the first controller to instruct the data publisher to increase the publisher data flow rate or decrease the publisher data flow rate (Burns in par 0129, teaches that a PID controller determines whether the target rate limit should be throttled down by monitoring (e.g., comparing, etc.) the lag times (i.e., measured lag times) of events as compared to the target lag time. The rate limit of the system 400 may be throttled down in situations where the system 400 is not meeting the target lag time criterion. The target rate limit may be throttled down to allow the system 400 to recover (e.g., catch up, etc.) so that the system 400 can again meet the target lag time performance criterion. A PID controller may be configured to use, as an input, an error that is a difference between the average measured lag time and the target lag time).
Regarding Claim 7, Burns teaches the limitations contained in parent Claim 4. Burns further teaches:
wherein causing the first controller to control the data processing unit comprises causing the first controller to instruct the data processing unit to increase the computing resource consumption amount or decrease the computing resource consumption amount (Burns in par 0030, teaches o enable the EMB to recover to a point that the EMB is able to process events according to the target lag time. The EMB is said to throttle the target rate limit. Throttling, as used herein, refers to reducing, for a period of time (i.e., a throttling period), the number of events that will be accepted. When the actual processing time of accepted events exceeds the target lag time, the EMB may reduce (e.g., throttle) the rate of acceptance of events for processing. After the throttling period ends (e.g., expires, etc.), the rate limit may be reset to its original value. Burns in par 0129, teaches that a PID controller determines whether the target rate limit should be throttled down by monitoring (e.g., comparing, etc.) the lag times (i.e., measured lag times) of events as compared to the target lag time).
Regarding Claim 8, Burns teaches the limitations contained in parent Claim 4. Burns further teaches:
wherein causing the second controller to control the data processing unit comprises causing the second controller to instruct the data processing unit to increase the data processing flow rate or decrease the data processing flow rate (Burns in par 0030, teaches o enable the EMB to recover to a point that the EMB is able to process events according to the target lag time. The EMB is said to throttle the target rate limit. Throttling, as used herein, refers to reducing, for a period of time (i.e., a throttling period), the number of events that will be accepted. When the actual processing time of accepted events exceeds the target lag time, the EMB may reduce (e.g., throttle) the rate of acceptance of events for processing. After the throttling period ends (e.g., expires, etc.), the rate limit may be reset to its original value. Burns in par 0127 - 0129, teaches that each of the PID controllers 412A and 412B monitors a pipeline (or a portion thereof) of the system 400, without being part of the pipeline, to determine whether to throttle the rate limit at which the ingestion engine 402 accepts events. A PID controller (e.g., the PID controllers 412A and 412B) monitors how events flow through the pipeline (or portions thereof) of the system 400 in order to determine whether the system 400 is performing according to the target lag time, how far behind the target lag time the system 400 is performing, and how quickly the system 400 is recovering toward performing according to the target lag time).
Regarding Claim 10, Burns teaches the limitations contained in parent Claim 4. Burns further teaches:
]wherein causing the second controller to control the database comprises causing the second controller to instruct the database to increase the data storage rate or decrease the data storage rate (Burns in par 0048, teaches that an event management bus may be configured to monitor various types of events depending on needs of an industry and/or technology area. For example, information technology services may generate events in response to one or more conditions, such as, computers going offline, memory overutilization, CPU overutilization, storage quotas being met or exceeded, applications failing or otherwise becoming unavailable, networking problems (e.g., latency, excess traffic, unexpected lack of traffic, intrusion attempts, or the like), or the like, or combination thereof. Burns in par 0127 - 0129, teaches that each of the PID controllers 412A and 412B monitors a pipeline (or a portion thereof) of the system 400, without being part of the pipeline, to determine whether to throttle the rate limit at which the ingestion engine 402 accepts events. A PID controller (e.g., the PID controllers 412A and 412B) monitors how events flow through the pipeline (or portions thereof) of the system 400 in order to determine whether the system 400 is performing according to the target lag time, how far behind the target lag time the system 400 is performing, and how quickly the system 400 is recovering toward performing according to the target lag time).
Regarding Claim 11, this Claim merely recites an apparatus comprising at least one processor and at least one non-transitory memory including computer-coded instructions thereon (See Burns’ par 0077), the computer coded instructions, with the at least one processor, cause the apparatus to perform instructions as similarly disclosed in Claim 1. Accordingly, Burns discloses/teaches every limitation of Claim 11, as indicated in the above rejection of Claim 1.
Regarding Claim 12, this Claim merely recites an apparatus comprising at least one processor and at least one non-transitory memory including computer-coded instructions thereon (See Burns’ par 0077), the computer coded instructions, with the at least one processor, cause the apparatus to perform instructions as similarly disclosed in Claim 3. Accordingly, Burns discloses/teaches every limitation of Claim 12, as indicated in the above rejection of Claim 3.
Regarding Claim 13, this Claim merely recites an apparatus comprising at least one processor and at least one non-transitory memory including computer-coded instructions thereon (See Burns’ par 0077), the computer coded instructions, with the at least one processor, cause the apparatus to perform instructions as similarly disclosed in Claim 4. Accordingly, Burns discloses/teaches every limitation of Claim 13, as indicated in the above rejection of Claim 4.
Regarding Claim 14, this Claim merely recites an apparatus comprising at least one processor and at least one non-transitory memory including computer-coded instructions thereon (See Burns’ par 0077), the computer coded instructions, with the at least one processor, cause the apparatus to perform instructions as similarly disclosed in Claim 5. Accordingly, Burns discloses/teaches every limitation of Claim 14, as indicated in the above rejection of Claim 5.
Regarding Claim 16, this Claim merely recites an apparatus comprising at least one processor and at least one non-transitory memory including computer-coded instructions thereon (See Burns’ par 0077), the computer coded instructions, with the at least one processor, cause the apparatus to perform instructions as similarly disclosed in Claim 7. Accordingly, Burns discloses/teaches every limitation of Claim 16, as indicated in the above rejection of Claim 7.
Regarding Claim 17, this Claim merely recites an apparatus comprising at least one processor and at least one non-transitory memory including computer-coded instructions thereon (See Burns’ par 0077), the computer coded instructions, with the at least one processor, cause the apparatus to perform instructions as similarly disclosed in Claim 8. Accordingly, Burns discloses/teaches every limitation of Claim 17, as indicated in the above rejection of Claim 8.
Regarding Claim 19, this Claim merely recites an apparatus comprising at least one processor and at least one non-transitory memory including computer-coded instructions thereon (See Burns’ par 0077), the computer coded instructions, with the at least one processor, cause the apparatus to perform instructions as similarly disclosed in Claim 10. Accordingly, Burns discloses/teaches every limitation of Claim 19, as indicated in the above rejection of Claim 10.
Regarding Claim 20, this Claim merely recites a computer program product comprising at least one non-transitory computer-readable storage medium having computer program code stored thereon that (See Burns’ par 0077), in execution with at least one processor, configures the computer program product for performing instructions as similarly disclosed in Claim 1. Accordingly, Burns discloses/teaches every limitation of Claim 20, as indicated in the above rejection of Claim 1.
Allowable Subject Matter
Claims 6, 9, 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/ARIEL MERCADO-VARGAS/Primary Examiner, Art Unit 2118