DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group I in the reply filed on 04/27/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 19 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/27/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/16/2023 and 01/13/2026 were filed after the filing date of this application on 05/19/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 13 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for “the single crystal device layer comprises at least one of a single crystal silicon carbide”, does not reasonably provide enablement for “the single crystal device layer comprises at least one of … crystalline silicon carbide, and an amorphous silicon carbide”. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
The factors to determine if undue experimentation is required to make and use the invention include, but are not limited to: (A) The breadth of the claims; (B) The nature of the invention; (C) The state of the prior art; (D) The level of one of ordinary skill; (E) The level of predictability in the art; (F) The amount of direction provided by the inventor; (G) The existence of working examples; and (H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure.
In this case, factors B, C, D, E, F, G, and H suggest that the entire scope of claim 13 is not enabled. As applicant acknowledges in the specification as originally filed, the nature of the invention, the state of the art, and the level of ordinary skill in the art is that “amorphous silicon carbide” and “crystalline silicon carbide” are not single crystals. See, e.g., [0014] “The CVD used in the approach provide an amorphous or crystalline material having grain boundaries throughout the diamond layer, which is not a single crystal material. A single crystal material has a continuous crystal lattice throughout its volume and has no grain boundaries.” Additionally, applicant does not appear to provide any details regarding how a “single crystal device layer” could include grain boundaries and maintain its “continuous crystal lattice” throughout the layer resulting an incredible amount of experimentation that would contradict the accepted understanding of the term “single crystal”. Accordingly, applicant’s claim that “the single crystal device layer comprises” materials that are not single crystals is not enabled.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites “the single crystal device layer comprises at least one of a single crystal silicon carbide, crystalline silicon carbide and an amorphous silicon carbide.” The language is indefinite, because it is unclear how “the single crystal device layer” can comprise “crystalline silicon carbide and an amorphous silicon carbide” while the plain meaning of the words and applicant’s own specification indicate that “amorphous” and “crystalline” materials are not “single crystal” See, e.g., [0014] of the specification as originally filed. Additionally, “the single crystal device layer” lacks antecedent basis. It is unclear if applicant is referring to “the single crystal semiconductor layer” or “the semiconductor device layer”. For the purpose of this Office Action, the Office will interpret the claim as “a buried oxide layer formed between the semiconductor device layer and the silicon substrate, the buried oxide layer is adjacent to the semiconductor device layer, wherein the semiconductor device layer comprises at least one of a single crystal silicon carbide, crystalline silicon carbide and an amorphous silicon carbide.”
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 13 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 13 recites “the single crystal device layer comprises at least one of a single crystal silicon carbide, crystalline silicon carbide and an amorphous silicon carbide.” “Amorphous” and “crystalline” allow for materials that are not “single crystal”.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamoka et al. (US20220320813A1), hereafter Yamoka, in view of Menezo et al. (WO2023072610A1), hereafter Menezo.
Regarding claim 1, Yamoka disclose an optoelectronic device (Title) comprising: a silicon substrate (Fig. 1A element 101; [0030]); an epitaxial mesa formed on the silicon substrate (Fig. 1A element 106 and 107; [0036]-[0037] implicitly discloses “epitaxial” to a person of ordinary skill in the art based on the “a well-known crystal growth technique” since epitaxy is a common III-V crystal growth technique; See, e.g., [0012] disclosing epitaxy for III-V growth); a semiconductor material layer formed on the silicon substrate and between the silicon substrate and the epitaxial mesa (Fig. 1A element 102; [0040]), wherein the semiconductor material layer comprises a bandgap that is wider than a bandgap of the epitaxial mesa ([0031]); and a semiconductor device layer formed between the single crystal semiconductor material layer and the epitaxial mesa (Fig. 1A element 103). Yamoka does not explicitly disclose the semiconductor material is a single crystal semiconductor material. However, Menezo discloses using a single crystal semiconductor material (Fig. 2A element 200) between a substrate (Fig. 2A element 210) and a semiconductor device layer (Fig. 2A element 400). An advantage is to use a material with high thermal dissipation coefficient ([0057]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka with the semiconductor material is a single crystal semiconductor material as disclosed by Menezo in order to use a material with high thermal dissipation coefficient and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 2, Yamoka further discloses the epitaxial mesa comprises an optically active region ([0036]-[0037]), wherein the bandgap of the semiconductor material layer is wider than a bandgap of the optically active region ([0031]).
Regarding claim 3, Yamoka further discloses the epitaxial mesa comprises an optically passive region ([0041]).
Regarding claim 4, Yamoka further discloses the semiconductor material layer comprises silicon carbide ([0040]). Menezo further discloses forming the material layer as a single crystal layer ([0057]).
Regarding claim 5, Yamoka further discloses the semiconductor material layer comprises a thermal conductivity that is greater than 100 W/(m x K) ([0040] implicitly discloses the limitation since SiC has a thermal conductivity between 120 and 500 W/(m*K)).
Regarding claim 6, Yamoka further discloses a refractive index of the semiconductor material layer is less than 3.5 at a wavelength emitted by the optically active region ([0040] implicitly discloses the limitation since SiC has a refractive index of ~2.57-2.7).
Regarding claim 7, Yamoka further discloses the semiconductor device layer comprises at least one of a waveguide, a Bragg reflector, a grating, formed underneath the epitaxial mesa ([0041]).
Regarding claim 8, Yamoka does not explicitly disclose a first transparent conductive oxide (TCO) interconnect layer formed between the semiconductor device layer and the epitaxial mesa; and a second TCO interconnect layer formed on the epitaxial mesa opposite the silicon substrate. However, Menezo discloses a first interconnect layer formed between the semiconductor device layer and the epitaxial mesa (Fig. 2A where elements 604 connect to element 500); and a second interconnect layer formed on the epitaxial mesa opposite the silicon substrate (Fig. 2A where element 603 contacts the photonic stack). An advantage is to use electrical pumping to cause light emission. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka with a first interconnect layer formed between the semiconductor device layer and the epitaxial mesa; and a second interconnect layer formed on the epitaxial mesa opposite the silicon substrate as disclosed by Menezo in order to use electrical pumping to cause light emission. Yamoka in view of Menezo do not explicitly disclose using transparent conductive oxide for the interconnect layers. However, the Office takes Official notice that using transparent conductive oxide for the interconnect layers is well known in the art in order to provide an electrical contact that does not affect the light. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka in view of Menezo with transparent conductive oxide for the interconnect layers as is known in the art in order to provide an electrical contact that does not affect the light and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 9, Yamoka in view of Menezo do not explicitly disclose at least one of the first TCO interconnect layer and the second TCO interconnect layer comprises one of indium tin oxide and indium zinc oxide. However, the Office take Official Notice that indium tin oxide (ITO) and indium zinc oxide (IZO) are well known materials for electrical interconnects in the laser arts for the same reasons outlined above. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka in view of Menezo with at least one of the first TCO interconnect layer and the second TCO interconnect layer comprises one of indium tin oxide and indium zinc oxide as is known in the art in order to provide an electrical contact that does not affect the light and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 10, Yamoka further discloses the optically active region comprises one or more layers of bulk material, quantum dots, quantum wells, quantum- dash structures, and nanowires ([0035]).
Regarding claim 14, Yamoka further discloses the semiconductor material layer is formed directly on the silicon substrate (Fig. 1A element 102 is directly on element 101).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamoka in view of Menezo in view of Caer et al. (US20180323575A1), hereafter Caer.
Regarding claim 11, Yamoka further discloses a first semiconductor material layer formed between the semiconductor device layer and the optically active region (Fig. 2A element 151 below element 106; [0040]); and a second semiconductor material layer formed on the optically active region opposite the first semiconductor material layer (Fig. 2A element 151 above element 106; [0040]), wherein at least one of the first semiconductor material layer and the second semiconductor material layer comprises a Group III-V material ([0036]). Yamoka does not explicitly disclose the epitaxial mesa comprises: a first separate-confinement heterostructure (SCH) layer formed between the first semiconductor material layer and the optically active region, and a second SCH layer formed between the optically active region and the second semiconductor material layer. However, Caer discloses the epitaxial mesa comprises: a first separate-confinement heterostructure (SCH) layer formed between the first semiconductor material layer and the optically active region ([0063]), and a second SCH layer formed between the optically active region and the second semiconductor material layer ([0063]). An advantage, as is known in the art, is to help confine light to the active region. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka in view of Menezo with the epitaxial mesa comprises: a first separate-confinement heterostructure (SCH) layer formed between the first semiconductor material layer and the optically active region, and a second SCH layer formed between the optically active region and the second semiconductor material layer as disclosed by Caer in order to help confine light to the active region.
Regarding claim 12, Yamoka in view of Menezo in further view of Caer do not explicitly disclose the first semiconductor material layer is bonded directly onto the semiconductor device layer. However, the Office takes Official Notice that direct bonding of semiconductor layers is well known in the art in order to create high bonding strength and high temperature stability. Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka in view of Menezo in further view of Caer with the first semiconductor material layer is bonded directly onto the semiconductor device layer as is known in the art in order to make a high strength bond that has high temperature stability.
Regarding claim 13, Yamoka further discloses the semiconductor device layer comprises at least one of a single crystal silicon carbide, crystalline silicon carbide and an amorphous silicon carbide ([0046]). Yamoka does not explicitly disclose a buried oxide layer formed between the semiconductor device layer and the silicon substrate, the buried oxide layer is adjacent to the semiconductor device layer. However, Caer discloses a buried oxide layer formed between the semiconductor device layer and the silicon substrate (Fig. 3 element 101 is between elements 100 and 102), the buried oxide layer is adjacent to the semiconductor device layer (Fig. 3 element 102 and 101 are adjacent). An advantage is to provide the optical coupling ([0047]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka in view of Menezo with a buried oxide layer formed between the semiconductor device layer and the silicon substrate, the buried oxide layer is adjacent to the semiconductor device layer as disclosed by Caer in order to provide the optical coupling.
Claims 15, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamoka in view of Caer.
Regarding claim 15, Yamoka discloses an optical device (Title), comprising: an optical cavity configured to create lasing conditions ([0036]), the optical cavity formed on a silicon substrate (Fig. 1A element 101); a thermally conductive region provided between the silicon substrate and the optical cavity (Fig. 1A element 102), and an optical device integration region formed between the optical cavity and the thermally conductive region (Fig. 1A elements 103 and 104 are formed between element 105 and 102). Yamoka does not explicitly disclose lasing based on an injection current or wherein the thermally conductive region is electrically insulating. However, Caer discloses lasing based on an injection current ([0003]; Fig. 1 elements 110-110b and 111-111b) and wherein the thermally conductive region is electrically insulating ([0031] and [0033]). An advantage is to use a known pumping mechanism ([0001]) and to insulate the III-V stack ([0033]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka with lasing based on an injection current or wherein the thermally conductive region is electrically insulating as disclosed by Caer in order to use a known pumping mechanism and to insulate the III-V stack.
Regarding claim 17, Yamoka further discloses the semiconductor material layer comprises a thermal conductivity that is greater than 100 W/(m x K) ([0040] implicitly discloses the limitation since SiC has a thermal conductivity between 120 and 500 W/(m*K)).
Regarding claim 18, Yamoka further disclose the thermally conductive region is directly between the silicon substrate and the optical cavity (Fig. 1A element 102 is between elements 101 and 105).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yamoka in view of Caer, as applied to claim 15 above, in further view of Menezo.
Regarding claim 16, Yamoka further discloses the thermally conductive region comprises silicon carbide (Fig. 1 element 102; [0040]). Yamoka in view of Caer do not explicitly disclose the semiconductor material is a single crystal semiconductor material. However, Menezo discloses using a single crystal semiconductor material (Fig. 2A element 200) between a substrate (Fig. 2A element 210) and a semiconductor device layer (Fig. 2A element 400). An advantage is to use a material with high thermal dissipation coefficient ([0057]). Accordingly, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to modify Yamoka in view of Caer with the semiconductor material is a single crystal semiconductor material as disclosed by Menezo in order to use a material with high thermal dissipation coefficient and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA KING whose telephone number is (571)270-1441. The examiner can normally be reached Monday to Friday 10am-5pm MT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Min Sun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Joshua King/Primary Examiner, Art Unit 2828 07/07/2026
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