Prosecution Insights
Last updated: April 19, 2026
Application No. 18/320,804

Secondary side peak current controlled mode flyback converter

Non-Final OA §103
Filed
May 19, 2023
Examiner
LAXTON, GARY L
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cypress Semiconductor Corporation
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
93%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
943 granted / 1090 resolved
+18.5% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
1116
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
34.8%
-5.2% vs TC avg
§102
40.3%
+0.3% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1090 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-9, 14-16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shah et a. (US 10910954) in view of Patel et al. (US 20130229832). Claims 1, 14 and 20; Shah et al. disclose an apparatus comprising: a flyback converter comprising: rectifier (210), a flyback transformer (204) and a signal transformer (fig. 2D: 282); a primary side comprising a primary-side controller (218) coupled to a power switch (216), the flyback transformer (e.g. Np) and the signal transformer (282); and a secondary side comprising a secondary-side controller (202) coupled to the flyback transformer (e.g. Ns) and the signal transformer (282), wherein the secondary-side controller is configured to cause a pulse width modulation (PWM) signal to be generated, based on a set of parameters (e.g. fig. 2A: SR_SNS, 226a; SR- Vss, Vbus_in, Vbus_out, etc.) and an operational status of the power switch (ON/OFF status, voltage resonance status, Valley minimum status, valley switching modes status, etc.: see col. 5 lines 12-20), to control operation of the primary-side controller. Moreover, Shah et al. disclose obtaining parameters: (e.g. fig. 2A: SR_SNS, 226a; SR-Vss,Vbus_in, Vbus_out, etc.); power switch is off during valley resonance, turning power switch ON (e.g. col. 5 lines 15-18; col. 11 lines 65-67). Of course, when turning the power switch the voltage waveform across the primary winding NP and transformer will ramp up at a rate based on those parameters that holds the switch ON for the duration or length of period determined by the secondary controller. However, Shah et al. do not disclose whether the secondary-side controller is configured at least to operate in a current control mode. Patel et al. teach how well-known it is to control a flyback converter 104 in a current mode control that controls the current output of flyback converter 104 (see para. [0023]). Claims 2 and 3; Shah et al. disclose the claimed subject matter in regards to claim 1 supra, except for operating in CCM or DCM. Patel et al. teach an AC-to-DC power converters a controller that can operate in different modes of operations, such as, discontinuous conduction mode (128), or continuous conduction mode (126). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Shah et al. to include operating in CCM in order to provide continuous power to the load for high power demand and to operate in DCM during low load demand to increase efficiency. Claims 5 and 15; AC voltage input parameter (Shah et al. fig. 8: 292). Of course, the ramping up of the voltage waveform would be proportional to the input voltage and inductance of the primary winding since the power switch is connected to the input voltage and the primary. Claims 6 and 13; Shah et al. disclose the claimed subject matter in regards to claim 1 supra, except for storing parameters in firmware. Patel et al. teach that the methods and processes described in the detailed description section can be embodied as code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Shah et al. to include providing code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium to implement control as taught by Patel et al. Claims 7 and 16; obtaining parameters: (e.g. fig. 2A: SR_SNS, 226a; SR-Vss, Vbus_in, Vbus_out, etc.); determining the switch is OFF (e.g. valley switching mode operation), e.g. power switch is off during valley resonance. While power switch is OFF, of course, the voltage waveform across the primary and transformer ramps down. Claims 8 and 16; of course, the ramping down of the voltage waveform would be proportional to the output voltage and inductance of the secondary winding. Claim 9; Shah et al. disclose the claimed subject matter in regards to claim 1 supra, except for storing parameters in firmware. Patel et al. teach that the methods and processes described in the detailed description section can be embodied as code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Shah et al. to include providing code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium to implement control as taught by Patel et al. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shah et al. and Patel et al in view of Rai (US 10862399). Claim 13; Shah et al. and Patel et al. disclose the claimed subject matter in regards to claim 1 supra, except for using a serial bus. Rai teaches it is known in art for providing a serial bus-compatible power supply device, such as a serial bus power delivery (SBPD) device with a power control analog subsystem having hardware, firmware, or any combination to store information and to be used and communicated by a secondary side controller for communicating to a primary side controller to implement a control scheme. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Shah et al. to include providing a serial bus-compatible power supply device, such as a serial bus power delivery (SBPD) device with a power control analog subsystem having hardware, firmware, or any combination to store information and to be used and communicated by a secondary side controller for communicating to a primary side controller to implement a control scheme as taught by Rai Allowable Subject Matter Claims 10-12 and 17-19 are still objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GARY L LAXTON/Primary Examiner, Art Unit 2838 3/02/2026
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Prosecution Timeline

May 19, 2023
Application Filed
May 19, 2025
Non-Final Rejection — §103
Jun 04, 2025
Interview Requested
Jun 11, 2025
Examiner Interview Summary
Jun 11, 2025
Applicant Interview (Telephonic)
Jul 31, 2025
Response Filed
Oct 08, 2025
Final Rejection — §103
Nov 14, 2025
Interview Requested
Nov 25, 2025
Response after Non-Final Action
Dec 18, 2025
Request for Continued Examination
Jan 08, 2026
Response after Non-Final Action
Mar 02, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
93%
With Interview (+6.6%)
2y 4m
Median Time to Grant
High
PTA Risk
Based on 1090 resolved cases by this examiner. Grant probability derived from career allow rate.

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