DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 2 (Figure 3) in the reply filed on 03/16/2026 is acknowledged. The traversal is on the ground(s) that the Examiner has not established a serious search burden because the claims as currently recited are generic to both species, the Examiner has not established that the species require different fields of search, and the Examiner has not established separate status in the art. The Examiner respectfully disagrees and the arguments are not found to be persuasive. The fact that the claims are generic to multiple species does not preclude a proper election of species requirement as an election of species requirement is made based on the species presented not the claims presented as it limits the Applicant to claiming one invention. The existence of generic claims does not eliminate the search burden arising from the presence of patentably distinct species. Furthermore, Applicant’s position assumes that prior art directed to one species would necessarily be relevant to the other species because the species disclosed possess different structures and operational characteristics. The cited classification was cited as evidence that the technologies associated with the respective species are recognized in different areas of the art and may require different search resources, classification and search strategies. Species 1 and Species 2 are not merely alternative layouts of the same circuitry. Species 2 includes a distinct configuration of switches 304, 305 and 306 with a connection of switch 306 to the output node that introduces a different operational characteristic not possible with Species 1. The different therefore extends beyond mere structural variation and represents a distinct technological approach. Accordingly, the species presented have acquired a separate status in the art and are properly treated as being patentably distinct.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/20/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6-8, 13-15 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Zeinali (US 2022/0337160 A1).
Regarding claim 1, Zeinali teaches an apparatus (Figure 1A), comprising: an inductor (Figure 1A Component L) coupled between an input power supply node (Figure 1A Component Vin) and a switch node (Figure 1A Component 112); a shared capacitor coupled to the switch node (Figure 1A Component CBout); a switch device configured to couple the switch node to a ground supply node (Figure 1A Component S1) in response to an activation of a magnetize control signal (Figure 1A Component S1 Control Signal; Paragraph 0032); a first switch circuit (Figure 1A Component Sout,1) configured, in response to an activation of a first de-magnetize signal (Figure 1A Component Sout,1 Driver Output Signal), to generate a first boost voltage using the shared capacitor (Figure 1A Component Sout,1 outputs a voltage Vout,1 based on a voltage outputted by Component CBout to node Component 112), and couple the switch node to a first regulated power supply node using the first boost voltage (Figure 1A Component Sout,1 generates Vout,1 to an output pin node seen at the top terminal of Component Cout,1 and couples the switching node to the output node); and a second switch circuit (Figure 1A Component Sout,2) configured, in response to an activation of a second de-magnetize signal (Figure 1A Component Sout,2 Driver Output Signal), to generate a second boost voltage using the shared capacitor (Figure 1A Component Sout,2 outputs a voltage Vout,2 based on a voltage outputted by Component CBout to node Component 112), and couple the switch node to a second regulated power supply node using the second boost voltage (Figure 1A Component Sout,2 generates Vout,2 to an output pin node seen at the top terminal of Component Cout,2 and couples the switching node to the output node).
Regarding claim 4, Zeinali teaches all the limitations of claim 1. Zeinali further teaches a control circuit configured to: activate the magnetize control signal during a first time period (Figure 3 Component Phase 1 is the first time period); activate the first de-magnetize signal during a second time period subsequent to the first time period (Figure 3 Component Phase 2 is a second time period); activate the magnetize control signal during a third time period subsequent to the second time period (Figure 3 shows that after Phase 2 the Inductor is again charged which is the third time period); and activate the second de-magnetize signal during a fourth time period subsequent to the third time period (Figure 3 Component Vout,2 outputting phase is the fourth time period).
Regarding claim 6, Zeinali teaches all the limitations of claim 1. Zeinali further teaches a diode coupled between the shared capacitor and the input power supply node (Figure 1A Component SBout connects CBout to VC; Paragraph 0034 “when a voltage level of input voltage V.sub.in is sufficient for driving plurality of output switches 104, input voltage V.sub.in may be utilized as output bootstrap voltage source VC”; That passage highlights that VC can be Vin; Paragraph 0016 “exemplary output bootstrap switch may include a bootstrap diode”).
Regarding claim 7, Zeinali teaches a method (Figure 1A), comprising: magnetizing an inductor (Figure 1A Component L) and charging a shared capacitor (Figure 1A Component CBout) during a first time period (Figure 3 Component Phase 1 is the first time period; S1 and SBout turn on at the same time as highlighted by Paragraphs 0035 and 0036), wherein the inductor and capacitor are included in a power converter circuit (Figure 1A is a power converter circuit having the inductor and shared capacitor), wherein the inductor is coupled to an input power supply node (Figure 1A Component Vin) and a switch node of the power converter circuit (Figure 1A Component 112; Component L is coupled to Component Vin and Component 112), and wherein the shared capacitor is coupled to the switch node (Figure 1A Component CBout is coupled to Component 112); generating a first boost voltage using the shared capacitor (Figure 1A Component Sout,1 outputs a voltage Vout,1 based on a voltage outputted by Component CBout to node Component 112) and coupling the switch node to a first regulated power supply node using the first boost voltage during a second time period subsequent to the first time period (Figure 1A Component Sout,1 generates Vout,1 to an output pin node seen at the top terminal of Component Cout,1 and couples the switching node to the output node; Figure 3 Component Phase 2 is a second time period); magnetizing the inductor and charging the shared capacitor during a third time period subsequent to the second time period (Figure 3 shows that after Phase 2 the Inductor is again charged which is the third time period); and generating a second boost voltage using the shared capacitor (Figure 1A Component Sout,2 outputs a voltage Vout,2 based on a voltage outputted by Component CBout to node Component 112) and coupling the switch node to a second regulated power supply node using the second boost voltage during a fourth time period subsequent to the third time period (Figure 1A Component Sout,2 generates Vout,2 to an output pin node seen at the top terminal of Component Cout,2 and couples the switching node to the output node; Figure 3 Component Vout,2 outputting phase is the fourth time period).
Regarding claim 8, Zeinali teaches all the limitations of claim 7. Zeinali further teaches wherein magnetizing the inductor includes coupling the switch node to a ground supply node (Figure 1A shows that the inductor charges when Component S1 is turned ON which would couple the switching node to ground; This is an inherent operation to charge and magnetize an inductor).
Regarding claim 13, Zeinali teaches all the limitations of claim 7. Zeinali further teaches wherein the shared capacitor is further coupled to the input power supply node via a diode (Figure 1A Component SBout connects CBout to VC; Paragraph 0034 “when a voltage level of input voltage V.sub.in is sufficient for driving plurality of output switches 104, input voltage V.sub.in may be utilized as output bootstrap voltage source VC”; That passage highlights that VC can be Vin; Paragraph 0016 “exemplary output bootstrap switch may include a bootstrap diode”).
Regarding claim 14, Zeinali teaches an apparatus (Figure 1A), comprising: a first circuit block (Figure 1A Component Sout,1) coupled to a first regulated power supply node (Figure 1A Component output node outputting Component Vout,1); a second circuit block (Figure 1A Component Sout,2) coupled to a second regulated power supply node (Figure 1A Component output node outputting Component Vout,2); and a power converter circuit (Figure 1A Component 100) that includes an inductor (Figure 1A Component L) coupled between an input power supply node (Figure 1A Component 110) and a switch node (Figure 1A Component 112), and a shared capacitor coupled to the switch node (Figure 1A Component CBout), wherein the power converter circuit is configured to: magnetize the inductor and charge the shared capacitor during a first time period (Figure 3 Component Phase 1 is the first time period); during a second time period, generate a first boost voltage using the shared capacitor and couple, using the first boost voltage, the switch node to the first regulated power supply node to generate a first voltage on the first regulated power supply node (Figure 1A Component CBout is used to generate a voltage at node 112; Component Sout,1 couples the switching node to the output node outputting Vout,1; Component Vout,1 is generated based on the voltage; Figure 3 Component Phase 2 is the second time period), wherein the second time period subsequent to the first time period (Figure 3 Component Phase 2 happens after Phase 1); magnetize the inductor and charge the shared capacitor during a third time period is subsequent to the second time period (Figure 3 shows that after Phase 2 the Inductor is again charged which is the third time period); and during a fourth time period, generate a second boost voltage using the shared capacitor and couple, using the second boost voltage, the switch node to the second regulated power supply node to generate a second voltage on the second regulated power supply node (Figure 1A Component CBout is used to generate a voltage at node 112; Component Sout,2 couples the switching node to the output node outputting Vout,2; Component Vout,2 is generated based on the voltage; Figure 3 Component Vout,2 outputting phase is the fourth time period), wherein the fourth time period is subsequent to the third time period (Figure 3 the outputting of Vout,2 phase is after the second charging phase).
Regarding claim 15, Zeinali teaches all the limitations of claim 14. Zeinali further teaches wherein to magnetize the inductor, the power converter circuit is further configured to couple the switch node to a ground supply node (Figure 1A shows that the inductor charges when Component S1 is turned ON which would couple the switching node to ground; This is an inherent operation to charge and magnetize an inductor).
Regarding claim 20, Zeinali teaches all the limitations of claim 14. Zeinali further teaches wherein the shared capacitor is further coupled to the input power supply node via a diode (Figure 1A Component SBout connects CBout to VC; Paragraph 0034 “when a voltage level of input voltage V.sub.in is sufficient for driving plurality of output switches 104, input voltage V.sub.in may be utilized as output bootstrap voltage source VC”; That passage highlights that VC can be Vin; Paragraph 0016 “exemplary output bootstrap switch may include a bootstrap diode”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 11-12 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zeinali (US 2022/0337160 A1) in view of Wei (US 10622900 B1).
Regarding claim 5, Zeinali teaches all the limitations of claim 4. Zeinali does not teach wherein the control circuit is further configured to: determine a first duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage; and determine a second duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage.
Wei teaches a single inductor multiple output DC/DC converter (Figure 2a), comprising: a first switch circuit (Figure 2a Component S1) outputting a first voltage at a first regulated power supply node (Figure 2a Component Vo1); a second switch circuit (Figure 2a Component S2) outputting a second voltage at a second regulated power supply node (Figure 2a Component Vo2); a control circuit (Figure 2a Components EA+201) configured to: determine a first duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage (Figure 2a Component EA outputting VEA1 and compares VFB1, which is indicative of the voltage Vo1, with a reference voltage, VR1); and determine a second duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage (Figure 2a Component EA outputting VEA2 and compares VFB2, which is indicative of the voltage Vo2, with a reference voltage, VR2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zeinali to incorporate a feedback control scheme as taught by Wei. The advantage of this proposed modification is that it improves voltage regulation accuracy, accommodate for changing load conditions while maintaining desired output voltages and reduce any output voltage ripple.
Regarding claim 11, Zeinali teaches all the limitations of claim 7. Zeinali does not teach determining a duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage.
Wei teaches a single inductor multiple output DC/DC converter (Figure 2a), comprising: a first switch circuit (Figure 2a Component S1) outputting a first voltage at a first regulated power supply node (Figure 2a Component Vo1); a second switch circuit (Figure 2a Component S2) outputting a second voltage at a second regulated power supply node (Figure 2a Component Vo2); a control circuit (Figure 2a Components EA+201) configured to: determine a first duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage (Figure 2a Component EA outputting VEA1 and compares VFB1, which is indicative of the voltage Vo1, with a reference voltage, VR1); and determine a second duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage (Figure 2a Component EA outputting VEA2 and compares VFB2, which is indicative of the voltage Vo2, with a reference voltage, VR2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zeinali to incorporate a feedback control scheme as taught by Wei. The advantage of this proposed modification is that it improves voltage regulation accuracy, accommodate for changing load conditions while maintaining desired output voltages and reduce any output voltage ripple.
Regarding claim 12, Zeinali teaches all the limitations of claim 11. Zeinali does not teach determining a duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage.
Wei teaches a single inductor multiple output DC/DC converter (Figure 2a), comprising: a first switch circuit (Figure 2a Component S1) outputting a first voltage at a first regulated power supply node (Figure 2a Component Vo1); a second switch circuit (Figure 2a Component S2) outputting a second voltage at a second regulated power supply node (Figure 2a Component Vo2); a control circuit (Figure 2a Components EA+201) configured to: determine a first duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage (Figure 2a Component EA outputting VEA1 and compares VFB1, which is indicative of the voltage Vo1, with a reference voltage, VR1); and determine a second duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage (Figure 2a Component EA outputting VEA2 and compares VFB2, which is indicative of the voltage Vo2, with a reference voltage, VR2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zeinali to incorporate a feedback control scheme as taught by Wei. The advantage of this proposed modification is that it improves voltage regulation accuracy, accommodate for changing load conditions while maintaining desired output voltages and reduce any output voltage ripple.
Regarding claim 18, Zeinali teaches all the limitations of claim 14. Zeinali does not teach wherein the power converter circuit is further configured to determine a duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage.
Wei teaches a single inductor multiple output DC/DC converter (Figure 2a), comprising: a first switch circuit (Figure 2a Component S1) outputting a first voltage at a first regulated power supply node (Figure 2a Component Vo1); a second switch circuit (Figure 2a Component S2) outputting a second voltage at a second regulated power supply node (Figure 2a Component Vo2); a control circuit (Figure 2a Components EA+201) configured to: determine a first duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage (Figure 2a Component EA outputting VEA1 and compares VFB1, which is indicative of the voltage Vo1, with a reference voltage, VR1); and determine a second duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage (Figure 2a Component EA outputting VEA2 and compares VFB2, which is indicative of the voltage Vo2, with a reference voltage, VR2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zeinali to incorporate a feedback control scheme as taught by Wei. The advantage of this proposed modification is that it improves voltage regulation accuracy, accommodate for changing load conditions while maintaining desired output voltages and reduce any output voltage ripple.
Regarding claim 19, Zeinali teaches all the limitations of claim 14. Zeinali does not teach wherein the power converter circuit is further configured to determine a duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage.
Wei teaches a single inductor multiple output DC/DC converter (Figure 2a), comprising: a first switch circuit (Figure 2a Component S1) outputting a first voltage at a first regulated power supply node (Figure 2a Component Vo1); a second switch circuit (Figure 2a Component S2) outputting a second voltage at a second regulated power supply node (Figure 2a Component Vo2); a control circuit (Figure 2a Components EA+201) configured to: determine a first duration of the second time period using a first voltage level of the first regulated power supply node and a first reference voltage (Figure 2a Component EA outputting VEA1 and compares VFB1, which is indicative of the voltage Vo1, with a reference voltage, VR1); and determine a second duration of the fourth time period using a second voltage level of the second regulated power supply node and a second reference voltage (Figure 2a Component EA outputting VEA2 and compares VFB2, which is indicative of the voltage Vo2, with a reference voltage, VR2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zeinali to incorporate a feedback control scheme as taught by Wei. The advantage of this proposed modification is that it improves voltage regulation accuracy, accommodate for changing load conditions while maintaining desired output voltages and reduce any output voltage ripple.
Allowable Subject Matter
Claims 2-3, 9-10 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
Regarding claim 2, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the first switch circuit includes: a level-shift circuit configured to translate a first voltage level of the first de-magnetize signal using the first boost voltage to generate a first shifted signal; and a switch device configured to couple the switch node and the first regulated power supply node using the first shifted signal.
Regarding claim 3, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the second switch circuit includes: a level-shift circuit configured to translate a second voltage level of the second de-magnetize signal using the second boost voltage to generate a second shifted signal; and a switch device configured to couple the switch node and the second regulated power supply node using the second shifted signal.
Regarding claim 9, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein coupling the switch node to the first regulated power supply node includes: translating a first voltage level of a first control signal using the first boosted voltage to generate a first shifted signal; and activating a first switch device using the first shifted signal, wherein the first switch device is coupled between the switch node and the first regulated power supply node. Claim 10 depends upon claim 9.
Regarding claim 16, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests the power converter circuit is further configured to: translate a first voltage level of a first control signal using the first boost voltage to generate a first shifted signal; and activate the first switch device using the first shifted signal. Claim 17 depends upon claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hoyerby (US 2014/0300413 A1) teaches a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to a first gate voltage. A second charging path is connectable between the gate terminal of the power transistor and a second supply voltage to charge the gate terminal from the first gate voltage to a second gate voltage larger or higher than the first gate voltage. A voltage of the second voltage supply is higher than a voltage of the first voltage supply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
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