Prosecution Insights
Last updated: October 01, 2026
Application No. 18/321,526

ORCHESTRATION OF QUBO JOBS BETWEEN GATE-BASED QUANTUM COMPUTERS AND QUANTUM ANNEALERS

Non-Final OA §102
Filed
May 22, 2023
Examiner
CARDWELL, ERIC
Art Unit
2139
Tech Center
2100 — Computer Architecture & Software
Assignee
Dell Products L.P.
OA Round
2 (Non-Final)
88%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
577 granted / 656 resolved
+33.0% vs TC avg
Moderate +12% lift
Without
With
+11.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
16 currently pending
Career history
671
Total Applications
across all art units

Statute-Specific Performance

§101
4.6%
-35.4% vs TC avg
§103
49.3%
+9.3% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
9.3%
-30.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on April 23rd, 2026, has been entered. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dukatz et al. [US2018/0308000]. Dukatz teaches quantum computing machine learning module.. Regarding claims 1 and 11, Dukatz teaches a method, comprising: obtaining information about a first pre-defined implementation of a QUBO (quadratic unconstrained binary optimization) problem [Dukatz paragraph 0094, first lines “…The system obtains a first set of data, the first set of data including data representing multiple computational tasks previously performed by the system (step 302). In some implementations the multiple computational tasks previously performed by the system may include optimization tasks…”(where the examiner has determined previously performed computational tasks reads on the BRI of what a pre-defined implementation of a QUBO could be considered to be. Since QUBO’s are multiple computational tasks.)] configured for execution on a gate-based device [Dukatz paragraph 0095, middle lines “…may have been routed to one or more quantum gate computers…”]; obtaining information about a second pre-defined implementation of the QUBO problem [Dukatz paragraph 0095, first lines “…The system obtains input data for the multiple computational tasks previously performed by the system, including data representing a type of computing resource the task was routed to (step 304). For example, previously performed optimization tasks may have been routed to one or more quantum annealers or to one or more classical computers…”] configured for execution on an annealing device [Dukatz paragraph 0095, middle lines “…to one ore more quantum annealers…”]; receiving information about a QUBO job that is to be executed [Dukatz paragraph 0015, all lines “…The system receives data representing a computational task to be performed by a system including one or more quantum computing resources, e.g., one or more quantum gate computers, adiabatic annealers, or quantum simulators, and one or more classical computing resources, e.g., one or more classical computers or super computers…”]; identifying first hardware and second hardware that are available to execute the QUBO job [Dukatz paragraph 0059, all lines “…The additional computing resources 110a-110d may include one or more quantum gate processors, e.g., quantum gate processor 110b. A quantum gate processor includes one or more quantum circuits, i.e., models for quantum computation in which a computation is performed using a sequence of quantum logic gates, operating on a number of qubits (quantum bits)…” and paragraph 0058, first lines “…The additional computing resources 110a-110d may include quantum annealer computing resources, e.g., quantum annealer 110a. A quantum annealer is a device configured to perform quantum annealing—a procedure for finding the global minimum of a given objective function over a given set of candidate states using quantum tunneling…” and paragraph 0060, first lines “…The additional computing resources 110a-110d may include one or more quantum simulators, e.g., quantum simulator 110c. A quantum simulator is a quantum computer that may be programmed to simulate other quantum systems and their properties…”], and the first hardware is different from the second hardware [Dukatz figure 1A, feature 110a, 110b, 110c, and 110d are all different from one another]; using the information about the first and second pre-defined implementations of the QUBO problem [Dukatz paragraph 0019, most lines “…for each computational task, one or more of: (i) data representing a size of an input data set associated with the computational task; (ii) data indicating whether an input data set associated with the computational task comprised static, real time or both static and real time input data; (iii) data representing an error tolerance associated with the computational task; and (iv) data representing a required level of confidence associated with the computational task…”] to generate respective predictions concerning performance of the QUBO job on the first hardware and the second hardware [Dukatz paragraph 0090, most lines “…data representing properties of using the corresponding computing resource to solve the computational task may include data representing an approximate quality of the generated solution, a computational time associated with the generated solution, or a computational cost associated with the generated solution. In some implementations, the machine learning model may receive data representing multiple solutions to multiple computational tasks and data representing properties of using the corresponding computing resources to solve the multiple computational tasks in parallel…”]; comparing the predictions [Dukatz paragraph 0073, first lines “…Forecast data may be compared to current conditions and optimization task objectives to determine whether a current optimization task and corresponding task objectives are similar to previously seen optimization tasks and corresponding task objectives…”]; and based on the comparing, selecting one of the first hardware and the second hardware for execution of the QUBO job [Dukatz paragraph 0088, last lines “…The machine learning model 204 is configured to process the received data and to determine which of the one or more additional computing resources 110a-110d to route the received data representing the computational task or sub tasks to…”]. Regarding claims 2 and 12, as per claim 1, Dukatz wherein the first hardware comprises a gate-based device operable to execute a quantum circuit [Dukatz paragraph 0059, all lines “…The additional computing resources 110a-110d may include one or more quantum gate processors, e.g., quantum gate processor 110b. A quantum gate processor includes one or more quantum circuits, i.e., models for quantum computation in which a computation is performed using a sequence of quantum logic gates, operating on a number of qubits (quantum bits)…”]. Regarding claims 3 and 13, as per claim 1, Dukatz the second hardware comprises an annealing device that comprises a quantum annealing device, or a simulated annealing device [Dukatz paragraph 0058, first lines “…The additional computing resources 110a-110d may include quantum annealer computing resources, e.g., quantum annealer 110a. A quantum annealer is a device configured to perform quantum annealing—a procedure for finding the global minimum of a given objective function over a given set of candidate states using quantum tunneling…” and paragraph 0060, first lines “…The additional computing resources 110a-110d may include one or more quantum simulators, e.g., quantum simulator 110c. A quantum simulator is a quantum computer that may be programmed to simulate other quantum systems and their properties…”]. Regarding claims 4 and 14, as per claim 1, Dukatz teaches the first hardware and the second hardware are both elements of a single heterogeneous computing infrastructure [Dukatz figure 1A, 110a-d are all in a single heterogeneous computing infrastructure]. Regarding claims 5 and 15, as per claim 1, Dukatz teaches each of the pre-defined implementation of the QUBO problem defines a different respective combination of hardware and software [Dukatz paragraph 0039, last lines “…The training data includes data from several sources, as described below, which may be used to generate multiple training examples. Each training example can include (i) input data relating to a previous computational task, e.g., data specifying the task, size/complexity of the task, restrictions for solving the task, error tolerance, (ii) information relating to which device was used to solve the task, or (iii) metrics indicating a quality of the solution obtained using the device, e.g., a level of confidence in the solution, computational time taken to generate the solution, or computational costs incurred…”] Regarding claims 6 and 16, as per claim 1, Dukatz teaches each of the predictions indicates how closely the respective performances of the QUBO job conform with one or more requirements of a service level objective [Dukatz paragraph 0104, most lines “…the obtained input data may also include data representing a required level of confidence associated with the computational task. For example, certain types of quantum computers will provide a probabilistic rather than a deterministic result, and based on the amount of cycles on the quantum computer the confidence in the result can be increased. A required level of confidence associated with a computational task may be used to determine which computing resource to route the computational task to. For example, some computing resources may be configured to generate solutions to computational tasks that are more likely to be accurate than solutions generated by other computing resources. Solutions to computational tasks that require high levels of confidence may therefore be routed to computing resources that are more likely to produce accurate solutions to the computational tasks. For example, such computational tasks may not be provided to an adiabatic quantum processor that may, in some cases, produce a range of solutions with varying degrees of confidence…”]. Regarding claims 7 and 17, as per claim 1, Dukatz teaches the QUBO job is orchestrated to whichever of a gate-based device, or an annealing device, exhibits the better predicted performance of the QUBO job [Dukatz paragraph 0088, last lines “…The machine learning model 204 is configured to process the received data and to determine which of the one or more additional computing resources 110a-110d to route the received data representing the computational task or sub tasks to…”]. Regarding claims 8 and 18, as per claim 1, Dukatz teaches the first hardware comprises an annealing device in a form of either a real quantum computing hardware, or a simulation engine operable to simulate quantum computing hardware [Dukatz paragraph 0058, first lines “…The additional computing resources 110a-110d may include quantum annealer computing resources, e.g., quantum annealer 110a. A quantum annealer is a device configured to perform quantum annealing—a procedure for finding the global minimum of a given objective function over a given set of candidate states using quantum tunneling…” and paragraph 0060, first lines “…The additional computing resources 110a-110d may include one or more quantum simulators, e.g., quantum simulator 110c. A quantum simulator is a quantum computer that may be programmed to simulate other quantum systems and their properties…”]. Regarding claims 9 and 19, as per claim 1, Dukatz teaches the second hardware comprises a gate-based device in a form of either real quantum computing hardware, or a simulation engine operable to simulate quantum computing hardware [Dukatz paragraph 0059, all lines “…The additional computing resources 110a-110d may include one or more quantum gate processors, e.g., quantum gate processor 110b. A quantum gate processor includes one or more quantum circuits, i.e., models for quantum computation in which a computation is performed using a sequence of quantum logic gates, operating on a number of qubits (quantum bits)…”]. Regarding claims 10 and 20, as per claim 1, Dukatz teaches the selecting of the hardware is performed in response to invocation of a function that specifies a set of elements of the QUBO job, and the elements of the QUBO problem comprise (a) a set of constraints to be satisfied in an optimization of a solution to the QUBO job, and (b) service level objective constraints [Dukatz paragraph 0039, all lines “…The system decides when and where to outsource computations associated with the received computational tasks. Such task routing may be a complex problem that is dependent on many factors. The system is trained to learn optimal routings of received computational tasks using a set of training data. The training data includes data from several sources, as described below, which may be used to generate multiple training examples. Each training example can include (i) input data relating to a previous computational task, e.g., data specifying the task, size/complexity of the task, restrictions for solving the task, error tolerance, (ii) information relating to which device was used to solve the task, or (iii) metrics indicating a quality of the solution obtained using the device, e.g., a level of confidence in the solution, computational time taken to generate the solution, or computational costs incurred…”]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC CARDWELL/Primary Examiner, Art Unit 2139
Read full office action

Prosecution Timeline

May 22, 2023
Application Filed
Sep 16, 2025
Non-Final Rejection mailed — §102
Nov 03, 2025
Response Filed
Apr 23, 2026
Request for Continued Examination
May 20, 2026
Response after Non-Final Action
Sep 03, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12717484
INTERFACE LAYOUT FOR STACKED MEMORY ARCHITECTURES
2y 3m to grant Granted Aug 25, 2026
Patent 12717715
VIRTUAL INDEXING IN A MEMORY DEVICE
1y 7m to grant Granted Aug 25, 2026
Patent 12704970
MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM
2y 7m to grant Granted Aug 11, 2026
Patent 12675226
HOSTS AND OPERATION METHODS THEREOF, MEMORY SYSTEMS AND OPERATION METHODS THEREOF, AND ELECTRONIC APPARATUS
1y 9m to grant Granted Jul 07, 2026
Patent 12669961
COORDINATING ESTABLISHMENT OF SOURCE AND TARGET COPY RELATIONSHIPS ON PRIMARY AND SECONDARY SERVERS
3y 7m to grant Granted Jun 30, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+11.7%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month