DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed November 13, 2025 have been entered and considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 8-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al. (US 5459655 A), in view of Arai et al. (JP 2003142689 A).
Regarding claim 1, first embodiment of Mori et al. (hereby referred to as Mori et al. (Fig. 4A)) teaches:
A semiconductor device comprising:
a first conductive pattern [12a, Col. 6, Lines 17-32, Fig. 4A];
a second conductive pattern [14a, Col. 6, Lines 17-32, Fig. 4A];
a third conductive pattern [12b, Col. 6, Lines 11-64, Fig. 4A];
a fourth conductive pattern [14b, Col. 6, Lines 17-58, Fig. 4A];
a plurality of first semiconductor chips [31a, Col.6, Lines 25-32, Fig. 4A], each first semiconductor chip [31a, Fig. 4A] having
a front face,
a back face that is coupled to the first conductive pattern [12a, Fig. 4A], and
a switching device [S11-S14, S21-24, S31-34, Col. 4, Lines 38-41; Col. 5, Lines 24-41, Fig. 1] formed in said each first semiconductor chip [31a, Fig. 4A], the switching device [300 “IGBT”, Col. 8, Lines 30-63, Fig. 8] having a high-potential electrode [311, Col. 8, Lines 38-42, Fig. 8] at the back face and a low-potential electrode [312, Col. 8, Lines 38-44 Fig. 8] at the front face;
a plurality of second semiconductor chips [32a, Col. 6, Lines 25-32, Fig. 4A], each second semiconductor chip [32a, Fig. 4A] having
a front face,
a back face that is coupled to the first conductive pattern [12a, Fig. 4A], and
a diode device [D11-14, D21-24, D31-34, Col. 8, Lines 1-29, Fig. 1] formed in said each second semiconductor chip [32a, Col. 6, Lines 25-32, Fig. 4A], the diode device [200, Col. 8, Lines 30-67 to Col. 9, Lines 1-35, Fig. 9] having a cathode electrode [211, Col. 9, Lines 8-35, Fig. 9] at the back face thereof and an anode electrode [212, Col. 9, Lines 8-35, Fig. 9] at the front face thereof.
a plurality of second wires [Col. 6, Lines 25-32, Fig. 4A], respectively coupling the anode electrodes [212, Fig. 9] of the plurality of diode devices [32a, Fig. 4A] and the second conductive pattern [14a, Fig. 4A],
the plurality of first semiconductor chips [31a, Fig. 4A] and the plurality of second semiconductor chips [32a, Fig. 4A] are arranged on the first conductive pattern [12a, Fig. 4A] in two rows, that includes a first row and a second row, each row being in a first direction and including at least one of the plurality of first semiconductor chips [31a, Fig. 4A] and at least one of the plurality of second semiconductor chips [32a, Fig. 4A], the first direction being parallel to a predetermined side of the first conductive pattern [12a, Fig. 4A].
Mori et al. (Fig. 4A) does not teach:
a plurality of first wires, respectively coupling the low-potential electrodes of the plurality of switching devices and the second conductive pattern.
each of the plurality of second wires having a length substantially equal to a length of each of the plurality of first wires.
the plurality of first wires and the plurality of second wires are each in a second direction orthogonal to the first direction.
each of the plurality of first semiconductor chips in the first row has a control electrode that is connected, via a third wire, to the third conductive pattern,
each of the plurality of first semiconductor chips in the second row has a control electrode that is connected, via a fourth wire, to the fourth conductive pattern.
Another embodiment of Mori et al. (hereby referred to as Mori et al. (Fig. 10)) teaches:
a plurality of first wires [37, Col. 9, Lines 66-67 to Col. 10, Lines 1-5, Fig. 10], respectively coupling the low-potential electrodes [312, Fig. 8] of the plurality of switching devices [35, Fig. 10] and the second conductive pattern [31, Fig. 10].
each of the plurality of second wires having a length substantially equal to a length of each of the plurality of first wires. [Lengths, Col. 11, Lines 55-67 to Col. 12, Lines 1-19, Fig. 15]
the plurality of first wires and the plurality of second wires are each in a second direction orthogonal to the first direction. [Not specifically mentioned but can be seen in Fig. 10, 15, 18]
each of the plurality of first semiconductor chips [35, Col. 9, Lines 58-67 to Col. 10, Lines 1-5, Fig. 10-11] in the first row has a control electrode [35G, Fig. 10-11] that is connected, via a third wire [38, Fig. 10-11], to the third conductive pattern [33, Fig. 10-11],
each of the plurality of first semiconductor chips [35, Col. 9, Lines 58-67 to Col. 10, Lines 1-5, Fig. 10-11] in the second row has a control electrode [35E, Fig 10-11] that is connected, via a fourth wire [37, Fig. 10-11], to the fourth conductive pattern [31, Fig. 10-11].
See MPEP 2125(I) Drawings as Prior Art: “Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). However, the picture must show all the claimed structural features and how they are put together. Jockmus v. Leviton, 28 F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial. For instance, drawings in a design patent can anticipate or make obvious the claimed invention as can drawings in utility patents. When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as "enabled disclosures."
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Mori et al. (Fig. 10) into the teachings of Mori et al. (Fig. 4A) to include a plurality of first wires, respectively coupling the low-potential electrodes of the plurality of switching devices and the second conductive pattern, each of the plurality of second wires having a length substantially equal to a length of each of the plurality of first wires, the plurality of first wires and the plurality of second wires are each in a second direction orthogonal to the first direction, each of the plurality of first semiconductor chips in the first row has a control electrode that is connected, via a third wire, to the third conductive pattern, each of the plurality of first semiconductor chips in the second row has a control electrode that is connected, via a fourth wire, to the fourth conductive pattern, for the purpose of connecting features within the device, reducing or eliminating nonuniformity, distributing heat uniformly, equating inductances, improving symmetry and interconnectivity, increasing density and signal speed, and improving performance and efficiency. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts and MPEP 2144.04 (IV)(A) Changes in Size/Proportion.
Mori et al. (Fig. 4A) and Mori et al. (Fig. 10) do not teach:
In a plan view, the first and second conductive patterns are located between the third conductive pattern and the fourth conductive pattern.
Arai et al. teaches:
In a plan view, the first and second conductive patterns [P50, P60, paragraph [0103-0105], Fig. 8] are located between the third conductive pattern [P51, paragraph [0103-0105], Fig. 8] and the fourth conductive pattern [P61, paragraph [0103-0105],Fig. 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Arai et al. into the teachings of Mori et al. (Fig. 4A) and Mori et al. (Fig. 10) to include in a plan view, the first and second conductive patterns are located between the third conductive pattern and the fourth conductive pattern, for the purpose of connecting features within the device, reducing or eliminating nonuniformity, distributing heat uniformly, equating inductances, improving symmetry and interconnectivity, increasing density and signal speed, and improving performance and efficiency. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Regarding claim 2, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A) further teaches:
a same number of the first semiconductor chips [31a, Col. 6, Lines 25-32, Fig. 4A] are in each of the two rows, where said same number is a first number, and
a same number of the second semiconductor chips [32a, Col. 6, Lines 25-32, Fig. 4A] are in each of the two rows, where said same number is a second number.
Regarding claim 3, Mori et al. (Fig. 4A ), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 2.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. disclose the above claimed subject matter.
However, Mori et al. (Fig. 4A) and Mori et al. (Fig. 10) do not teach:
the first number is equal to the second number.
Arai et al. teaches:
the first number is equal to the second number. [Fig. 14]
Although Arai et al. does not specifically mention the first number is equal to the second number; it can be seen in Fig. 14 that the semiconductor device [80, Fig. 14] contains two first semiconductor chips [T1, T3, paragraph [0011-0012], Fig. 14], and two second semiconductor chips [D1, D4, paragraph [0011-0012], Fig. 14], in the first row. Two first semiconductor chips [T2, T3, paragraph [0011-0012], Fig. 14], and two second semiconductor chips [D2, D3, paragraph [0011-0012], Fig. 14] in the second row.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Arai et al. into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include the first number is equal to the second number, for the purpose of increasing uniformity and simplicity, improving yield and customization, and improving cost efficiency and time to market. MPEP 2144.04(VI)(B) Duplication of Parts.
Regarding claim 5, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A) further teaches:
each of the first semiconductor chips [31a, Fig. 4A] has a body diode [200, Fig. 9] formed therein, the body diode [200, Fig. 9] having
a cathode electrode [211, Col. 9, Lines 8-35, Fig. 9] thereof at the back face of said each first semiconductor chip [31a, Fig. 4A], and
an anode electrode [212, Col. 9, Lines 8-35, Fig. 9] thereof at the front face of said each first semiconductor chip [31a, Fig. 4A].
Regarding claim 6, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. disclose the above claimed subject matter.
However, Mori et al. (Fig. 4A) and Arai et al. do not teach:
a difference in length between each of the plurality of first wires and each of the plurality of second wires is within a range of manufacturing variations.
Mori et al. (Fig. 10) teaches:
a difference in length between each of the plurality of first wires and each of the plurality of second wires is within a range of manufacturing variations. [Lengths, Col. 11, Lines 55-67 to Col. 12, Lines 1-19, Fig. 15]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Mori et al. (Fig. 10) into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include a difference in length between each of the plurality of first wires and each of the plurality of second wires is within a range of manufacturing variations, for the purpose of improving inductance uniformity. See also, MPEP 2144.04 (IV)(A) Changes in Size/Proportion.
Regarding claim 8, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. disclose the above claimed subject matter.
However, Mori et al. (Fig. 4A) and Mori et al. (Fig. 10) do not teach:
the first and second semiconductor chips are alternately arranged in each of the two rows.
Arai et al. teaches:
the first [T1, T2, T3, T4, paragraph [0011-0012], Fig. 14] and second [D1, D2, D3, D4, paragraph [0011-0012], Fig. 14] semiconductor chips are alternately arranged in each of the two rows.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Arai et al. into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include the first and second semiconductor chips are alternately arranged in each of the two rows, for the purpose of achieving proper rotationally symmetrical positional relationship. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Regarding claim 9, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 8.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. disclose the above claimed subject matter.
However, Mori et al. (Fig. 4A) and Mori et al. (Fig. 10) do not teach:
one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chip are respectively arranged in the two rows on a same end side thereof.
Arai et al. teaches:
one of the plurality of first semiconductor chips [T1-T4, Fig. 14] and one of the plurality of second semiconductor chip [D1-D4, Fig. 14] are respectively arranged in the two rows on a same end side thereof.
Although not specifically mentioned, it can be seen in Fig. 14 that one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chip are respectively arranged in the two rows on a same end side thereof.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Arai et al. into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chip are respectively arranged in the two rows on a same end side thereof, for the purpose of increasing density, reducing size, reducing wire lengths therefore reducing inductance. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Regarding claim 10, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A) further teaches:
the second conductive pattern [14a, Col. 6, Lines 23-25, Fig. 4A] has a rectangular shape, and
the first conductive pattern [12a, Col. 6, Lines 17-25, Fig. 4A] is so shaped as to sandwich the second conductive pattern [14a, Fig. 4A] from two opposite sides along the first direction of the second conductive pattern [14a, Fig. 4A], and
the plurality of first semiconductor chips [31a, Fig. 4A] and the plurality of second semiconductor chips [32a, Fig. 4A] are arranged on the first conductive pattern [12a, Fig. 4A] in the two rows respectively closer to the two opposite sides.
Regarding claim 11, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 10.
Mori et al. (Fig. 4A) further teaches:
the first conductive pattern [12a, Col. 6, Lines 17-25, Fig. 4A] has a U shape in a top view of the semiconductor device.
Regarding claim 12, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. disclose the above claimed subject matter.
However, Mori et al. (Fig. 4A) and Mori et al. (Fig. 10) do not teach:
the first conductive pattern has a rectangular shape, and
the second conductive pattern is so shaped as to sandwich the first conductive pattern from two opposite sides along the first direction of the first conductive pattern, and
the plurality of first semiconductor chips and the plurality of second semiconductor chips are arranged on the first conductive pattern in the two rows respectively closer to the two opposite sides.
Arai et al. teaches:
the first conductive pattern [P10, paragraph [0010], Fig. 14] has a rectangular shape, and
the second conductive pattern [P20, paragraph [0010], Fig. 14] is so shaped as to sandwich the first conductive pattern [P10, Fig. 14] from two opposite sides along the first direction of the first conductive pattern [P10, Fig. 14], and
the plurality of first semiconductor chips [T1-T4, paragraph [0011-0012], Fig. 14] and the plurality of second semiconductor chips [D1-D4, paragraph [011-012], Fig. 14] are arranged on the first conductive pattern [P10, Fig. 14] in the two rows respectively closer to the two opposite sides.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Arai et al. into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include the first conductive pattern has a rectangular shape, and the second conductive pattern is so shaped as to sandwich the first conductive pattern from two opposite sides along the first direction of the first conductive pattern, and the plurality of first semiconductor chips and the plurality of second semiconductor chips are arranged on the first conductive pattern in the two rows respectively closer to the two opposite sides, for the purpose of increasing density, manufacturing a smaller device, improving connectivity between features of the device, improving length of wires for desired inductance, and improving rotationally symmetrical positional relationship. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts and MPEP 2144.04 (IV)(B) Changes in Shape.
Regarding claim 13, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 12.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. disclose the above claimed subject matter.
However, Mori et al. (Fig. 4A) and Mori et al. (Fig. 10) do not teach:
the second conductive pattern has a U shape in a top view of the semiconductor device.
Arai et al. teaches:
the second conductive pattern [P20, paragraph [0010], Fig. 14] has a U shape in a top view of the semiconductor device.
Arai et al. cites a second conductive pattern [P20] as an “L-shape”, but in Fig. 14 it can be seen that the second conductive pattern [P20] contains a leg extending from both ends of the second conductive pattern, resulting in a shape resembling a “U”, more than an “L”.
It should also be noted that Mori et al. teaches a conductive pattern [12a, 12b, 13a, 13b “electrode plate”, Col. 6, Lines 17-23, Fig. 4A] has a U-shape.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Arai et al. into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include the second conductive pattern has a U shape in a top view of the semiconductor device, for the purpose of surrounding the first conductive pattern, simplifying connections between features, and improving length of wires for desired inductance. See also, MPEP 2144.04(IV)(B) Changes in Shape.
Regarding claim 15, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A) further teaches:
the third conductive pattern [12b, Col. 6, Lines 11-64, Fig. 4A] is coupled to the second conductive pattern [14a, Fig. 4A]; and
the semiconductor device further includes:
a third semiconductor chip [31b, Col. 6, Lines 25-32, Fig. 4A] having another switching device [S11-S14, S21-24, S31-34, Col. 4, Lines 38-41; Col. 5, Lines 24-41, Fig. 1] formed therein, the third semiconductor chip [31b, Fig. 4A] being arranged in the third conductive pattern [12b, Fig. 4A],
a fourth semiconductor chip [32b, Col. 6, Lines 25-32, Fig. 4A] having another diode device [200, Fig. 9] formed therein, the fourth semiconductor chip [32b, Fig. 4A] being arranged in the third conductive pattern [12b, Fig. 4A].
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. disclose the above claimed subject matter.
However, Mori et al. (Fig. 4A) and Arai et al. do not teach:
another wire coupling a low-potential electrode of said another switching device in the third semiconductor chip and the fourth conductive pattern, and
yet another wire coupling an anode electrode of said another diode device in the fourth semiconductor chip and the fourth conductive pattern, the yet another wire having a length substantially equal to a length of the another wire.
Mori et al. (Fig. 10) teaches:
another wire [37, Col. 9, Lines 66-67 to Col. 10, Lines 1-5, Fig. 10] coupling a low-potential electrode [312/35E, Fig. 8/11] of said another switching device [35, Fig. 10] in the third semiconductor chip and the fourth conductive pattern [31, Fig. 10], and
yet another wire coupling [39, Col. 9, Lines 66-67 to Col. 10, Lines 1-5, Fig. 10] an anode electrode [212/36A, Fig. 9/11] of said another diode device [36, Col. 9, Lines 55-67 to Col. 10, Lines 1-5, Fig. 10] in the fourth semiconductor chip and the fourth conductive pattern [31, Fig. 10], the yet another wire having a length substantially equal to a length of the another wire. [Lengths, Col. 11, Lines 55-67 to Col. 12, Lines 1-19, Fig. 15]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Mori et al. (Fig. 10) into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include another wire coupling a low-potential electrode of said another switching device in the third semiconductor chip and the fourth conductive pattern, and yet another wire coupling an anode electrode of said another diode device in the fourth semiconductor chip and the fourth conductive pattern, the yet another wire having a length substantially equal to a length of the another wire, for the purpose of connecting features within the device, achieving desired inductances, reducing or eliminating nonuniformity, and distributing heat uniformly. See also, MPEP 2144.04(IV)(B) Changes in Shape and MPEP 2144.04(VI)(C) Rearrangement of Parts.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al. (US 5459655 A), in view of Arai et al. (JP 2003142689 A) as applied to claim 1 above, and further in view of Michikoshi et al. (US 20140001481 A1).
Regarding claim 4, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. do not teach:
each of the switching devices is a metal-oxide-semiconductor field-effect transistor (MOSFET), wherein
the high-potential electrode is a drain electrode, and
the low-potential electrode is a source electrode.
Michikoshi et al. teaches:
each of the switching devices [14a-14d, paragraph [0029], Fig. 1] is a metal-oxide-semiconductor field-effect transistor (MOSFET), wherein
the high-potential electrode is a drain electrode [paragraph [0030-0031] Fig. 1], and
the low-potential electrode is a source electrode [SP, paragraph [0030-0031], Fig. 1].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Michikoshi et al. into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include each of the switching devices is a metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the high-potential electrode is a drain electrode, and the low-potential electrode is a source electrode, for the purpose of improving power consumption, versatility, switching speed and scalability; and improving energy efficiency, creating proper contacts leading to improved performance.
Regarding claim 14, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 1.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. do not teach:
the first semiconductor chip, or the second semiconductor chip, or both, is a SiC substrate chip.
Michikoshi et al. teaches:
the first semiconductor chip, or the second semiconductor chip, or both [14a-14d, paragraph [0029], Fig. 1], is a SiC substrate chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Michikoshi et al. into the teachings of Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. to include the first semiconductor chip, or the second semiconductor chip, or both, is a SiC substrate chip, for the purpose of widening bandgap, operating at higher voltages, frequencies and temperatures, improving reliability, energy efficiency, and power density, and reducing cost.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Mori et al. (US 5459655 A), in view of Arai et al. (JP 2003142689 A) as applied to claim 6 above, and further in view of Boulay et al. (US 8669638 B2).
Regarding claim 7, Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. teach the semiconductor device according to claim 6.
Mori et al. (Fig. 4A), Mori et al. (Fig. 10) and Arai et al. do not teach:
the manufacturing variations are smaller in the first direction than in the second direction.
Boulay et al. teaches:
the manufacturing variations are smaller in the first direction than in the second direction. [Col. 1, Lines 36-53; Col. 4, Lines 11-21, Fig. 1]
Boulay et al. discloses the claimed limitation except for specifically mentioning smaller variations in the first direction, than in the second direction. However, it would have been obvious to a person of ordinary skill in the art before the effective filing day of the instant invention to include smaller variations in the first direction, than in the second direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine optimization. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05 (II)(A).
Response to Arguments
Applicant's arguments filed November 13, 2025 have been fully considered but they are not persuasive. Applicant argues on pages 1-4, in remarks filed November 13, 2025 that primary reference Mori et al. (US 5459655 A) does not teach limitations of independent claim 1. Examiner disagrees with Applicant; In the office action dated August 22, 2025, Examiner provided column and line locations for all limitations of independent claim 1. “A plurality of first wires [37, Col. 9, Lines 66-67 to Col. 10, Lines 1-5, Fig. 10], respectively coupling the low-potential electrodes [312, Fig. 8] of the plurality of switching devices [35, Fig. 10] and the second conductive pattern [31, Fig. 10].” and “a plurality of second wires [Col. 6, Lines 25-32, Fig. 4A], respectively coupling the anode electrodes [212, Fig. 9] of the plurality of diode devices [32a, Fig. 4A] and the second conductive pattern [14a, Fig. 4A].” The limitations of independent claim 1 were overcome by a combination of Mori et al. (US 5459655 A) Fig. 4A and Fig. 10. The reason for combining being to connect features within the device, reducing or eliminating nonuniformity, distributing heat uniformly, equating inductances, improving symmetry and interconnectivity, increasing density and signal speed, and improving performance and efficiency.
Applicant argues on page 4, in remarks filed November 13, 2025 that the prior art of record does not teach the amended limitations of independent claim 1. Examiner disagrees with Applicant. The amended limitations of independent claim 1 can be overcome by new considerations of primary reference Mori et al. (US 5459655 A), and secondary reference Arai et al. (JP 2003142689 A).
Applicant argues on pages 4-5, in remarks filed November 13, 2025 that dependent claims 2-15 should be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
In summary, primary reference Mori et al. (US 5459655 A) teaches the claimed limitations of independent claim 1. The amendments to independent claim 1 can be overcome by primary reference Mori et al. (US 5459655 A), and secondary reference Arai et al. (JP 2003142689 A). All claims directly or indirectly dependent on independent claim 1 are also rejected for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID MICHAEL HELBERG whose telephone number is (571)270-1422. The examiner can normally be reached Mon.-Fri. 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.M.H./Examiner, Art Unit 2815 02/06/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815