Office Action Predictor
Last updated: April 15, 2026
Application No. 18/321,682

OVER VOLTAGE PROTECTION CIRCUIT AND POWER AMPLIFIER INCLUDING THE SAME

Non-Final OA §102
Filed
May 22, 2023
Examiner
CHOE, HENRY
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., LTD.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
1y 10m
To Grant
91%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
1238 granted / 1339 resolved
+24.5% vs TC avg
Minimal -2% lift
Without
With
+-1.5%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
29 currently pending
Career history
1368
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
37.3%
-2.7% vs TC avg
§102
47.2%
+7.2% vs TC avg
§112
3.8%
-36.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1339 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Independent Claims 1, 11 and 18 are the one of the broadest Independent claims I ever seen. Please amend the claims in reasonable way. Thank you, Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 4, 6, 7, 11 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Choi (Fig. 1); 10,911,002]. Regarding claims 1, 11 and 18, Choi discloses an amplifier circuit comprising an over voltage protection circuit (400, 500, 210, 220, R3), a power amplifier (Fig. 1) amplifying an input RF signal (IN) by receiving a bias current (Ibias1) from a bias circuit (210, R3) and the circuit comprising an input signal detector (400) detecting a magnitude of the input RF signal (IN), and a first transistor (Q1) receiving the magnitude of the input RF signal (IN) through a control terminal (base terminal of Q1) thereof and turned on based on the magnitude of the input RF signal (IN) to sink the current from a first node (11) of the bias circuit (210, R3). Regarding claim 3, wherein the bias circuit (210, R3) comprises a second transistor (Q21) supplying the bias current (Ibias1), and the first node (11) is a control terminal (base terminal of Q21) of the second transistor (Q21). Regarding claim 4, wherein the input signal detector (400) comprises a first resistor (resistor in 400) adjusting a turn on voltage level of the first transistor (Q1) based on the magnitude of the input RF signal (IN). Regarding claims 6 and 17, wherein the magnitude of the input RF signal (IN) corresponds to an envelope of the input RF signal (IN). Regarding claim 7, wherein the power amplifier (Fig. 1) comprises a power transistor (Q1, Q2) amplifying and outputting a voltage of the input RF signal (IN), and the bias circuit (210, R3) supplies the bias current (Ibias1) to the power transistor (Q1). Regarding claim 19, Choi further comprising one or more bias circuits (210, 220, R3) configured to supply the one or more bias currents (Ibias1, Ibias2) and wherein the over voltage protection circuit (400, 500, 210, 220, R3) is further configured to sink the bias current (Ibias1) from the one or more bias circuits (210, 220, R3) to decrease the at least one (Ibias1) of the one or more bias currents (Ibias1, Ibias2). Regarding claim 20, wherein the over voltage protection circuit (400, 500, 210, 220, R3) comprises a sink transistor (Q21) configured to turn on to decrease the at least one (Ibias1) of the one or more bias currents (Ibias1, Ibias2), and a resistor (R3) configured to adjust a turn on voltage of the sink transistor (Q21). Allowable Subject Matter Claims 2, 5, 8-10 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (703)774-4614. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HENRY CHOE/ Primary Examiner, Art Unit 2843 #2915
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Prosecution Timeline

May 22, 2023
Application Filed
Sep 15, 2025
Non-Final Rejection — §102
Apr 09, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
91%
With Interview (-1.5%)
1y 10m
Median Time to Grant
Low
PTA Risk
Based on 1339 resolved cases by this examiner. Grant probability derived from career allow rate.

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