DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 23rd, 2023, is being considered by the Examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “16” has been used to designate both p-type regions and n-type regions. More specifically, the instant specification appears to identify n-type regions as reference character “18” ([0028]), but the instant figures show both the n-type and p-type regions as reference character “16” (see Fig. 1). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 4 and 5 are objected to because of the following informalities:
(a) Regarding Claim 4, line 1, “wherein the wide rail region” should read, “wherein the primary wide rail region”.
(b) Regarding Claim 5, line 2, “connected by a transistor to provide supply power from one narrow rail region to an adjacent other narrow rail region”, should read, “connected by a transistor to provide power supply from one narrow rail region to an adjacent other narrow rail region”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "constructing a plurality of adjacent narrow rail regions, wherein at least one of the adjacent narrow rail regions is isolated from the primary wide rail region and wherein the primary rail is contiguous only with the second secondary rail" in lines 4-6 of said claim. There is insufficient antecedent basis for this limitation in the claim. More specifically, regarding the terms “the primary rail” and “the second secondary rail”. Said terms were previously introduced in independent claim 13; however, they were not introduced in independent Claim 19. When “the primary rail” was stated, was applicant referring to “the primary wide rail region” or did they intend on introducing “the primary rail”. With regard to “the second secondary rail”, was applicant referring to the at least one of the adjacent narrow rail regions or intending to introduce the first and second secondary rails. For the purposes of examination, the Examiner will interpret “the primary rail” as “the primary wide rail region” and “the second secondary rail” as “the at least one of the adjacent narrow rail regions”.
Claim 20 recites the limitation “wherein the primary rail has a width between 120 nm and 250 nm, and each of the first and second secondary rails has a width between 50 nm and 120 nm” in lines 1-3 of said claim. There is insufficient antecedent basis for this limitation in the claim. More specifically, regarding the terms “the primary rail” and “the first and second secondary rails”. For the purposes of examination, as applied to Claim 19 above, Examiner will interpret “the primary rail” as “the primary wide rail region” and “the first and second secondary rails” as “the plurality of adjacent narrow rail regions”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-9, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumoto, et al. (US 20210233858 A1; hereinafter referred to as Matsumoto).
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Regarding Claim 1, Matsumoto discloses a semiconductor structure (semiconductor device 500, [0045], Fig. 7) comprising:
a plurality of backside supply rails (conductive structures 512 and 560, [0045], Fig. 7; conductive structures 512 and 560 provide backside power and signal to a device meaning they are analogous to backside supply rails);
a primary wide rail region (see Annotated Matsumoto Fig. 7 above); and
a plurality of adjacent narrow rail regions, wherein at least one of the adjacent narrow rail regions is isolated from the primary wide rail region (see Annotated Matsumoto Fig. 7 above).
Regarding Claim 2, Matsumoto discloses the semiconductor structure of claim 1, wherein the primary wide rail region and the at least one of the adjacent narrow rail regions are contiguous (see Annotated Matsumoto Fig. 7 above).
Regarding Claim 3, Matsumoto discloses the semiconductor structure of claim 1, wherein a width of two adjacent narrow rail regions is equal to a width of the primary wide rail region ([0045], Fig. 7).
Regarding Claim 7, Matsumoto discloses the semiconductor structure of claim 1, wherein a supply voltage connection for each narrow rail region is provided by a via connected to the primary wide rail region (vias 602, [0047], Fig. 8).
Regarding Claim 8, Matsumoto discloses the semiconductor structure of claim 1, wherein the primary wide rail region is isolated from an adjacent narrow rail region of the plurality of adjacent narrow rail regions by a cut (cuts 520, [0045], Fig. 7).
Regarding Claim 9, Matsumoto discloses the semiconductor structure of claim 1, wherein the plurality of adjacent narrow rail regions are isolated by a lateral cut (Fig. 7).
Regarding Claim 19, Matsumoto discloses a method for constructing a semiconductor structure, the method comprising:
constructing a plurality of backside supply rails (conductive structures 512 and 560, [0045], Fig. 7; conductive structures 512 and 560 provide backside power and signal to a device);
constructing a primary wide rail region (see Annotated Matsumoto Fig. 7 above); and
constructing a plurality of adjacent narrow rail regions, wherein at least one of the adjacent narrow rail regions is isolated from the primary wide rail region and wherein the primary rail [region] is contiguous only with the second secondary rail [the at least one of the adjacent narrow rail regions] (see Annotated Matsumoto Fig. 7 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a) Determining the scope and contents of the prior art.
b) Ascertaining the differences between the prior art and the claims at issue.
c) Resolving the level of ordinary skill in the pertinent art.
d) Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4-5 and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto as applied to claims 1-3, 7-9, and 19 above, and further in view of Chou, et al. (US 20230009640 A1; hereinafter referred to as Chou).
Regarding Claim 4, Matsumoto discloses the semiconductor structure of claim 1.
Matsumoto does not disclose wherein the wide rail region and the plurality of adjacent narrow rail regions are at N-N and P-P boundaries.
However, in analogous art, Chou discloses a semiconductor structure wherein a plurality of adjacent rail regions (backside power rails 116a, 116b, and 116c, [0041], Fig. 1B) are at N-N and P-P boundaries ([0041], Fig. 1B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the backside rail structure as disclosed by Matsumoto by placing the rail regions at N-N and P-P boundaries as disclosed by Chou. One would be motivated to do so to allow for the formation of source/drain regions and conduction regions in the N-N and P-P regions by providing power and/or signal to said regions through the backside rail structure which can lead to increased device performance and more efficient device structure (Chou: [0041-0042]).
Regarding Claim 5, Matsumoto discloses the semiconductor structure of claim 1.
Matsumoto does not disclose wherein the plurality of adjacent narrow rail regions are connected by a transistor to provide supply power from one narrow rail region to an adjacent other narrow rail region.
However, in analogous art, Chou discloses a semiconductor structure wherein adjacent rail regions are connected by a transistor to provide supply power from one rail region to an adjacent other narrow rail region ([0019]; “the header circuitry 112 includes switching devices, such as a plurality of transistors, that are used to transmit or receive electrical signals to and from the semiconductor device layer 110, such as to turn on and turn off the circuitry (e.g., transistors, etc.) of the semiconductor device layer 110”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the rail structure as disclosed in Matsumoto such that the adjacent narrow rail regions are connected by a transistor as disclosed in Chou. One would be motivated to do so as the introduction of transistor devices (e.g., switching devices) leads to reduced stand-by or leakage power for the semiconductor device as the transistors are able to transmit or receive signals as to when the rails should be operational (Chou: [0019]).
Regarding Claim 13, Matsumoto discloses a semiconductor structure comprising:
a primary rail (see Annotated Matsumoto Fig. 7 above);
a first secondary rail and a second secondary rail, wherein the second secondary rail is isolated from the primary rail (see Annotated Matsumoto Fig. 7 above).
Matsumoto fails to disclose a transistor connecting the first secondary rail to the second secondary rail to supply power therebetween.
However, in analogous art, Chou discloses a semiconductor structure wherein adjacent rail regions are connected by a transistor to provide supply power from one rail region to an adjacent other narrow rail region ([0019]; “the header circuitry 112 includes switching devices, such as a plurality of transistors, that are used to transmit or receive electrical signals to and from the semiconductor device layer 110, such as to turn on and turn off the circuitry (e.g., transistors, etc.) of the semiconductor device layer 110”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the rail structure as disclosed in Matsumoto such that the adjacent narrow rail regions are connected by a transistor as disclosed in Chou. One would be motivated to do so as the introduction of transistor devices (e.g., switching devices) leads to reduced stand-by or leakage power for the semiconductor device as the transistors are able to transmit or receive signals as to when the rails should be operational (Chou: [0019]).
Regarding Claim 14, Matsumoto/Chou discloses the semiconductor structure of claim 13, wherein the primary rail is contiguous only with the second secondary rail (see Annotated Matsumoto Fig. 7 above).
Regarding Claim 15, Matsumoto/Chou discloses the semiconductor structure of claim 13, wherein a width of the first and second secondary rails is equal to a width of the primary rail (Matsumoto: [0045], Fig. 7).
Regarding Claim 16, Matsumoto/Chou discloses the semiconductor structure of claim 13, wherein a supply voltage connection for the first and second secondary rails is provided by a via connected to the primary rail (Matsumoto: vias 602, [0047], Fig. 8).
Regarding Claim 17, Matsumoto/Chou discloses the semiconductor structure of claim 13, wherein the first secondary rail is isolated from the second secondary rail by a lateral cut (Matsumoto: Fig. 7).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto as applied to claims 1-3, 7-9, and 19 above, and further in view of Liu (US 20220359492 A1; hereinafter referred to as Liu).
Regarding Claim 6, Matsumoto discloses the semiconductor structure of claim 1.
Matsumoto fails to explicitly disclose wherein the plurality of adjacent narrow rail regions have a same voltage.
However, in analogous art, Liu discloses a semiconductor structure wherein the plurality of adjacent narrow rail regions (backside metal rails 430, [0028], Fig. 4) have a same voltage ([0030]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to have adjacent narrow rail regions as disclosed by Matsumoto have a same voltage across as disclosed by Liu. One would be motivated to do so as maintaining a same voltage across the narrow rail regions leads to improved power efficiency (Liu: [0032]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto as applied to claims 1-3, 7-9, and 19 above, and further in view of Xie, et al. (US 20230132353 A1; hereinafter referred to as Xie).
Regarding Claim 10, Matsumoto discloses the semiconductor structure of claim 1.
Matsumoto fails to explicitly disclose wherein the primary wide rail region has a width between 120 nm and 250 nm.
However, in analogous art, Xie discloses a backside rail structure wherein the primary wide rail region having a width between 120 nm and 250 nm ([0026]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the width of the primary wide rail region of Matsumoto to be in the overlapping range of Xie as it would merely result in an optimization of a result effective variable. The width of the primary wide rail region is a result effective variable as one would have chosen the width of the primary wide rail region by balancing the need for reducing device size and, more specifically, rail size to increase compactness and also reduce resistance generated by the rail with the need to retain the backside power rails function. One skilled in the art would have been motivated to produce a primary wide rail region in the claimed width range by balancing the desired effectiveness of reducing device size and resistance while maintaining function. Further, while the instant specification does disclose the claimed range of between 120 nm and 250 nm ([0053, 0060]), the specification is silent as to why this range is critical to the claimed invention.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto as applied to claims 1-3, 7-9, and 19 above, and further in view of Vishwanath, et al. (US 20210167066 A1; hereinafter referred to as Vishwanath).
Regarding Claim 11, Matsumoto discloses the semiconductor structure of claim 1.
Matsumoto does not disclose wherein each narrow rail region of the plurality of adjacent narrow rail regions has a width between 50 nm and 120 nm.
However, in analogous art, Vishwanath discloses a rail structure wherein each narrow rail region of the plurality of adjacent narrow rail regions (shared power rails, [0003]) has a width between 50 nm and 120 nm ([0003], “approximately 50 nm or larger”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the width of the each narrow rail region of the plurality of adjacent narrow rail regions of Matsumoto to be in the overlapping range of Vishwanath as it would merely result in an optimization of a result effective variable. The width of the each narrow rail region of the plurality of adjacent narrow rail regions is a result effective variable as one would have chosen the width of the each narrow rail region of the plurality of adjacent narrow rail regions by balancing the need for reducing device size and, more specifically, rail size to increase compactness and also reduce resistance and IR drop generated by the rail with the need to retain the backside power rails function. One skilled in the art would have been motivated to produce a narrow rail region of the plurality of adjacent narrow rail regions in the claimed width range by balancing the desired effectiveness of reducing device size and resistance/IR drop while maintaining function. Further, while the instant specification does disclose the claimed range of between 50 nm to 120 nm ([0053, 0060]), the specification is silent as to why this range is critical to the claimed invention.
Regarding Claim 12, Matsumoto/Vishwanath discloses the semiconductor structure of claim 11.
The combination of Matsumoto/Vishwanath fails to explicitly disclose wherein a gap region between the plurality of adjacent narrow rail regions has a width between 10 nm and 20 nm.
However, Matsumoto does disclose that the plurality of adjacent narrow regions are offset from one another in that the cuts performed are offset by a proportion of the size of the device ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the gap region between the plurality of adjacent narrow regions as disclosed by Matsumoto/Vishwanath as Matsumoto teaches the gap between the plurality of adjacent narrow rail regions is a result effective variable. One would choose the width of the gap region between the plurality of adjacent narrow rail regions by balancing the need for reducing device and narrow rail region width in order to increase device compactness and allow for reduced IR drop generated within the rail. Further, while the instant application does disclose the claimed gap width range of between 10 nm and 20 nm ([0060]), the specification is silent as to why this range is critical to the claimed invention.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto/Chou as applied to claim 13 above, and further in view of Xie and Vishwanath.
Regarding Claim 18, Matsumoto/Chou discloses the semiconductor structure of claim 13.
Matsumoto/Chou do not disclose wherein the primary rail has a width between 120 nm and 250 nm, and each of the first and second secondary rails has a width between 50 nm and 120 nm.
However, in analogous art, Xie discloses a backside rail structure wherein the primary rail having a width between 120 nm and 250 nm ([0026]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the width of the primary rail of Matsumoto to be in the overlapping range of Xie as it would merely result in an optimization of a result effective variable. The width of the primary rail is a result effective variable as one would have chosen the width of the primary rail by balancing the need for reducing device size and, more specifically, rail size to increase compactness and also reduce resistance generated by the rail with the need to retain the backside power rails function. One skilled in the art would have been motivated to produce a primary wide rail region in the claimed width range by balancing the desired effectiveness of reducing device size and resistance while maintaining function. Further, while the instant specification does disclose the claimed range of between 120 nm and 250 nm ([0053, 0060]), the specification is silent as to why this range is critical to the claimed invention.
The combination of Matsumoto/Chou/Xie are also silent on each of the first and second secondary rails having a width between 50 nm and 120 nm.
However, in analogous art, Vishwanath discloses a rail structure wherein the first and second secondary rails (shared power rails, [0003]) having a width between 50 nm and 120 nm ([0003], “approximately 50 nm or larger”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the width of the each narrow rail region of the plurality of adjacent narrow rail regions of Matsumoto/Chou/Xie to be in the overlapping range of Vishwanath as it would merely result in an optimization of a result effective variable. The width of the first and second secondary rails is a result effective variable as one would have chosen the width of the first and second secondary rails by balancing the need for reducing device size and, more specifically, rail size to increase compactness and also reduce resistance and IR drop generated by the rail with the need to retain the backside power rails function. One skilled in the art would have been motivated to produce the first and second secondary rails in the claimed width range by balancing the desired effectiveness of reducing device size and resistance/IR drop while maintaining function. Further, while the instant specification does disclose the claimed range of between 50 nm to 120 nm ([0053, 0060]), the specification is silent as to why this range is critical to the claimed invention.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto as applied to claims 1-3, 7-9, and 19 above, and further in view of Xie and Vishwanath.
Regarding Claim 20, Matsumoto discloses the method of claim 19.
Matsumoto does not disclose wherein the primary [wide] rail [region] has a width between 120 nm and 250 nm, and each of the first and second secondary rails [plurality of adjacent narrow rail regions] has a width between 50 nm and 120 nm.
However, in analogous art, Xie discloses a backside rail structure wherein the primary wide rail region having a width between 120 nm and 250 nm ([0026]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the width of the primary wide rail region of Matsumoto to be in the overlapping range of Xie as it would merely result in an optimization of a result effective variable. The width of the primary wide rail region is a result effective variable as one would have chosen the width of the primary wide rail region by balancing the need for reducing device size and, more specifically, rail size to increase compactness and also reduce resistance generated by the rail with the need to retain the backside power rails function. One skilled in the art would have been motivated to produce a primary wide rail region in the claimed width range by balancing the desired effectiveness of reducing device size and resistance while maintaining function. Further, while the instant specification does disclose the claimed range of between 120 nm and 250 nm ([0053, 0060]), the specification is silent as to why this range is critical to the claimed invention.
The combination of Matsumoto/Xie are also silent on each of the first and second secondary rails having a width between 50 nm and 120 nm.
However, in analogous art, Vishwanath discloses a rail structure wherein the first and second secondary rails (shared power rails, [0003]) having a width between 50 nm and 120 nm ([0003], “approximately 50 nm or larger”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the width of the each narrow rail region of the plurality of adjacent narrow rail regions of Matsumoto to be in the overlapping range of Vishwanath as it would merely result in an optimization of a result effective variable. The width of the each narrow rail region of the plurality of adjacent narrow rail regions is a result effective variable as one would have chosen the width of the each narrow rail region of the plurality of adjacent narrow rail regions by balancing the need for reducing device size and, more specifically, rail size to increase compactness and also reduce resistance and IR drop generated by the rail with the need to retain the backside power rails function. One skilled in the art would have been motivated to produce a narrow rail region of the plurality of adjacent narrow rail regions in the claimed width range by balancing the desired effectiveness of reducing device size and resistance/IR drop while maintaining function. Further, while the instant specification does disclose the claimed range of between 50 nm to 120 nm ([0053, 0060]), the specification is silent as to why this range is critical to the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Lee, et al. (US 20240429168 A1); discloses a backside rail structure with a plurality of rails.
(b) Chen, et al. (US 20220084561 A1); discloses a backside rail structure with different lengths/widths and with transistors connecting rails.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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