DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, Species I, FIGs. 1-4, claims 1-3 and 6 in the reply filed on 04/27/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 4, 5, and 7-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and or Species, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 05/24/2022. It is noted, however, that applicant has not filed a certified copy of the 2022-084784 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/23/2023 and 06/28/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings received on 05/23/2023 are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuki et al. (U.S. PG. Pub. No. 2022/0068554 A1, hereinafter “Matsuki”) in view of Yosui et al. (U.S. PG. Pub. No. 2015/0296621 A1, hereinafter “Yosui”).
With respect to claim 1, Matsuki teaches an electronic component (Fig. 16) comprising:
a glass substrate 10;
an outer surface conductor 11 that is in contact with an outer surface (upper surface) of the glass substrate; and
a protective film 14 that covers the outer surface of the glass substrate and the outer surface conductor and is in contact with the outer surface of the glass substrate and the outer surface conductor,
wherein when the glass substrate has first surface roughness Ra1 at an interface S2 between the glass substrate and the outer surface conductor, the glass substrate has second surface roughness Ra2 at an interface S1 between the glass substrate and the protective film, and the outer surface conductor has third surface roughness Ra3 at an interface S3 (annotated Fig. 16) between the outer surface conductor and the protective film, Ra1<Ra2 is satisfied (para. [0141]).
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Matsuki does not expressly teach Ra1<Ra3<Ra2 is satisfied.
Yosui teaches an electronic component (FIG. 5A),
wherein Ra1<Ra3 is satisfied (para. [0057]). Surface roughness of first principal surface 91 is greater than surface roughness of second surface 93.
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The incorporation of the surface roughness teaching of Yosui to the electronic component of Matsuki would result in “Ra1<Ra3<Ra2 is satisfied” as claimed. Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate the surface roughness as taught by Yousi to the electronic component of Matsuki to improve the mechanical adhesion among the outer glass substrate, the outer surface conductor and the protective film.
With respect to claim 2, Matsuki in view of Yosui teaches the electronic component according to claim 1, wherein (Ra3−Ra1)<(Ra2−Ra3) is satisfied (Matsuki, para. [0141] and Yosui, para. [0057]). The combination of the Matsuki and Yosui would have the claimed limitation.
With respect to claims 3 and 6, Matsuki in view of Yosui teaches the electronic component according to claims 1 and 2, respectively, further comprising:
a first through conductor (front or back through wire 13) and a second through conductor (the other of front or back through wire 13) that penetrate the glass substrate, wherein
the outer surface includes a bottom surface (lower surface), which is one main surface of the glass substrate, and a top surface (upper surface) located on a back side of the bottom surface,
the outer surface conductor includes a bottom surface conductor (lower surface conductor 11) that is in contact with the bottom surface and a top surface (upper surface conductor 11) conductor that is in contact with the top surface, and
the bottom surface conductor, the first through conductor, the top surface conductor, and the second through conductor are connected in order and configure a part of a spiral coil (Matsuki, para. [0085]).
Claims 1-3 and 6 are also rejected under 35 U.S.C. 103 as being unpatentable over Mizushiro (U.S. PG. Pub. No. 2018/0158607 A1) in view of Yosui.
With respect to claim 1, Mizushiro teaches an electronic component 1a (FIG. 1-3) comprising:
a glass substrate 2;
an outer surface conductor 6a that is in contact with an outer surface (upper or lower surface) of the glass substrate; and
a protective film 7a that covers the outer surface of the glass substrate and the outer surface conductor and is in contact with the outer surface of the glass substrate and the outer surface conductor,
wherein when the glass substrate has first surface roughness Ra1 Rz2 at an interface (interface at surface roughness Rz2) between the glass substrate and the outer surface conductor, the glass substrate has second surface roughness Ra2 Rz1 at an interface (interface at surface roughness Rz1) between the glass substrate and the protective film, and the outer surface conductor has third surface roughness Ra3 Rz3 (annotated FIG. 3) at an interface (interface at Rz3) between the outer surface conductor and the protective film, Ra1 <Ra2 is satisfied (para. [0045]).
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Mizushiro does not expressly teach Ra1<Ra3<Ra2 is satisfied.
Yosui teaches an electronic component (FIG. 5A),
wherein Ra1<Ra3 is satisfied (para. [0057]). Surface roughness of first principal surface 91 is greater than surface roughness of second surface 93.The incorporation of the surface roughness teaching of Yosui to the electronic component of Mizushiro would result in “Ra1<Ra3<Ra2 is satisfied” as claimed. Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate the surface roughness as taught by Yousi to the electronic component of Mizushiro to improve the mechanical adhesion among the outer glass substrate, the outer surface conductor and the protective film.
With respect to claim 2, Mizushiro in view of Yosui teaches the electronic component according to claim 1, wherein (Ra3−Ra1)<(Ra2−Ra3) is satisfied (Mizushiro, para. [0045] and Yosui, para. [0057]). The combination of the Matsuki and Yosui would have the claimed limitation.
With respect to claims 3 and 6, Mizushiro in view of Yosui teaches the electronic component according to claims 1 and 2 respectively, further comprising:
a first through conductor 5a or 5b and a second through conductor (the other of through conductor 5a or 5b) that penetrate the glass substrate, wherein
the outer surface includes a bottom surface (lower surface), which is one main surface of the glass substrate, and a top surface (upper surface) located on a back side of the bottom surface,
the outer surface conductor includes a bottom surface conductor 6b that is in contact with the bottom surface and a top surface conductor 6a that is in contact with the top surface, and
the bottom surface conductor, the first through conductor, the top surface conductor, and the second through conductor are connected in order and configure a part of a spiral coil (Mizushiro, para. [0045]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. A list of pertinent prior art is attached in form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANGTIN LIAN whose telephone number is (571)270-5729. The examiner can normally be reached Monday-Friday 0800-1700.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shawki S. Ismail can be reached at 571-272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MANG TIN BIK LIAN/ Primary Examiner, Art Unit 2837
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