DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species IX, corresponding to the “gate driver circuit” embodiment of originally filed Claims 17, 22, and 23, in the reply filed on 16 December 2024 is acknowledged.
Claim 22 is objected as being directed to allowable subject matter. The restriction requirement between Groups I through XI, as set forth in the Office action mailed on 22 November 2024, has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Specifically, the restriction requirement of 22 November 2024 is partially withdrawn. Claim 24, directed to subject matter further defining the allowable subject matter of Claim 22, is no longer withdrawn from consideration because the claim requires all the limitations of a claim that is objected as being directed to allowable subject matter.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Response to Amendment
The amendment received 05 May 2025 directs the claimed invention to features of Figure 12 of the originally filed disclosure that are not supported by the provisional application filed 17 October 2022. Thus, for the purposes of examination, the effective filing date of the claimed invention is 23 May 2023.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-18, 40-43, 45-47, and 50 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byun et al. (hereinafter “Byun” US 2021 / 0225256).
As pertaining to Claim 17, Byun discloses (see Fig. 7) a gate driver circuit (ST1; see Page 4, Para. [0060]; and Page 6, Para. [0094]-[0095]) comprising:
a shift register subcircuit (i.e., see (TP1, TP2), for example, in (STP1)) configured to receive shift register clock signals (CLK1, CLK2), to receive a carry in signal (see (FLM) corresponding to (CRk)), and to generate a carry out signal (CR1); and
an output buffer subcircuit (see (TP5, TP4, TP7, TP6) in (STP1)) configured to receive an output buffer clock signal (CLK2) and to generate a corresponding gate output signal (SP1), the output buffer subcircuit (again, see (TP5, TP4, TP7, TP6) in (STP1)) including:
a first transistor (TP5) having a first source-drain terminal configured to receive the output buffer clock signal (i.e., see (CLK2)) and having a second source-drain terminal at which the gate output signal (SP1) is generated;
a second transistor (TP4) having a first source-drain terminal coupled to the second source-drain terminal of the first transistor (TP5) and having a second source-drain terminal coupled (i.e., via path (CP2, TP8)) to a power supply line (VSS);
a third transistor (TP7) having a first source-drain terminal coupled to a gate terminal of the second transistor (TP4), a second source-drain terminal coupled to a node (see (TP1)) in the shift register subcircuit (again, see (TP1, TP2), for example, in (STP1)), and a gate terminal that is coupled (i.e., via path (TP2, TP3, CP2, TP8)) to the power supply line (VSS); and
a fourth transistor (TP6) having a first source-drain terminal directly coupled to a gate terminal of the first transistor (TP5) and a gate terminal that is directly coupled to the power supply line (VSS; see Page 8 through Page 10, Para. [0124]-[0167] for a complete description of the subcircuits of Figure 7; in particular, see Page 8 through Page 9, Para. [0124]-[0136] and [0138]-[0142]).
As pertaining to Claim 18, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (TP5, TP4, TP7, TP6) in (STP1)) further comprises:
a first capacitor (CN1) having a first terminal (i.e., a lower terminal) coupled (i.e., via path (TN1)) to the gate terminal of the second transistor (TP4) and having a second terminal (i.e., an upper terminal) configured to receive one of the shift register clock signals (CLK2; see Page 10, Para. [0158]-[0159]).
As pertaining to Claim 40, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (TP5, TP4, TP7, TP6) in (STP1)) further comprises:
a capacitor (CP2) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TP4) and having a second terminal (i.e., an upper terminal); and
a fifth transistor (TP3) having a source-drain terminal directly coupled to the second terminal (i.e., the upper terminal) of the capacitor (CP2) and having a gate terminal coupled to an additional gate driver circuit (i.e., see any portion of (STN1) and/or any additional (ST1); and see Page 8 through Page 9, Para. [0124]-[0136] and [0138]-[0142]).
As pertaining to Claim 41, Byun discloses (see Fig. 7) that the fifth transistor (TP3) further comprises an additional source-drain terminal configured to receive (i.e., via path (TP2, TN4, CN2, TN5) and/or path (TP2, TP6, CP1, TP5)) one of the shift register clock signals (CLK2; again, see Page 8 through Page 9, Para. [0124]-[0136] and [0138]-[0142]).
As pertaining to Claim 42, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (TP5, TP4, TP7, TP6) in (STP1)) further comprises:
a capacitor (CP2) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TP4) and having a second terminal (i.e., an upper terminal); and
a fifth transistor (TP3) having a source-drain terminal directly coupled to the second terminal (i.e., the upper terminal) of the capacitor (CP2) and a second source-drain terminal configured to receive (i.e., via path (TP2, TN4, CN2, TN5) and/or path (TP2, TP6, CP1, TP5)) one of the shift register clock signals (CLK2; again, see Page 8 through Page 9, Para. [0124]-[0136] and [0138]-[0142]).
As pertaining to Claim 43, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (TP5, TP4, TP7, TP6) in (STP1)) further comprises:
a first capacitor (CP2) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TP4) and having a second terminal (i.e., an upper terminal) configured to receive (i.e., via path (TP4, TP5) and/or path (TP3, TP2, TP5, CP1)) one of the shift register clock signals (CLK2; again, see Page 8 through Page 9, Para. [0124]-[0136] and [0138]-[0142]).
As pertaining to Claim 45, Byun discloses (see Fig. 7) a gate driver circuit (ST1; see Page 4, Para. [0060]; and Page 6, Para. [0094]-[0095]) comprising:
a shift register subcircuit (i.e., see (TP1, TP2), for example, in (STP1)) configured to receive shift register clock signals (CLK1, CLK2), to receive a carry in signal (see (FLM) corresponding to (CRk)), and to generate a carry out signal (CR1); and
an output buffer subcircuit (see (TN8, TN9, TN1, TN7) in (STN1)) configured to receive an output buffer clock signal (CLK3) and to generate a corresponding gate output signal (SN1) to a first row of pixels (i.e., see (PX) in Fig. 1 and Page 3, Para. [0053]), the output buffer subcircuit (again, see (TN8, TN9, TN1, TN7) in (STN1)) including:
a first transistor (TN8) having a first source-drain terminal configured to receive the output buffer clock signal (CLK3) and having a second source-drain terminal at which the gate output signal (SN1) is generated;
a second transistor (TN9) having a first source-drain terminal coupled to the second source-drain terminal of the first transistor (TN8) and having a second source-drain terminal coupled to a power supply line (VSS);
a third transistor (TN1) having a first source-drain terminal coupled to a gate terminal of the second transistor (TN9), a second source-drain terminal coupled to a node (NP1) in the shift register subcircuit (again, see (TP1, TP2), for example, in (STP1)), and a gate terminal that is coupled to the power supply line (VSS); and
a fourth transistor (TN2) having a first source-drain terminal (i.e., an upper terminal) coupled (i.e., via (CN1)) to the gate terminal of the second transistor (TN9), a second source-drain terminal (i.e., a lower terminal) configured to receive one of the shift register clock signals (CLK2), and a gate terminal configured to receive a signal (i.e., (OS1)) from an additional gate driver circuit (i.e., see any portion of (STP1) and/or any additional (ST1)) configured to generate a corresponding gate output signal (i.e., a corresponding (SN1)) to a second row of pixels (again, see (PX) in Fig. 1 for a successive row of pixels) different than the first row of pixels (see Page 8 through Page 10, Para. [0124]-[0167] for a complete description of the subcircuits of Figure 7; in particular, see Page 8, Para. [0124]-[0128]; Page 9, Para. [0143]-[0149]; and Page 10, Para. [0154]-[0156] and Para. [0161]-[0162]; and see Fig. 6 and note that each gate driver circuit corresponding to any portion of (STP1) and/or any additional (ST1) is configured to generate a corresponding gate output signal via a generated carry signal (CR) that is generated and passed from row to row).
As pertaining to Claim 46, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (TN8, TN9, TN1, TN7) in (STN1)) further comprises:
a fifth transistor (TN4) having a first source-drain terminal coupled to a gate terminal of the first transistor (TN8) and a gate terminal that is coupled to the power supply line (VSS; see Page 9, Para. [0147]; and Page 10, Para. [0161]-[0162]).
As pertaining to Claim 47, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (TN8, TN9, TN1, TN7) in (STN1)) further comprises:
a first capacitor (CN1) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TN9) and having a second terminal (i.e., an upper terminal) directly coupled to the first source-drain terminal of the fourth transistor (TN2; see Page 10, Para. [0156] and [0158]-[0159]).
As pertaining to Claim 50, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (TN8, TN9, TN1, TN7) in (STN1)) further comprises:
a fifth transistor (TN4) having a first source-drain terminal (i.e., a right terminal) coupled (i.e., via (CN2, TN5, TN2, CN1)) to the gate terminal of the fourth transistor (TN2), a gate terminal shorted to the power supply line (VSS), and a second source-drain terminal (i.e., a left terminal) directly coupled (i.e., via (NN3)) to the additional gate driver circuit (see (TP4, TP5, TP6), for example in (STP1); and see Page 10, Para. [0161]-[0162]).
Claims 51 and 53 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung et al. (hereinafter “Chung” US 2016 / 0210925).
As pertaining to Claim 51, Chung discloses (see Fig. 2 and Fig. 5) a gate driver circuit (100; see Page 5 through Page 6, Para. [0068]-[0069]) comprising:
a shift register subcircuit (see any portion of (SRCN) in Fig. 5) configured to receive shift register clock signals (CLK1, CLK1’, CLK2, CLK3, CLK3’, CLK4), to receive a carry in signal (see (S[N-1]) serving as a carry in signal), and to generate a carry out signal (see (S[N]) serving as a carry out signal); and
an output buffer subcircuit (see at least (150B, 160, T5, C4)) configured to receive an output buffer clock signal (CLK3’) and to generate a corresponding gate output signal (S[N]), the output buffer subcircuit (150B, 160, T5, C4) including:
a first transistor (Tu) having a first source-drain terminal configured to receive the output buffer clock signal (CLK3’) and having a second source-drain terminal at which the gate output signal (S[N]) is generated;
a second transistor (T8) having a first source-drain terminal coupled (i.e., via path (T9, C5)) to the second source-drain terminal of the first transistor (Tu) and having a second source-drain terminal coupled (i.e., via path (TSD, C5, TD) or via path (TSD, T2, T2, T14)) to a fixed power supply line (GCK1; note that (GCK1) is fixed at a high level or a low level during driving);
a third transistor (T5) having a first source-drain terminal coupled to a gate terminal of the second transistor (T8), a second source-drain terminal coupled to a node (see a left node of (T5)) in the shift register subcircuit (see any portion of (SRCN) in Fig. 5), and a gate terminal that is coupled to the fixed power supply line (GCK1); and
a first capacitor (C4) having a first terminal (i.e., an upper terminal) directly coupled to the gate terminal of the second transistor (T8) and having a second terminal (i.e., a lower terminal); and
a second capacitor (C6) having a first terminal (i.e., an upper terminal) directly coupled to the second terminal (i.e., the lower terminal) of the first capacitor (C4) and having a second terminal (i.e., a lower terminal) shorted to the fixed power supply line (GCK1; see Page 6 through Page 7, Para. [0080], [0082], and [0086]; and Page 8, Para. [0088]-[0090] and [0092]-[0095] for a general description of Figure 5).
As pertaining to Claim 53, Chung discloses (see Fig. 2 and Fig. 5) that the output buffer subcircuit (see at least (150B, 160, T5, C4)) further comprises:
a fourth transistor (T4) having a first source-drain terminal directly coupled to the first capacitor (C4), a second source-drain terminal configured to receive one of the shift register clock signals (CLK1’), and a gate terminal configured to receive a signal (CLK1) from an additional gate driver circuit (i.e., a clock generation circuit; again, see Page 6 through Page 7, Para. [0080], [0082], and [0086]; and Page 8, Para. [0088]-[0090] and [0092]-[0095] for a general description of Figure 5).
Allowable Subject Matter
Claims 22-24, 44, 48-49, and 54 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the combination of structural and/or functional features recited in at least Claims 22-24, 44, 48-49, and 54. Specifically, none of the references relied upon by the examiner teach or fairly suggest all of the features of Claim 17 in combination with the features of Claim 22; none of the references relied upon by the examiner teach or fairly suggest all of the features of Claims 17 and 43 in combination with the features of Claim 44; none of the references relied upon by the examiner teach or fairly suggest all of the features of Claims 45 and 47 in combination with the features of Claim 48; and none of the references relied upon by the examiner teach or fairly suggest all of the features of Claims 51 and 53 in combination with the features of Claim 54.
As pertaining to the most relevant prior art relied upon by the examiner, Byun and/or Chung, as relied upon by the examiner in the above rejections, disclose all of the features as claimed in Claims 17-18, 40-43, 45-47, 50-51, and 53. However, none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest all of the structural features of the cited claims in combination with the features of Claims 22, 44, 48, and 54. The claimed combination of features is shown in Figure 12 of the applicant’s originally filed disclosure, particularly with respect to elements CQB2, C1, T16, and C2. The combination of features as required by Claims 22, 44, 48, and 54 appears to be suggested solely by the applicant’s disclosure.
Response to Arguments
Applicant's arguments filed 24 July 2025 with respect to Claims 17-18, 22-24, 40-51, and 53-54 have been fully considered but they are either not persuasive or are moot in view of the new grounds of rejection provided above. The applicant has argued with respect to Claims 17-18, 22-24, and 40-44 that the teachings of Byun, as previously relied upon by the examiner in the prior Office Action, do not provide for the newly recited “fourth transistor” of independent Claim 17 that has “a first source-drain terminal directly coupled to a gate terminal of the first transistor and a gate terminal that is directly coupled to the power supply line” (see Remarks at Page 11). Respectfully, the applicant’s argument is moot in so much as Byun, as newly relied upon by the examiner, discloses all of the features of newly recited independent Claim 17. The applicant is respectfully reminded that the claimed invention must be given its broadest reasonable interpretation in view of the specification without reading features from the specification into the claims. With respect to Claims 45-50, the applicant has asserted that the teachings of Byun, as relied upon by the examiner in the prior Office Action, do not teach or fairly suggest “an additional gate driver circuit configured to generate a corresponding gate output signal to a second row of pixels different than the first row of pixels” (see Remarks at Page 12). Upon thorough consideration of these features as presented in independent Claim 45, the examiner respectfully disagrees. The examiner respectfully points out that both of the claimed “additional gate driver circuit” and the claimed “signal” from the “additional gate driver circuit” are open to interpretation. The examiner respectfully maintains that the teachings of Byun provide for a fourth transistor (TN2) having a gate terminal configured to receive a signal, “OS1” for example, from an additional gate driver circuit, namely any portion of (STP1) and/or any additional (ST1), that is configured to generate a corresponding gate output signal, namely a corresponding (SN1), to a second row of pixels (PX) for a successive row of pixels different than the first row of pixels, as each gate driver circuit corresponding to any portion of (STP1) and/or any additional (ST1) is configured to generate a corresponding gate output signal via a generated carry signal (CR) that is generated and passed from row to row. The applicant has further argued with respect to Claims 51, 53, and 54 that the teachings of Chung, as relied upon by the examiner in the prior Office Action, do not provide for the “fixed power supply line” as claimed (see Remarks at Pages 12 and 13). Again, upon thorough consideration of these features as presented in independent Claim 51, the examiner respectfully disagrees. The examiner respectfully points out that the claimed “fixed power supply line” as claimed recites nothing related to the claimed “power supply line” or the claimed “fixed power” that would distinguish this feature from the fixed power supply line (GCK1) of Chung, as the line corresponding to (GCK1) is fixed and the power supply (GCK1) is fixed at either a high level or a low level during arbitrary periods of driving.
For at least these reasons, the rejection of Claims 17-18, 40-43, 45-47, 50-51, and 53 is maintained. Claims 22-24, 44, 48-49, and 54 remain objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Qing et al. (US 2024 / 0185936) at least at Figure 3B, Wang (US 2024 / 0087498) at least at Figure 3, and In (US 2023 / 0351941) at least at Figure 4 all disclose relevant gate driving circuits.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623