DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04 May 2026 has been entered.
Election/Restrictions
Applicant's election with traverse of Species IX, corresponding to the “gate driver circuit” embodiment of originally filed Claims 17, 22, and 23, in the reply filed on 16 December 2024 is acknowledged.
Claim 22 is objected as being directed to allowable subject matter. The restriction requirement between Groups I through XI, as set forth in the Office action mailed on 22 November 2024, has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Specifically, the restriction requirement of 22 November 2024 is partially withdrawn. Claim 24, directed to subject matter further defining the allowable subject matter of Claim 22, is no longer withdrawn from consideration because the claim requires all the limitations of a claim that is objected as being directed to allowable subject matter.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Response to Amendment
The amendment received 05 May 2025 directs the claimed invention to features of Figure 12 of the originally filed disclosure that are not supported by the provisional application filed 17 October 2022. Thus, for the purposes of examination, the effective filing date of the claimed invention is 23 May 2023.
Claim Objections
Claim 17 is objected to because of the following informalities: the claim recites “a second transistor having… a second source-drain directly terminal coupled to a power supply line.” The examiner assumes that the claim contains a typographical error and is intended to recite “… a second source-drain terminal directly coupled….” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-18 and 40-43 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (hereinafter “Kim” US 10,950,157).
As pertaining to Claim 17, Kim discloses (see Fig. 5) a gate driver circuit (300; see Col. 6, Ln. 15-20 and Col. 12, Ln. 42-44 and Ln. 57-59) comprising:
a shift register subcircuit (510, 520) configured to receive shift register clock signals (CCLK1, CCLK2), to receive a carry in signal (CR), and to generate a carry out signal (GWP); and
an output buffer subcircuit (540, 550) configured to receive an output buffer clock signal (CCLK3) and to generate a corresponding gate output signal (GWN), the output buffer subcircuit (540, 550) including:
a first transistor (TN6) having a first source-drain terminal configured to receive the output buffer clock signal (CCLK3) and having a second source-drain terminal at which the gate output signal (GWN) is generated;
a second transistor (TN5) having a first source-drain terminal coupled to the second source-drain terminal of the first transistor (TN6) and having a second source-drain terminal directly coupled to a power supply line (VGL);
a third transistor (TN1) having a first source-drain terminal coupled to a gate terminal of the second transistor (TN5), a second source-drain terminal coupled to a node (N2) in the shift register subcircuit (510, 520), and a gate terminal that is coupled to the power supply line (VGL); and
a fourth transistor (TN2) having a first source-drain terminal directly coupled to a gate terminal of the first transistor (TN6) and a gate terminal that is directly coupled to the power supply line (VGL; see Col. 12, Ln. 60-67 through Col. 13, Ln. 1-17; Col. 13, Ln. 56-65; Col. 15, Ln. 22-67 through Col. 16, Ln. 1-6).
As pertaining to Claim 18, Kim discloses (see Fig. 5) that the output buffer subcircuit (540, 550) further comprises:
a first capacitor (CN1) having a first terminal (i.e., a lower terminal) coupled to the gate terminal of the second transistor (TN5) and having a second terminal (i.e., an upper terminal) configured to receive one of the shift register clock signals (CCLK1; see Col. 15, Ln. 22-27).
As pertaining to Claim 40, Kim discloses (see Fig. 5) that the output buffer subcircuit (540, 550) further comprises:
a capacitor (CN1) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TN5) and having a second terminal (i.e., an upper terminal); and
a fifth transistor (TN3) having a source-drain terminal directly coupled to the second terminal (i.e., the upper terminal) of the capacitor (CN1) and having a gate terminal coupled to an additional gate driver circuit (i.e., see any portion of (STP), and/or (TN1), and/or any additional (ST); and see Col. 15, Ln. 22-27).
As pertaining to Claim 41, Kim discloses (see Fig. 5) that the fifth transistor (TN3) further comprises an additional source-drain terminal configured to receive one of the shift register clock signals (CCLK1; again, see Col. 15, Ln. 22-27).
As pertaining to Claim 42, Kim discloses (see Fig. 5) that the output buffer subcircuit (540, 550) further comprises:
a capacitor (CN1) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TN5) and having a second terminal (i.e., an upper terminal); and
a fifth transistor (TN3) having a first source-drain terminal directly coupled to the second terminal (i.e., the upper terminal) of the capacitor (CN1) and a second source-drain terminal configured to receive one of the shift register clock signals (CCLK1; again, see Col. 15, Ln. 22-27).
As pertaining to Claim 43, Kim discloses (see Fig. 5) that the output buffer subcircuit (540, 550) further comprises:
a first capacitor (CN1) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TN5) and having a second terminal (i.e., an upper terminal) configured to receive one of the shift register clock signals (CCLK1; again, see Col. 15, Ln. 22-27).
Claims 45-47 and 50 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Byun et al. (hereinafter “Byun” US 2021 / 0225256).
As pertaining to Claim 45, Byun discloses (see Fig. 7) a gate driver circuit (ST1; see Page 4, Para. [0060]; and Page 6, Para. [0094]-[0095]) comprising:
a shift register subcircuit (i.e., see (210, 220)) configured to receive shift register clock signals (CLK1, CLK2), to receive a carry in signal (see (FLM) corresponding to (CRk)), and to generate a carry out signal (CR1); and
an output buffer subcircuit (see (240, 250, 260) in (STN1)) configured to receive an output buffer clock signal (CLK3) and to generate a corresponding gate output signal (SN1) to a first row of pixels (i.e., see (PX) in Fig. 1 and Page 3, Para. [0053]), the output buffer subcircuit (again, see (240, 250, 260)) including:
a first transistor (TN8) having a first source-drain terminal configured to receive the output buffer clock signal (CLK3) and having a second source-drain terminal at which the gate output signal (SN1) is generated;
a second transistor (TN9) having a first source-drain terminal coupled to the second source-drain terminal of the first transistor (TN8) and having a second source-drain terminal coupled to a power supply line (VSS);
a third transistor (TN1) having a first source-drain terminal coupled to a gate terminal of the second transistor (TN9), a second source-drain terminal coupled to a node (NP1) in the shift register subcircuit (again, see (210, 220)), and a gate terminal that is coupled to the power supply line (VSS); and
a fourth transistor (TN2) having a first source-drain terminal (i.e., an upper terminal) coupled (i.e., via (CN1)) to the gate terminal of the second transistor (TN9), a second source-drain terminal (i.e., a lower terminal) configured to receive one of the shift register clock signals (CLK2), and a gate terminal configured to receive a signal (i.e., (OS1)) generated by an additional gate driver circuit (i.e., see an additional (ST1) for a previous row of pixels (PX) in Fig. 1 that generates the signal (OS1) via the passing of the carry signal (CR)), separate from the shift register subcircuit (i.e., see (210, 220)), configured to generate a corresponding gate output signal (i.e., a corresponding (SN)) to a second row of pixels (again, see (PX) in Fig. 1 for a previous row of pixels) different than the first row of pixels (see Page 8 through Page 10, Para. [0124]-[0167] for a complete description of the subcircuits of Figure 7; in particular, see Page 8, Para. [0124]-[0128]; Page 9, Para. [0143]-[0149]; and Page 10, Para. [0154]-[0156] and Para. [0161]-[0162]).
As pertaining to Claim 46, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (240, 250, 260) in (STN1)) further comprises:
a fifth transistor (TN4) having a first source-drain terminal coupled to a gate terminal of the first transistor (TN8) and a gate terminal that is coupled to the power supply line (VSS; see Page 9, Para. [0147]; and Page 10, Para. [0161]-[0162]).
As pertaining to Claim 47, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (240, 250, 260) in (STN1)) further comprises:
a first capacitor (CN1) having a first terminal (i.e., a lower terminal) directly coupled to the gate terminal of the second transistor (TN9) and having a second terminal (i.e., an upper terminal) directly coupled to the first source-drain terminal of the fourth transistor (TN2; see Page 10, Para. [0156] and [0158]-[0159]).
As pertaining to Claim 50, Byun discloses (see Fig. 7) that the output buffer subcircuit (see (240, 250, 260) in (STN1)) further comprises:
a fifth transistor (TN4) having a first source-drain terminal (i.e., a right terminal) coupled (i.e., via (CN2, TN5, TN2, CN1)) to the gate terminal of the fourth transistor (TN2), a gate terminal shorted to the power supply line (VSS), and a second source-drain terminal (i.e., a left terminal) directly coupled (i.e., via (NN3)) to the additional gate driver circuit (see Page 10, Para. [0161]-[0162]).
Allowable Subject Matter
Claims 22-24, 44, and 48-49 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the combination of structural and/or functional features recited in at least Claims 22-24, 44, and 48-49. Specifically, none of the references relied upon by the examiner teach or fairly suggest all of the features of Claim 17 in combination with the features of Claim 22; none of the references relied upon by the examiner teach or fairly suggest all of the features of Claims 17 and 43 in combination with the features of Claim 44; and none of the references relied upon by the examiner teach or fairly suggest all of the features of Claims 45 and 47 in combination with the features of Claim 48.
As pertaining to the most relevant prior art relied upon by the examiner, at least the teachings of Kim and Byun, as relied upon by the examiner in the above rejections, disclose all of the features as claimed in Claims 17-18, 40-43, 45-47, and 50. However, none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest all of the structural features of the cited claims in combination with the respective features of Claims 22, 44, and 48. The claimed combination of features is shown in Figure 12 of the applicant’s originally filed disclosure, particularly with respect to elements CQB2, C1, T16, and C2. The combination of features as required by Claims 22, 44, and 48 appears to be suggested solely by the applicant’s disclosure.
Claims 51, 53, and 54 are allowed.
The following is an examiner’s statement of reasons for allowance: none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the combination of features recited in independent Claim 51. Specifically, none of the references relied upon by the examiner teach or fairly suggest the claimed gate driver circuit comprising: “a shift register subcircuit configured to receive shift register clock signals, to receive a carry in signal, and to generate a carry out signal; and an output buffer subcircuit configured to receive an output buffer clock signal and to generate a corresponding gate output signal, the output buffer subcircuit including: a first transistor having a first source-drain terminal configured to receive the output buffer clock signal and having a second source-drain terminal at which the gate output signal is generated; a second transistor having a first source-drain terminal directly coupled to the second source-drain terminal of the first transistor and having a second source- drain terminal directly coupled to a fixed power supply line; a third transistor having a first source-drain terminal coupled to a gate terminal of the second transistor, a second source-drain terminal coupled to a node in the shift register subcircuit, and a gate terminal that is coupled to the fixed power supply line; a first capacitor having a first terminal directly coupled to the gate terminal of the second transistor and having a second terminal; and a second capacitor having a first terminal directly coupled to the second terminal of the first capacitor and having a second terminal shorted to the fixed power supply line.”
As pertaining to the most relevant prior art relied upon by the examiner, Huang et al. (US 2021 / 0225231) discloses (see Fig. 9) a gate driver circuit (see Page 9, Para. [0098]-[0100]) comprising:
a shift register subcircuit (T1, T3, T4) configured to receive shift register clock signals (CKB), to receive a carry in signal (STV), and to generate a carry out signal (STV_OUT); and
an output buffer subcircuit (T13, T14, C3, C4) configured to receive an output buffer clock signal (CK) and to generate a corresponding gate output signal (OUT), the output buffer subcircuit (T13, T14, C3, C4) including:
a first transistor (T13) having a first source-drain terminal configured to receive the output buffer clock signal (CK) and having a second source-drain terminal at which the gate output signal (OUT) is generated;
a second transistor (T14) having a first source-drain terminal directly coupled to the second source-drain terminal of the first transistor (T13) and having a second source-drain terminal directly coupled to a fixed power supply line (VSS);
a third transistor (T16) having a first source-drain terminal coupled (i.e., via (C3)) to a gate terminal of the second transistor (T14), a second source-drain terminal coupled (i.e., via path (C2), (T7)) to a node (PUCN) in the shift register subcircuit (T1, T3, T4), and a gate terminal that is coupled (i.e., via (C4)) to the fixed power supply line (VSS); and
a first capacitor (C3) having a first terminal (i.e., an upper terminal) directly coupled to the gate terminal of the second transistor (T14) and having a second terminal (i.e., a lower terminal); and
a second capacitor (C4) having a first terminal (i.e., an upper terminal) directly coupled to the first terminal (i.e., the upper terminal) of the first capacitor (C3) and having a second terminal (i.e., a lower terminal) shorted to the fixed power supply line (VSS; see Page 6 through Page 7, Para. [0066]-[0079]).
However, Huang et al. neither discloses nor suggests the claimed output buffer subcircuit comprising the claimed first capacitor and the claimed second capacitor arranged in the manner claimed. In fact, neither Huang et al. nor any other reference relied upon by the examiner, considered alone or in reasonable combination, discloses all of the structural features of independent Claim 51 wherein the claimed output buffer subcircuit comprises a first capacitor having a first terminal directly coupled to the gate terminal of the second transistor and having a second terminal; and a second capacitor having a first terminal directly coupled to the second terminal of the first capacitor and having a second terminal shorted to the fixed power supply line. The claimed combination of features appears to be suggested solely by the applicant’s disclosure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 04 May 2026 with respect to newly amended independent Claim 51 (see Remarks at Page 12) have been fully considered and are persuasive. Therefore, Claims 51, 53, and 54 have been indicated as allowable.
Applicant’s arguments with respect to newly amended Claim 17 (see Remarks at Page 11) have been fully considered but are moot because the new ground of rejection presented above does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner respectfully maintains that the teachings of Kim, as newly relied upon in the above rejections, disclose all of the features of Claims 17-18 and 40-43. However, the examiner Claims 22-24 and 44 remain objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant’s arguments with respect to newly amended Claim 45 (see Remarks spanning Pages 11 and 12) have been fully considered but they are not persuasive. In this regard, the applicant has argued that the teachings of Byun, as relied upon by the examiner in the prior Office Action, do not provide for a “fourth transistor” that “has a gate terminal configured to ‘receive a signal generated by an additional gate driver circuit, separate from the shift register subcircuit.’” The examiner respectfully disagrees. The examiner respectfully reminds the applicant that the claims must be given their broadest reasonable interpretation in view of the Specification without reading features from the Specification into the claims. The claimed “additional gate driver circuit” and “shift register subcircuit” are arbitrarily defined and open to broad interpretation. Further, in this regard, the claimed “signal generated by an additional gate driver circuit” is arbitrarily defined both with respect to the “signal” that is generated and with respect to the manner in which the “signal” is generated. The examiner respectfully maintains that the teachings of Byun provide for the claimed “fourth transistor” at least in the manner reflected in the above rejection of Claim 45.
For at least these reasons, the rejection of Claims 17-18, 40-43, 45-47, and 50 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Qing et al. (US 2024 / 0185936) at least at Figure 3B, Wang (US 2024 / 0087498) at least at Figure 3, and In (US 2023 / 0351941) at least at Figure 4 all disclose relevant gate driving circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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