DETAILED ACTION
This action is responsive to: the request for continued examination, the amended claim, and the applicant arguments/remarks made in an amendment filed on January 12, 2026.
Claims 1-5, 7-12, 14-18, and 20 are pending. Claims 1, 8, and 15 are independent. Claims 6, 13 and 19 were cancelled by applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
“Vbl2” and “Vbl3” are referenced in the description of waveforms in Fig. 9. but no waveforms are labeled as such in the drawings.
“Vbl4” and “Vbl5” are referenced in the description of waveforms in Fig. 10. but no waveforms are labeled as such in the drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Applicant stated in response to non-final rejection that Vbl2-5 do not constitute reference signs, but instead are “placeholders for numerical values for transient voltages.” However, applicant included in Figs. 9 and 10 contain the reference signs “Vpgm1,” “Vpgm2,” and “Vpgm3” and “Vpass1,” “Vpass2,” and “Vpass3” which themselves act as reference signs and placeholders for numerical values for transient voltages. Thus, the argument presented by applicant that these figures comply with 37 CFR 1.84(p)(5) is not persuasive. In that applicant has failed to show that the two qualities are mutually exclusive and furthermore a basis for excluding reference signs for bit line voltages in Figs. 9 and 10. Therefore the objection is maintained.
Claim Rejections - 35 USC § 112 – indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 7-12, 14-18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.02(II) instructs examiners, “Definiteness of claim language must be analyzed, not in a vacuum, but in light of: (A) The content of the particular application disclosure; (B) The teachings of the prior art; and (C) The claim interpretation that would be given by one possessing the ordinary level of skill in the pertinent art at the time the invention was made.”
The claims are not clear and create confusion with the recitation of the variable “i” that must be great than 1, but is also recited as limiting the number of times “pulse programming” is performed by way of an equation “i-1,” along with later recited limitations on i-1 and n>=i and n-1. The disclosure more clearly aligns the “program state” number (e.g., L1, L2, L3, L4) with the number of times pulse programming is performed (e.g., 1, 2, 3, 4, respectively). Some of the clarity issues in the claims are the use of variables recited in ways that are difficult to follow. Other clarity issues involve using terms that do not express the actual feature, but instead express something else that is caused by the unrecited feature. Other clarity issues appear to be translation issues. Other issues appear to raise issues regarding antecedent basis, such as redundantly recited clauses.
The best evidence of the confusion and lack of clarity in the claims, is challenges in apply prior art to the claims where the prior art appears to disclose the same invention as applicant discloses (at least insofar as the claims appear to recite, to the extent their recitations are understood). For this reason, and for compact prosecution purposes, Khakifirooz et al. (US 10109361) is provided in the rejection below because it is the closest prior art and describes an identical invention to that disclosed by applicant.
As related to the use of “i” and “i-1” (as well as “n” and “n>=i and “n-1”), independent claims 1, 8, and 15, each recite “perform[ing] programming suppression on first memory cells . . . in a coarse programming process, such that the first memory cells are in a first programmed state.” As used in the claim, this “first programmed state” is different from the claimed “ith programmed state” (as recited in claims 1, 3, and 7 (and similarly, 8, 10, 14 and 15, 17, 20).
As indicated in applicant’s originally filed disclosure, the “first programmed state” is not a programmed state, but instead is the “erased state” (e.g., Spec. para. 62: “the first programmed state indicates an L0 programmed state, e.g., an erase state.”).
The claim requires certain cells to be “program[] suppress[ed].” Applicant explains in their originally filed disclosure (e.g., Spec. para. 49), “a programming suppression voltage is applied to the bit line coupled to the memory cell to cause it not to be programmed any longer.” In the prior art, for example Khakifirooz et al. (US 10109361), explains similarly, for memory cells that have achieved their target program state, their respective bit lines are connected to a voltage (such as 2-3V) “so that they are inhibited from further programming,” (Khakifirooz col. 7, lines 41-45). In other words, the claimed “programming suppression voltage” is program inhibit voltage applied to the bit line.
As indicated in the originally filed disclosure, the invention relates to performing coarse program without verify, which is recited in claim 1, and appears to be illustrated in Figure 7 for example. However, the claims are not clear and create confusion with the recitation of the variable “i” that must be great than 1, but is also recited as limiting the number of times “pulse programming” is performed by way of an equation “i-1.” The disclosure more clearly aligns the “program state” number (e.g., L1, L2, L3, L4) with the number of times pulse programming is performed (e.g., 1, 2, 3, 4, respectively).
Use of i and i-1 notation creates further confusion in the dependent claims such as dependent claims 3, 10, and 17, which not only redundantly recites “performing the pulse programming for i-1 times” making it unclear whether this is an additional performance of pulse programming for i-1 times or whether its recitation seeks to limit “the performing the pulse programming for i-1 times,” but also appears to link the programming for i-1 times to its antecedent claim’s “n-1 times” for applying programming pulses by way of a “first” i-1 programming pulse that is one of the “n-1 times.” The boundaries of claim 3 are unclear, and create further confusion in its dependent claim 4 (and 11, and 17).
Claim 5 (like 12 and 18) repeats “performing the pulse programming for i-1 times on the second memory cells to program the second memory cells to the ith programmed state comprising performing the pulse programming for i-1 times on the second memory cells to program the second memory cells to the ith programmed state . . . .” In short, this clause simply states the memory is programmed “based on a memory cell type,” but every memory is programmed “based upon” its cell type. The applicant further states that the intended for programming to be based upon the memory cell being classified as fast programming type or slow programming type. This feature does not distinguish the claim because there is no indication in the claim as to how the programming would be different based upon the fast type or slow type.
As helpful guidance, in response to this rejection, applicant should first carefully consider Khakifirooz et al (US 10109361) and then attempt to determine patentable differences, if any, applicant’s disclosed Figures 7, 9, and 10. At that point, if patentably differences are found, attempt to redraft claims to express the different method of coarse programming without verification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-12, 14-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Her et al (US 20200202915 A1), in view of Masuduzzaman (US 20170125087 A1) and Lin (US 20200234768 A1).
Regarding Independent Claim 1, Her teaches a method of programming a memory, through a programming operation having a coarse programming process and a fine programming process, the method comprising:
performing programming suppression (paragraph 0095 “program inhibit voltage…is applied”) on first memory cells in the coarse programming process, such that the first memory cells are in a first programmed state (fig. 8: E); and
performing pulse programming for i-1 times (Fig. 7B: Vpgmn) on second memory cells to program the second memory cells to an ith programmed state (Fig 8: P1-7) in the coarse programming process, where i is an integer greater than 1,
applying a programming voltage (Fig. 7B: Vpgmn) to word lines coupled to the second memory cells to program the second memory cells to the ith programmed state,
wherein the coarse programming process does not include programming verification (Fig. 7B).
However, Her fails to teach methods of programming fast cells by applying bit line voltages of less magnitude or for a shorter duration than what would be applied to slow cells
Masuduzzaman teaches that in response to the second memory cells corresponding to a fast programming type:
applying a first voltage (Fig. 20B: vbl_high) to the bit lines coupled to the second memory cells at a first stage of pulse programming, the first voltage less than the suppression voltage (para 61 “the connected bit line being pulled to a state designating program inhibit (e.g., Vdd)”);
applying the suppression voltage (para 61 “the connected bit line being pulled to a state designating program inhibit (e.g., Vdd)”) to the bit lines coupled to the second memory cells at a third stage of pulse programming subsequent to the first stage (Fig. 21: program slow memory cells, inhibit fast memory cells) ;
Lin teaches that in response to the second memory cells corresponding to a fast programming type:
a second voltage (para 235 “Referring now to waveform 2004 the selected bit line voltage is at a steady state value prior to time t2. An example of the steady state value is 0V… The bit line voltage is maintained at PE_Max until time t5, when it is reduced to the steady state value.”) to the bit lines coupled to the second memory cells at a second portion (Fig. 20: t5) of the second stage of pulse programming subsequent to the first portion (Fig 20: t3b, t5), the second voltage less than the first voltage;
applying the suppression voltage (Fig 20: PE_MAX) to the bit lines coupled to the second memory cells at a first portion (Fig 20: t3b, t5) of a second stage of pulse programming;
applying the suppression voltage (Fig 20: PE_MAX) to the bit lines coupled to the second memory cells at a third stage (Fig. 20: pulse_D) of pulse programming subsequent to the second stage (Fig. 20: pulse_C); and
When cells are fast and thus might be programmed past the desired threshold voltage its desirable to partially inhibit programming by either applying a lower voltage below the suppression voltage to the bit line. Or to apply an inhibit voltage to the bit line during the programming window. Doing such allows less charge to be captured in the cell and thus prevents the threshold voltage of the cell from being programmed beyond the desired value associated with a certain programming state.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lin and Masuduzzaman to the teachings of Her to produce a method of programming fast cells wherein during a programming pulse being applied to the word line a program suppression pulse is applied for part of the duration of the programming pulse. Or that when programming of fast cells a voltage lower than the program suppression pulse is applied. So as not to provide a greater change in threshold voltage during the programming of a fast cell than desired.
Regarding Claim 2, Her, Masuduzzaman, and Lin teach the limitations of Claim 1.
Her teaches determining a number n of programmed states in the coarse programming process (Fig. 8: P7, Foggy PGM), where n ≥ i; and
applying programming pulses for n-1 times (Fig. 7B: PLn-1) to a page in the memory based on the number n of the programmed states in the coarse programming process, the first memory cells and the second memory cells being memory cells in the page.
Regarding Claim 3, Her, Masuduzzaman, and Lin teach the limitations of Claim 2.
Her teaches wherein performing the pulse programming (Fig. 7B: Vpgm1-n) for i-1 times on the second memory cells to program the second memory cells to the ith programmed state comprises performing the pulse programming on the second memory cells at first i-1 programming pulses of the n-1 programming pulses to program the second memory cells to the ith programmed state.
Regarding Claim 4, Her, Masuduzzaman, and Lin teach the limitations of Claim 3.
Her further teaches in response to a number i of programming pulses applied to the page not reaching n-1, performing programming suppression on the second memory cells in a pulse programming process starting from an ith programming pulse (Fig 7B: Vpgm1-n) by applying the suppression voltage (paragraph 0095 “program inhibit voltage…is applied”) to the bit lines coupled to the second memory cells.
Regarding Independent Claim 8, Her teaches a memory device (Fig 2: 100) with a memory programmable by a programming operation having coarse programming and fine programming, the memory comprising: an array (Fig 2: 110) and a peripheral circuit (Fig 2: 120, 130, 131),
wherein the peripheral circuit is configured to perform the method of programming rejected in Claim 1.
Regarding Claim 9-11, Her, Masuduzzaman, and Lin teach the limitations of claim 8. And the method of programming, which the memory is configured to perform, that is recited in these claims are rejected for the same reasons as claims 2-4 respectively.
Regarding Independent Claim 15, A system (Fig 2: 100), comprising:
one or more memories (Fig 2: 100) programmable by a programming operation having coarse programming and fine programming, the memories comprising: an array (Fig 2: 110); and a peripheral circuit (Fig 2: 120, 130, 131),
wherein the peripheral circuit is configured to perform the methods rejected in claims 1 and 8.
Regarding Claim 16, Her , Masuduzzaman, and Lin teach the limitations of claim 15. And the method of programming, which the memory is configured to perform, that is recited in this claim is rejected for the same reasons as claims 2 and 9.
Regarding claim 17, Her, Masuduzzaman, and Lin teach the limitations of claim 16. And the method of programming, which the memory is configured to perform, that is recited in this claim is rejected for the same reasons as claims 3-4 and 10-11.
Regarding Claims 5, 12, and 18, Her, , Masuduzzaman, and Lin recite the limitations of Claims 2, 9, and 17. Her fails to teach different methods of classifying memory cells as either fast or slow memory cells for different fine programming operations based on the cell type.
However, Masuduzzaman teaches a method of applying a first voltage to word lines (paragraph 0063) coupled to the memory cells in the page;
performing programming verification on the memory cells in the page (Fig 16C: 1002); and
classifying the memory cells into a fast programming type and a slow programming type based on a threshold voltage of the memory cells (Fig 16C: 1014, 1016), and
wherein performing the pulse programming (paragraph 0101) for i-1 times on the second memory cells to program the second memory cells to the ith programmed state comprises performing the pulse programming for i-1 times on the second memory cells to program the second memory cells to the ith programmed state based on a memory cell type of the second memory cells.
It would have been prima facie obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Masuduzzaman to the teachings of Her to produce a method of programming 3D memories wherein after a coarse programming process without a verification step the cells are classified as either fast or slow cells before the fine programming process begins.
Regarding Claims 7, 14, and 20 Her, Masuduzzaman, and Lin teach the limitations of Claims 5, 12, and 18. Lin further teaches wherein performing the pulse programming for i-1 times on the second memory cells to program the second memory cells to the ith programmed state based on the memory cell type of the second memory cells comprises:
in response to the second memory cells corresponding to the slow programming type, applying the second voltage (para 235 “0V”) to the bit lines coupled to the second memory cells, and applying the programming voltage (Fig. 20: Vpgm) to the word lines (Fig. 4C: WLL0-WLL14) coupled to the second memory cells to perform the pulse programming for i-1 times to program the second memory cells to the ith programmed state.
Response to Arguments
Applicant’s arguments, see section III pages 11-12, filed May 18, 2026, with respect new matter not in the specification have been fully considered and are persuasive. The rejection of 1-5, 7-12, 14-18 and 20 under 35 U.S.C. 112(a) has been withdrawn.
With respect to this rejection applicant has pointed out in in their remarks that the second voltage referred to is not elements of Fig. 10 but rather when the bit line transition to ground at the same time as the programming pulse transitions to ground after programming of a state is performed. Referring to the figure provided by applicant this clears up the confusion present in the reading of the claim language.
Applicant's arguments with respect to the rejections under 35 U.S.C. 112(b) and 35 U.S.C. 103 filed May 18, 2026 have been fully considered but they are not persuasive.
Applicant argues that the rejection under 35 U.S.C. 112(b) is not responsive to the rejection and arguments made the previous office actions. Applicant alleges that the indices “i” and “n” are clear in that represent various numbers that relate to one another. However, the rejection is not based on the use of these indices alone, but rather how they are used. Many of the claims recite these indices as variably referring to programming pulses and programming states or both within the same sentence. What exactly they are referring to is lost in the claims.
Applicant further asserts that the rejection’s indication of difficulty in articulating how the substantially identical prior art applies to the indefinite claims is not a proper basis for definiteness analysis. This argument is not persuasive. 35 U.S.C. 112(b) states “The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter . . . .” Definiteness of claim language is not only evaluated in light of the originally filed disclosure and in light of how persons skilled in the relevant art would interpret the claims, but also in light of the prior art. MPEP 2173.05(II). The indefiniteness of the claims, as identified in the definiteness requirement rejection, is exemplified by the difficulty of applying prior art that is substantially identical to the claims.
Finally with respect to the arguments made with regard to the rejection under 35 U.S.C. 103 applicant claims that second voltage is recited by any of the references and therefore renders claims 1, 8 and 15 allowable. However, Lin discloses this limitation, as indicated supra. Therefore, the previous rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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