DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 8-9, 11-13, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 20220365724 A1), in view of Lee (US 11809290 B2), and further in view of Kim (US 20160117119 A1).
PNG
media_image1.png
361
78
media_image1.png
Greyscale
Claim 11. A system operative to manage completion queues (CQs) for a storage device, comprising: the storage device; and a host system coupled to the storage device, the host system further comprising: one or more processors; a host controller circuit coupled to the one or more processors; and host memory to store submission queues (SQs) and the CQs, wherein the host controller circuit is operative to: fetch a command from a given SQ that corresponds to a target CQ in the host memory; save the command in an SQ internal buffer of the host controller circuit; calculate, before sending the command to the storage device for execution, an available capacity (AC) associated with the given SQ in the host system to store a response to the command from the storage device, wherein the available capacity is calculated based on, at least in part, available slots in the target CQ; and send the command to the storage device for execution when the available capacity associated with the given SQ is non-zero.
Referring to claims 1, 11, and taking claim 11 as exemplary, Chou teaches a system operative to manage completion queues (CQs) for a storage device, comprising: ([Chou Summary])
the storage device; and ([Chou 0007] “storage device”)
a host system coupled to the storage device, the host system further comprising: ([Chou 0007] “host system coupled to a storage device”)
one or more processors; ([Chou 0007] “processors”)
a host controller circuit coupled to the one or more processors and the storage device; and ([Chou 0007] “host controller … one or more processors”)
host memory to store submission queues (SQs) and the CQs, ([Chou 0007] “memory to store SQs and CQs”)
wherein the host controller circuit is operative to: fetch a command from a given SQ that corresponds to a target CQ in the host memory; ([Chou Fig. 1, 0023-27] “The host driver 130 uses the SQs 125 to submit command descriptors to the host controller 120”, “submitting a command to an SQ” and “fetching a command from an SQ” are used interchangeably” i.e., the host controller fetches the commands before it sends them to the storage device.
Each SQ corresponds to its respective CQ because “Each SQ 125 identifies the CQ 126 that will receive its command completion notification”)
Chou does not teach to save the command in an SQ internal buffer of the host controller circuit.
However, Lee teaches save the command in an SQ internal buffer of the host controller circuit; ([Lee 3:19-37 (26-26)] As it is commonly done in the art, queues and buffers are used interchangeably, and so hSQ of Lee is taken as an “SQ internal buffer of the host controller”.)
Before the effective filing date of invention, it would have been obvious to a person of ordinary skill in the art, having the teachings of Chou and Lee before them to combine the host system of Chou with a host controller buffers of Lee. The reason or motivation for doing so would be so that ([Lee 4:29-60 (31)] “the reliability of the storage system 10 may be improved”).
Chou in view of Lee does not teach to calculate an available capacity (AC) associated with the given SQ for the host system to store a response to the command from the storage device, wherein the available capacity is calculated based on, at least in part, available slots in the target CQ.
However, Kim teaches calculate, before sending the command to the storage device for execution, an available capacity (AC) associated with the given SQ in the host system to store a response to the command from the storage device, wherein the available capacity is calculated based on, at least in part, available slots in the target CQ; and ([Kim 0145-0153], commands can be inhibited from being fetched from the submission queue if the completion queue is full and therefore the determination is made before that command has been executed.)
Before the effective filing date of invention, it would have been obvious to a person of ordinary skill in the art, having the teachings of Chou in view of Lee and Kim before them to combine the host system of Chou in view of Lee with the capacity determination of Kim. The reason or motivation for doing so would be ([Kim 0008] “provides a storage device with improved operating speed and an operating method of the storage device”).
Further, Chou in view of Lee, in view of Kim teaches send the command to the storage device for execution when the available capacity associated with the given SQ is non-zero. ([Kim 0093-96 and 0145-0153] when the CQ is not full, the execution result can be enqueued, and the next command can be fetched from the SQ for subsequent execution.)
Claim 1 is a method variation of a system of claim 11, and is rejected using the same rationale.
Referring to claims 2, 12, and taking claim 11 as exemplary, Chou modified teaches the system of claim 11, wherein the available capacity is calculated based on, at least in part, a difference between a given threshold for the given SQ and the number of slots in the target CQ that are occupied by responses to commands originating from the given SQ. ([Kim 0095-96, 0151] the capacity is calculated as the fullness of the queue and empty slots are tracked. As the queues are correspond to each other, SQ capacity figures into CQ capacity.)
Claim 2 is a method variation of a system of claim 12, and is rejected using the same rationale.
Referring to claims 3, 13, and taking claim 11 as exemplary, Chou modified teaches the system of claim 12, wherein the available capacity is the minimum of the available slots in the target CQ and the difference. ([Kim 0095-96, 0151] the available capacity is calculated as the queue available/empty (“not full”) slots are tracked.)
Claim 3 is a method variation of a system of claim 13, and is rejected using the same rationale.
Referring to claims 8, 18, and taking claim 11 as exemplary, Chou modified teaches the system of claim 11, wherein the host controller circuit is further operative to:
send the command when the number of active commands in an active command queue of the storage device is within a predetermined maximum value. ([Kim 0020-22, 0093-96] the command is fetched to the storage device, while head and tail pointers keep track of the number of commands in the queue, and therefore within a predetermined limit.)
Claim 8 is a method variation of a system of claim 18, and is rejected using the same rationale.
Referring to claims 9, 19, and taking claim 11 as exemplary, Chou modified teaches the system of claim 11, wherein the host controller circuit is further operative to:
stop the command from the given SQ from being sent to the storage device when there is zero available capacity in the host system to store the response. ([Kim 0020-24, 0093-96] “preventing commands from being fetched from one or more full submission queues” if the head and tail pointers indicate that the queue is full, no more commands can be enqueued to the storage device SQ.)
Claim 9 is a method variation of a system of claim 19, and is rejected using the same rationale.
Claim(s) 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 20220365724 A1), in view of Lee (US 11809290 B2), in view of Kim (US 20160117119 A1) as applied to claims 1 and 11 above, and further in view of Jeong (US 20230073200 A1).
Referring to claims 10, 20, and taking claim 20 as exemplary, Chou modified does not teach the system of claim 11, wherein the host controller circuit communicates with the storage device according to a Universal Flash Storage (UFS) standard.
However, Jeong teaches the system of claim 11, wherein the host controller circuit communicates with the storage device according to a Universal Flash Storage (UFS) standard. ([Jeong 0092] “a universal flash storage (UFS) device”)
Before the effective filing date of invention, it would have been obvious to a person of ordinary skill in the art, having the teachings of Chou modified before them to combine the host system of Chou modified with the UFS device of Jeong. The reason or motivation for doing so would be ([Jeong 0186] “a memory system according to an embodiment of the disclosure can improve data I/O performance while performing data I/O operations corresponding to commands input from an external device.”).
Claim 10 is a method variation of a system of claim 20, and is rejected using the same rationale.
Allowable Subject Matter
Claims 4-7 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to the independent claims 4 and 14, the closest prior art of record, the combination of Chou (US 20220365724 A1), in view of Lee (US 11809290 B2), and further in view of Kim (US 20160117119 A1), teaches the determination of capacity of submission queues (SQ) and completion queues (CQ) located in the host memory, as described in the base claims 1 and 11 in the Application dated 05/24/2023, but fails to teach the calculation of the available capacity to additionally take into account the SQ buffer and the CQ buffer located in the host controller, that is in turn located within the host, but outside of the host memory, failing to teach limitations of claims 4 and 14, specifically:
“the available capacity is calculated based on, at least in part, available slots in a CQ internal buffer of the host controller for buffering responses from the storage device.”
Claims 5-7 and 15-17 depend from claims 4 and 14 respectively, inherit all their limitations, and are objected to as being dependent upon a rejected base claim using the same rationale.
Response to Arguments
Applicant's arguments filed 2/10/2025 have been fully considered but they are not persuasive.
The Applicant’s arguments pertain to the new claim limitations which have been addressed in the appropriate claim rejections above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth M. Lo can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ALSIP/Primary Examiner, Art Unit 2136