Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-15 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub. 2017/0364332 to Lowell.
Lowell was cited in applicant’s IDS filed on 9/6/23.
As to claim 1, Lowell teaches the invention as claimed including a method of operating a data processor that comprises a programmable execution unit operable to execute programs to perform processing operations, and in which when executing a program, the execution unit executes the program for respective execution threads, each execution thread corresponding to a respective work item [accelerated processing device having compute unit(s) executing redundant threads of work items; fingerprints can be created for each of the redundant threads by encoding results of operations performed by the threads, components 100, 101-103 and 105-107, Fig. 1 and corresponding text; paragraph 1, lines 1-9; paragraph 17, lines 1-8], the execution unit having an associated thread generating circuit that is configured to generate execution threads for execution by the execution unit [APD being a hardware device, paragraph 14, generates redundant threads for execution by processing elements of compute unit(s) of the APD, paragraph 33; Fig. 1 and corresponding text], and the data processor further comprising a controller that is operable to issue processing tasks to the execution unit, wherein the thread generating circuit associated with the execution unit will then generate appropriate execution threads for execution by the execution unit [scheduling of threads for execution by processing elements of compute unit(s), paragraphs 14 and 19], the method comprising:
the controller signaling to the execution unit when fault detection testing is to be performed to thereby cause the thread generating circuit associated with the execution unit [allocation or scheduling of thread to processing elements of compute unit(s) for execution to perform/implement RMT, paragraph 33] to generate for execution by the execution unit a set of two or more identical execution threads, wherein each of the execution threads in the set of two or more identical execution threads is configured to perform identical processing for the same work item when executed [APD identifies a thread for execution and generates one or more threads that are redundant with the identified thread in executing the same operations, paragraph 33, lines 1-6; step 505, Fig.5 and corresponding text; paragraph 20, lines 1-6];
and the method further comprising:
executing by the execution unit the respective execution threads in the set of two or more identical execution threads such that the same work item is processed by each of the execution threads in the set of two or more identical execution threads [the redundant threads are executed concurrently or in parallel, paragraph 33, lines 7-11; step 510, Fig. 5 and corresponding text] ;
comparing a result of the processing of the same work item for the respective execution threads in the set of two or more identical execution threads that have processed the work item; and
using the comparison of the result of the processing of the same work item for the respective execution threads in the set of two or more identical execution threads that have processed the same work item to determine whether there is a fault associated with the data processor [results of operations performed by the redundant threads or the fingerprints for the redundant threads can then be compared to detect (or, in some cases correct) errors that occur during execution of the redundant threads, paragraph 17, lines 8-12; step 535, Fig. 5 and corresponding text].
As to claim 2, Lowell teaches the invention as claimed including wherein when the comparison shows that the result of the processing of the work item that has been processed by the execution threads in the set of two or more identical execution threads is different for different ones of the execution threads in the set of two or more identical execution threads, the method comprises determining on that basis that there is a fault associated with the programmable execution unit [non-matching fingerprints or results indicates an error has occurred, paragraph 35, lines 8-12; paragraphs 9 and 17].
As to claim 3, Lowell teaches the invention as claimed including wherein when executing a program, the programmable execution unit executes the program for groups of plural execution threads, and wherein the set of two or more identical execution threads are generated as part of the same group of execution threads [redundant threads executed by processing elements of a computer unit or within the APD, paragraph 17, lines 1-8; Fig. 1].
As to claim 4, Lowell teaches the invention as claimed including wherein the programmable execution unit comprises a plurality of processing lanes arranged in parallel, such that plural execution threads can be processed in different processing lanes of the execution unit in a single processing cycle, and wherein the method comprises executing the identical threads in the set of identical threads in different processing lanes of execution unit in the same processing cycle, such that the comparison includes a comparison of the processing result for identical execution threads executing in parallel execution lanes in the same processing cycle [redundant threads can be executed in parallel in different processing elements of a compute unit, paragraphs 1, 33 and 37].
As to claim 5, Lowell teaches the invention as claimed including wherein respective threads in the set of identical threads that perform processing of the same work item are executed by the execution unit in different processing cycles, such that the comparison includes a comparison of the processing result for identical execution threads performing processing of the same work item at different times [redundant threads can be executed concurrently in different processing elements of a compute unit and redundant threads that are/required to be synchronized, paragraphs 1, 33 and 37].
As to claim 9, Lowell teaches the invention as claimed including wherein the set of identical threads comprises three or more identical execution threads for processing the same work item, and wherein in response to different instances of processing the same work item for respective threads in the set of identical threads giving different processing results, a majority processing result from the set of identical threads processing the work item in question is used for continuing processing [voting scheme when more than two redundant thread such that majority vote is the correct result, paragraphs 9-10].
As to claim 10, Lowell teaches the invention as claimed including wherein the data processor is executing a program to perform an overall data processing job, and wherein the work items correspond to work items that need to be processed for the data processing job, wherein the step of generating for execution by the execution unit a set of two or more identical execution threads for processing the same work item comprises replicating the thread generation for a work item that needs to be processed for the overall data processing job [APD identifies a thread for execution and generates one or more threads that are redundant with the identified thread in executing the same operations, paragraph 33, lines 1-6; step 505, Fig.5 and corresponding text; paragraph 20, lines 1-6; the redundant threads are executed concurrently or in parallel, paragraph 33, lines 7-11; step 510, Fig. 5 and corresponding text].
As to claim 11, Lowell teaches the invention as claimed including wherein the work items that are processed using the set of identical threads to determine whether there is a fault associated with the programmable execution unit are dedicated work items that are designed to test one or more functional units associated with the programmable execution unit for faults [results of the same, hence designated operations/work items performed by the redundant threads or the fingerprints for the redundant threads can then be compared in detecting or testing for (or, in some cases correct) errors that occur during execution of the redundant threads, paragraph 17, lines 8-12; step 535, Fig. 5 and corresponding text].
As to claims 12-15 and 19-20, Lowell teaches the method of operating a data processor as recited in claims 1-5 and 9-10 therefore Lowell teaches the data processor being operated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 8, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lowell as applied to claims 1 and 12 above, in view of US PG Pub. 2009/0183035 to Butler et al. (hereafter Butler).
Butler was cited in applicant’s IDS filed on 9/6/23.
As to claim 6, Lowell does not specifically teach wherein in response to determining using the comparison that there is a fault associated with the programmable execution unit, the method comprises: (i) re-issuing the set of identical threads for processing the work item for execution by the programmable execution unit, and executing the threads again to perform the processing of the work item in question; and/or (ii) adjusting an operating parameter of the data processor. However, Butler teaches execution units executing the same instruction having mismatch result to be re-executed [paragraphs 7, 36, 40 and 47-48]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modify Lowell with Butler because they are in the same field of endeavor of redundancy checking for error detection.
As to claim 8, Lowell does not specifically teach wherein comprising monitoring an operating environment of the data processor and, in response to detecting a change in the operating environment, triggering fault detecting testing by generating for execution by the execution unit a set of two or more identical execution threads, wherein each of the execution threads in the set of two or more identical execution threads is configured to perform processing for the same work item when executed. However, Butler teaches the changes in between different execution modes and detecting the change to reliable execution mode that triggers redundant instruction execution [paragraphs 7 and 26]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modify Lowell with Butler because they are in the same field of endeavor of redundancy checking for error detection.
As to claims 16 and 18, these claims are rejected for the same reason as claim 6 above.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lowell as applied to claims 1 and 12 above.
As to claim 7, Lowell does not specifically teach wherein the step of generating sets of identical threads for processing the same work item is performed periodically or intermittently during the operation of the data processor. However, Lowell disclosed generation of redundant threads to improve processing unit reliability [paragraph 9] and the attempt to reduce overhead of RMT error detection and correction by comparing results of operations performed by redundant threads intermittently by selectively bypassing the comparison [paragraph 10]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have taken into consideration the overhead of continuously performing error detection/correction to have apply the intermittent approach as being considered by Lowell to the generation of redundant threads to improve Lowell’s teaching by reducing resource consumption without significantly reducing probability of detecting errors.
As to claim 17, this claim is rejected for the same reason as claim 7 above.
Response to Arguments
Applicant's arguments filed 2/19/26 have been fully considered but they are not persuasive.
Applicant argued in substance that:
Lowell describes a software-based approach to redundant multithreading, the redundancy is thus present already in the software code provided to the data processor and there is no specific signaling or control to generate redundant execution threads at the level of the thread generation within the hardware data processor.
Redundant threads are taught to be executed on different processing element as disclosed by Lowell, whereas, in the claimed subject matter, asset of two of more identical execution threads are generated for execution by the same execution unit internally to the data processor.
Examiner respectfully traversed Applicant's remarks:
As to point (a), the examiner respectfully disagree and submit that APD as disclosed by Lowell is a hardware device [paragraph 14] or hardware device implemented RMT [paragraph 20] and that the generating of redundant threads for execution by processing elements of corresponding compute unit(s) is perform by the APD upon identification (i.e. indication or signal of a thread that was inherently generated) of a thread for execution [paragraph 33; Fig. 1 and corresponding text], therefore, mappings of Lowell clearly satisfied the limitations as claimed regardless of whether redundancy is present in software code provided to the data processor.
As to point (b), the examiner respectfully disagree and submit that different processing elements can nonetheless be on the same compute unit of the APD [Fig. 1 and corresponding text] which clearly satisfied the limitations as claimed.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QING YUAN WU whose telephone number is (571)272-3776. The examiner can normally be reached M-F 9AM-6PM EST.
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/QING YUAN WU/Primary Examiner, Art Unit 2199