CTNF 18/323,851 CTNF 81485 DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-8 are presented for examination. Drawings The drawings are objected to as failing to comply with 37 CFR 1.83(a) because the features disclosed in the description and claims should be illustrated in the drawings in a form of graphical drawing symbol or a labeled representation. Element numbers drawn to empty boxes does not provide adequate labeling for Figure(s) 14. Claim Objections Claim 4 line 3 uses the acronym or variable “rtl”, the first use of an acronym or variable in a claim should be defined to avoid any possible indefiniteness issues. Claim 4 line 4 uses the acronym or variable “sdc”, the first use of an acronym or variable in a claim should be defined to avoid any possible indefiniteness issues. Appropriate correction or clarification is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. Claim 1, line(s) 5 set forth features that may or may not occur in the future. The term "can" indicates the lack of a positive recitation of the functionality that is recited for which a potential infringer would know with certainty whether or not he or she would be infringing the recited features. "Can" is merely a potential act that may or may not occur in the future. There is no positive recitation in claim 1 that a delay value is actually applied to each path. The claimed features are only passively recited and not positively recited as actual features within the body of the claim. Furthermore, the cited feature "that can applied" makes the claim indefinite, because it fails to point out the precise meaning of the cited feature. As to claim(s) 6, the same deficiency applies. Dependent claims inherit the defect of the claim from which they depend. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Independent claim 1 Step 1: a method (process = 2019 PEG Step 1 = yes) Independent claim 1 Step 2A, Prong One: Independent claim 1 recites: (b) calculating the delay value that can applied to each path in the logic circuit (mathematical concepts) (c) verifying the logic circuit by detecting the delay value as a logic verification violation (mental concepts) Claim 1 is substantially drawn to mathematical concepts: calculations; and mental concepts: observation, evaluation, judgment, opinion. Information and/or data also fall within the realm of abstract ideas because information and data are intangible. See Electric Power Group 1 ( Electric Power hereinafter): “Information… is an intangible”. As to the limitations "verifying the logic circuit by detecting the delay value as a logic verification violation", under its broadest reasonable interpretation, “detecting… value as a… violation” is a mental concept. The Examiner notes that the limitations "verifying the logic circuit by detecting the delay value as a logic verification violation" are not elaborated but merely repeated in the Specification. If a claim limitation, under its broadest reasonable interpretation, covers mental concepts, then it falls within groupings of abstract ideas (2019 PEG Step 2A, Prong One: Abstract Idea Grouping? = Yes) . Independent claim 1 Step 2A Prong two: As to the limitations “designing a semiconductor device", they are no more than intended use. As to the limitations "(a) interpreting a constraint defining a delay value from a timing constraint", they represent no more than just “apply it” limitations, because they recite only the idea of a solution or outcome, i.e., they fail to recite details of how a solution to a problem is accomplished. As to the limitations “inputting data defining a logic circuit and timing constraint data defining a timing constraint relating to the logic circuit", these limitations describe the concept of “mere data gathering”, which corresponds to the concepts identified as abstract ideas by the courts. Data gathering, including when limited to particular content does not change its character as information, is also within the realm of abstract ideas. Data gathering has not been held by the courts to be enough to qualify as “significantly more”. See Electric Power . This judicial exception is not integrated into a practical application of the exception (2019 PEG Step 2A, Prong Two: Additional elements that integrate the Judicial exception/Abstract idea into a practical application? = NO) . Independent claim 1 Step 2B: As discussed with respect to Step 2A, Prong two, the intended use limitations remain intended use even upon reconsideration, because no actual designing of a semiconductor device is performed in the body of the claim. As discussed with respect to Step 2A, Prong two, limitations reciting only the idea of a solution or outcome are just “apply it” limitations, because they fail to recite details of how a solution to a problem is accomplished. See MPEP 2106.05(f)(1). The limitations are so broad that nothing is known about how the claimed constraint defining a delay value is interpreted. The specification merely reads (underline emphasis added): 'in the step S7_1_0, the computer 1001 interprets the timing constraint (data DF2) described in SDC' (see page 14, lines 9-10). As discussed with respect to Step 2A, the claim recites data gathering, these limitations are recited at a high level of generality; and therefore, remain insignificant extra-solution activity even upon reconsideration. Thus, taken alone the individual additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as an ordered combination adds nothing that is not already present when looking at the additional elements taken individually. There is no indication that their combination improves the functioning of a computer itself or improves any other technology (underline emphasis added). Therefore, the claim does not amount to significantly more than the abstract idea itself (2019 PEG Step 2B: NO) . Claim 6 recites substantially the same elements as claim 1 and is rejected for the same reasons above. Independent claim 6, Step 2A Prong two and 2B: As to the further additional elements a computer; an input device connected to the computer; and an display device connected to the computer, wherein the computer is configured to execute, they are interpreted as drawn to a generic computer. They are recited at a high level of generality and as performing generic computer functions routinely used in computer applications. Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system. The use of a computer to implement the abstract idea of a mathematical or mental algorithm has not been held by the courts to be enough to qualify as “significantly more”. Their collective functions merely provide conventional computer implementation, which is described in the specification as: 'The design system 1000 includes a computer 1001 such as a computer, a display device 1002 connected to the computer 1001, an input device 1003 connected to the computer 1001, and a storage device 1004 connected to the computer 1001' (see page 5, lines 7-11). Dependent claims Step 2A, Prong One: dependent claims further the abstract ideas of their independent claims. (See Independent claim 1, Step 2A, Prong One above). As to the limitations "2/7… (b2) enumerating all combinations of the output-side clock and the input-side clock", under its broadest reasonable interpretation, “enumerating” is a mental concept. The Examiner notes that "enumerat*" is not elaborated but merely repeated in the Specification If a claim limitation, under its broadest reasonable interpretation, covers abstract ideas, then it falls within groupings of abstract ideas (2019 PEG Step 2A, Prong One: Abstract Idea Grouping? = Yes) . Dependent claims Step 2A Prong two: As to the limitations "2/7… (b1) extracting a output-side clock used on the output side for output data and a input-side clock used on the input side for input data in each of the paths… (b3) extracting a clock path involving the output side and the input side", they represent no more than just “apply it” limitations, because transformation of information and/or data is not statutory. They invoke computers or other machinery merely as a tool to perform an existing process. As to the limitations "3/8… wherein the (c) verifying includes a functional verification by hardware and software", they represent no more than just “apply it” limitations, because they recite only the idea of a solution or outcome, i.e., they fail to recite details of how a solution to a problem is accomplished. As to the limitations “4… wherein the data defining the logic circuit is described in RTL, and wherein the timing constraint data is described in SDC" and "5… wherein the data defining the logic circuit is described in netlist, and wherein the timing constraint data is described in SDC”, they further the data gathering of their independent claims. This judicial exception is not integrated into a practical application of the exception (2019 PEG Step 2A, Prong Two: Additional elements that integrate the Judicial exception/Abstract idea into a practical application? = NO) . Dependent claims Step 2B: As discussed with respect to Step 2A, Prong two, limitations invoking computers or other machinery merely as a tool to perform an existing process are just “apply it” limitations. See MPEP 2106.05(f)(2). See for example in the Specification (underline emphasis added): "in the step S7_RT1, the computer 1001 extracts a clock-signal used in a path connecting at least two gates in a logic-circuit defined by a netlist that is a data DF3. Since the logic circuit usually includes a plurality of paths, the computer 1001 extracts a clock signal to be used for each path in the step S7_RT1" (see page 15, lines 17-22). As discussed with respect to Step 2A, Prong two, limitations reciting only the idea of a solution or outcome are just “apply it” limitations, because they fail to recite details of how a solution to a problem is accomplished. See MPEP 2106.05(f)(1). The limitations are so broad that nothing is known about how the claimed functional verification by hardware and software is performed. The Examiner notes that “function*” is not mentioned in the Specification. As discussed with respect to Step 2A, the claims recite data gathering, these limitations are recited at a high level of generality; and therefore, remain insignificant extra-solution activity even upon reconsideration. Therefore, the claims do not amount to significantly more than the abstract idea itself (2019 PEG Step 2B: NO) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23 AIA The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Examiner would like to point out that any reference to specific figures, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention. 07-21 AIA Claim s 1-3 and 6-8 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dmitry Korchemny, (Korchemny hereinafter), U.S. Patent 11386250, taken in view of Meng-Fan Wu, (Wu hereinafter), U.S. Patent 12536363 . As to claim 1, Korchemny discloses a method of designing a semiconductor device (see "During design planning 722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing" in col. 11, lines 17-19) , comprising: (a) interpreting a constraint defining a delay value from a timing constraint (see "setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship" in col. 1, lines 56-58) by inputting data defining a logic circuit (see "the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing" in col. 11, lines 17-19) and timing constraint data defining a timing constraint relating to the logic circuit (see "the mapping sub-system uses… design constraints (e.g., timing or logic constraints)" in col. 14, lines 59-62) ; (b) calculating the delay value that can applied to each path in the logic circuit (see "intra-FPGA path delays are typically accurately computed by FPGA place and route tools" in col. 3, lines 52-54) ; and (c) verifying the logic circuit by detecting the delay value as a logic verification violation (see "During netlist verification 720, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing" in col. 11, lines 17-21). While Korchemny discloses "design planning", Korchemny fails to disclose of designing a semiconductor device . Wu discloses of designing a semiconductor device . (See “A design system or tool such as an ECO system” in col. 11, lines 43-44). Examiner notes that the limitations “designing a semiconductor device" are no more than intended use, because no actual designing of a semiconductor device is performed in the body of the claim. Korchemny and Wu are analogous art because they are related to semiconductor device designs. Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Wu with Korchemny, because Wu describes "solutions that involve a selection of candidate clock points from a clock network and performing a multi-step iterative testing process where different combinations of timing delay adjustment values are tested for impact on negative slack between the candidate clock points…", and as a result, Wu reports that through his "… process, a promising combination of values may be determined which has the most optimized cost, e.g., most total negative slack (TNS) reduction" (see col. 3, line 62 to col. 4, line 2). As to claim 2, Korchemny discloses wherein the (b) calculating comprises… (b2) enumerating all combinations of the output-side clock and the input-side clock (see "Each clock signal has a pattern defined by the clock's high level durations and low level durations. Both the high and low level durations are defined as multiples of EC cycles. A clock pattern defined, for example, by 001, indicates that the clock is at a low level for two EC cycles, and is then at a high level for one EC cycle" in col. 4, line 65 to col. 5, line 4) ; and Wu discloses (b1) extracting a output-side clock used on the output side for output data and a input-side clock used on the input side for input data in each of the paths… (b3) extracting a clock path involving the output side and the input side (see "output/input" as "source or a sink", 'FIG. 3 is a block diagram illustrating examples of paths in which setup time violation may occur… various clock points (also referred to as “seeds”) branch off from one another… clock points may be a clock source or a sink node (having, e.g., one or more registers), which may branch out from and exist along clock paths of an IC design. Some clock points are downstream of others, and there may be multiple downstream clock points, with multiple levels through the topology… a clock network may include clock points that branch into many leaf-level “endpoints” (e.g., clock points G, H, I, J), where timing violations may accumulate down a set of clock paths' in col. 6, lines 8-39) ; and (b4) calculating a minimum delay value that allows data to be transmitted between the output side clock and the input side clock (see "hold time violations at modules A and B (when an input signal changes too soon after the clock's active transition, violating time required for data to be available after clock edge captures data)" in col. 5, lines 36-39). Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Wu with Korchemny, (see supra). As to claim 3, Korchemny discloses wherein the (c) verifying includes a functional verification by hardware and software (see "During logic design and functional verification 716, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy… functional verification may use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers… special systems of components referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification" in col. 10, line 59 to col. 11, line 3). As to claims 6-8, these claims recite a logic circuit designing apparatus comprising: a computer; an input device connected to the computer; and an display device connected to the computer for performing the method of claims 1-3. Korchemny discloses a 'computer system' (see col. 16, lines 41-44) for performing a method that teaches claims 1-3. Therefore, claims 6-8 are rejected for the same reasons given above . 07-22 AIA Claim s 4 and 5 are rejected under 35 U.S.C. 103(a) as being unpatentable over Korchemny taken in view of Wu as applied to claim 3 above, and further in view of Giuseppe Fomaciari, (Fomaciari hereinafter), U.S. Patent 7490307 . As to claim 4, while Korchemny discloses wherein the data defining the logic circuit is described in RTL (see "the DUT description is in a description language (e.g., a register transfer language (RTL))" in col. 13, lines 13-14) , Korchemny and Wu do not disclose wherein the timing constraint data is described in SDC. Fomaciari discloses wherein the timing constraint data is described in SDC (see "automate the merging of timing constraints of stored logic between the functional design and the test structures… automatically generate scripts 108 which take into account merged timing constraints of the stored logic between the functional design and test structures. Such merged timing constraints may be compliant with Synopsis® Design Constraints (SDC)" in col. 6, lines 4-11). Korchemny, Wu, and Fomaciari are analogous art because they are related to semiconductor device designs. Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Fomaciari with Korchemny and Wu, because Fomaciari discloses "automatic generation of timing constraints for the validation/signoff of test structures that may…", and as a result, Fomaciari reports to "… (vi) provide an optimal trade-off between timing accuracy and simple constraint description to achieve global optimization in a single-shot run" (see col. 2, lines 43-56). As to claim 5, Korchemny discloses wherein the data defining the logic circuit is described in netlist (see "the DUT description is in netlist level" in col. 13, lines 13-14) , and Fomaciari discloses wherein the timing constraint data is described in SDC (see "automate the merging of timing constraints of stored logic between the functional design and the test structures… automatically generate scripts 108 which take into account merged timing constraints of the stored logic between the functional design and test structures. Such merged timing constraints may be compliant with Synopsis® Design Constraints (SDC)" in col. 6, lines 4-11). Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Fomaciari with Korchemny and Wu, (see supra ). Conclusion Examiner would like to point out that any reference to specific figures, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUAN CARLOS OCHOA whose telephone number is (571)272-2625. The examiner can normally be reached Mondays, Tuesdays, Thursdays, and Fridays 9:30AM - 8:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Chavez can be reached at 571-270-1104. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JUAN C OCHOA/Primary Examiner, Art Unit 2186 Application/Control Number: 18/323,851 Page 2 Art Unit: 2186 Application/Control Number: 18/323,851 Page 3 Art Unit: 2186 Application/Control Number: 18/323,851 Page 4 Art Unit: 2186 Application/Control Number: 18/323,851 Page 5 Art Unit: 2186 Application/Control Number: 18/323,851 Page 6 Art Unit: 2186 Application/Control Number: 18/323,851 Page 7 Art Unit: 2186 Application/Control Number: 18/323,851 Page 8 Art Unit: 2186 Application/Control Number: 18/323,851 Page 9 Art Unit: 2186 Application/Control Number: 18/323,851 Page 10 Art Unit: 2186 Application/Control Number: 18/323,851 Page 11 Art Unit: 2186 Application/Control Number: 18/323,851 Page 12 Art Unit: 2186 1 Electric Power Group , LLC v. Alstom S.A., 119 USPQ2d 1739 Fed. Cir. 2016
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