DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-3, 5-14, and 16-20 are pending.
The U.S.C. 112 rejections have been corrected and the rejections are withdrawn.
Claim Interpretation
Based on the Applicant’s response regarding claim 3 relating to being their own lexicographer, “a regulation amplitude” will be interpreted as “the regulation amplitudes may include one or more of a frequency reduction multiple corresponding to the operating clock, a quantity of periodicities that the operating clock waits for, a voltage reduction multiple corresponding to the operating voltage, a frequency increase multiple corresponding to the operating clock, a quantity of periodicities that are advanced for the operating clock, and a voltage increase multiple corresponding to the operating voltage”, [0091]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 7-12, 14, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rusu et al. (US 20030065960) in view of Nemani et al. (US 20160070327) and Horigan et al. (US 6304978).
Regarding claim 1, Rusu teaches
A power consumption control apparatus, comprising a constant-frequency clock generator ([0034], “a low frequency clock) and a power consumption regulator (Fig. 2 (108 – controller), wherein the power consumption regulator is connected to two or more processing units in a system-on-a-chip (SoC); (Figs. 1 and 2, [0024], “ By including one embodiment of the present invention on the system on a chip, the frequency/voltage controller can adjust the processor frequency and voltage to minimize power dissipation.”)
the constant-frequency clock generator is configured to generate a constant-frequency clock signal and provide the constant-frequency clock signal to the power consumption regulator; and ([0034], “the controller 108 operates on a low frequency clock that is independent of the main processor clock. The controller reads the power sensor value and the software control register during normal operation. The sensor value and register contents are evaluated with the fuse tables in order to compute a new voltage/frequency operating point for the processor.”)
the power consumption regulator is configured to: obtain, based on the constant- frequency clock signal used as an operating clock, power consumption caused by the two or more processing units in a first period of time, and regulate power consumption of the two or more processing units in a second period of time based on the power consumption in a first time period. (Fig. 3, [0034], “the controller 108 operates on a low frequency clock that is independent of the main processor clock. The controller reads the power sensor value and the software control register during normal operation. The sensor value and register contents are evaluated with the fuse tables in order to compute a new voltage/frequency operating point for the processor.”, [0030], “During normal operation, controller 108 reads in a sensor value and determines how much power the processor 102 is consuming. The controller 108 compares this power consumption value with the stored operating points loaded from the fuse array 214 to determine what processor frequency and voltage points will allow for optimal performance while remaining within the allowable or tolerable power and thermal envelope.” And [0038], “The mechanism outputs the new frequency and voltage settings at step 314. These settings have been picked based on the desired operating point. For one embodiment, the settings are chosen to provide optimal processor efficiency while minimizing processor power dissipation. At step 316, the new frequency and voltage settings take effect at the clock generator and the power supply, respectively.”)
determine a preset current indicator based on the power consumption caused by the two or more processing units in the first period of time, ([0036], “After the controller is configured, the mechanism enters into normal operation. At step 304, the sensors are queried. The number and type of sensors used depends on the particular embodiment. For example, the sensor may sense current, power, temperature, or processing load.” And [0037], “The mechanism determines how much power the processor is consuming. Based on the processor power consumption is, the controller can find an appropriate operating point for the processor. At step 312, the mechanism decides whether the operating point of the processor should be adjusted. The controller of this embodiment compares the power consumption value with a table of values stored in memory to determine what the frequency and voltage should be set at. … The mechanism determines how much power the processor is consuming. Based on the processor power consumption is, the controller can find an appropriate operating point for the processor. At step 312, the mechanism decides whether the operating point of the processor should be adjusted. The controller of this embodiment compares the power consumption value with a table of values stored in memory to determine what the frequency and voltage should be set at.”)
Rusu teaches measuring current/power consumption periodically but does not specifically teach controlling the power consumption for a second time period based on a first time period with a common power regulator.
Nemani teaches obtain, based on the constant-frequency clock signal used as an operating clock, power consumption caused by the two or more processing units in a first period of time, and regulate power consumption (Fig. 2 (26 - DCVS Module) of the two or more processing units in a second period of time based on the power consumption in a first time period based on the power consumption in a first time period. ([0059], “The PCM module 101 may leverage knowledge of current consumption over recent sub-durations into a voltage regulator 189 to determine a current budget for a next sub-duration and direct a DCVS module 26 to adjust power consumption levels of one or more processing components (such as GPU 182 and CPU 110).”, [0064], “monitor module 114 may also monitor power sensors 157B for current consumption rates uniquely associated with the cores 222, 224, 230 and transmit the power consumption data to the PCM module 101 and/or a database (which may reside in memory 112). The PCM module 101 may work with the monitor module 114 to determine available current budgets for upcoming sub-durations and make adjustments to power consumption levels of processing components residing on the SoC 102” and [0094], “At block 515, a moving sum of the active current input is calculated for the most recent (N−1) sub-durations. At block 520, a remaining current budget for the Nth sub-duration may be calculated by subtracting the sum calculated at block 515 from the maximum allowable current consumption over N sub-durations. Next, at decision block 525, the remaining current budget for the Nth sub-duration may be compared to the active current input required by the processing components for the Nth sub-duration. … If the remaining current budget is less than the required active current input, however, the “no” branch is followed to block 535 and throttling to one or more processing components is increased in an effort to maintain the total current consumption over the duration beneath a peak current threshold.”)
Rusu and Nemani are analogous art. Nemani is cited to teach a similar concept of power management using throttling. Nemani teaches measuring peak current periodically to control power consumption and limit overcurrent. Based on Nemani, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Rusu to consider peak current within durations and subdurations when determining whether to throttle or not. Furthermore, being able to limit calculated/predicted peak current by throttling or not improves on Rusu by being able to improve QOS in a system. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “the better algorithms for managing power consumption on a SoC may minimize performance degradation of the processing components while avoiding significant di/dt events”, [0025]
Rusu and Nemani teach a preset current indicator based on power consumption of a first time period but do not teach that the preset current indicator compromises a current rate of change indicator
Horigan teaches
determine a preset current indicator based on the power consumption caused by the two or more processing units in the first period of time, wherein the preset current indicator comprises a current change rate indicator and (col. 5, lines 40-44, “The current change response circuit 250 generates a throttle signal on a signal line 262 to throttle the processor 205 when a change in current supplied exceeds a threshold value.” And col. 6, “a current consumption change event may be detected. Two examples of such current change event detection are shown in blocks 315 and 320. In block 315, one embodiment senses when the rate of change of current (di/dt) exceeds a threshold or predetermined value.” Where the adaptive throttling includes a multiple time periods (i.e. a first time period and a second time period))
regulate power consumption of the two or more processing units in a second period of time based on the present current indicator (col. 6, lines 54-61, “ a predetermined response may be used to control the rate of change of current based on one or more readings of the initial rate of change of current (see also discussion with respect to FIG. 2). Alternatively, adaptive throttling may be used as shown in block 345. Adaptive throttling continues sampling the current and adjusting throttling of the component operation until a steady state is reached as shown in block 350.” And (col. 5, lines 40-44, “The current change response circuit 250 generates a throttle signal on a signal line 262 to throttle the processor 205 when a change in current supplied exceeds a threshold value.” Where the adaptive throttling includes a multiple time periods (i.e. a first time period and a second time period))
Rusu, Nemani, and Horigan are analogous art. Horigan is cited to teach a similar concept of power management using throttling. Horigan teaches using a rate of change of current to periodically to control power consumption. Based on Horigan, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Rusu and Nemani to measure and adjust the rate of current within durations when determining whether to throttle the processors or not. Furthermore, being able to limit rate of current by throttling or not improves on Rusu and Nemani by being able to reduce the size of the power supply in the system. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “[b]y controlling or limiting the rate of change of current consumption for an electronic device, one may advantageously reduce the cost and/or size of the power supply required to operate that device.”, col. 1, lines 15-18
Regarding claim 3, Rusu teaches wherein the power consumption regulator is specifically configured to:
determine a value of the two or more processing units in a preset current indicator based on the power consumption caused by the two or more processing units in the period of time; and ([0036], “After the controller is configured, the mechanism enters into normal operation. At step 304, the sensors are queried. The number and type of sensors used depends on the particular embodiment. For example, the sensor may sense current, power, temperature, or processing load.”)
when the value of the two or more processing units in the preset current indicator meets a first regulation threshold corresponding to the preset current indicator, regulate the current power consumption of the two or more processing units based on a regulation amplitude corresponding to the first regulation threshold, wherein the first regulation threshold is one of at least two regulation thresholds corresponding to the preset current indicator, and each of the at least two regulation thresholds corresponds to one regulation amplitude. (Fig. 3, [0037], “The mechanism determines how much power the processor is consuming. Based on the processor power consumption is, the controller can find an appropriate operating point for the processor. At step 312, the mechanism decides whether the operating point of the processor should be adjusted. The controller of this embodiment compares the power consumption value with a table of values stored in memory to determine what the frequency and voltage should be set at. … The mechanism determines how much power the processor is consuming. Based on the processor power consumption is, the controller can find an appropriate operating point for the processor. At step 312, the mechanism decides whether the operating point of the processor should be adjusted. The controller of this embodiment compares the power consumption value with a table of values stored in memory to determine what the frequency and voltage should be set at.”)
Regarding claim 7, Nemani teaches further comprising a storage circuit connected to the power consumption regulator; the storage circuit is configured to store, based on a preset periodicity, power consumption caused by the one or more processing units in each periodicity; and the power consumption regulator is further configured to: obtain, from the storage circuit, power consumption caused by the one or more processing units in any periodicity, and use the power consumption as the power consumption caused by the one or more processing units in the period of time. ([0064], “monitor module 114 may also monitor power sensors 157B for current consumption rates uniquely associated with the cores 222, 224, 230 and transmit the power consumption data to the PCM module 101 and/or a database (which may reside in memory 112). The PCM module 101 may work with the monitor module 114 to determine available current budgets for upcoming sub-durations and make adjustments to power consumption levels of processing components residing on the SoC 102” and [0093], “a duration of time over which a peak current threshold into a voltage regulator must not be exceeded is sub-divided into a number of “N” sub-durations. … Next, at block 510 current sensor(s) may be monitored and the amount of active current input to the voltage regulator 189 measured for each sub-duration. Notably, the active current input to the voltage regulator 189 may essentially equate to the total current consumption over a period of time by processing components residing on a SoC 102”)
Regarding claim 8, Nemani teaches wherein the storage circuit comprises K memories, the K memories respectively correspond to K preset periodicities, and K is a positive integer greater than or equal to 2; and any one of the K memories is configured to store, based on a preset periodicity corresponding to the memory, power consumption caused by the one or more processing units in each preset periodicity corresponding to the memory. ([0064], “the PCM module 101 may use the monitored data to determine throttling adjustments that are directed to the DCVS module 26 for application. Through application of the throttling adjustments, the PCM module 101 may effectively optimize user experience by maintaining current consumption beneath a peak current threshold associated with the voltage regulator 189 without unnecessarily reducing power consumption.” [0064], “monitor module 114 may also monitor power sensors 157B for current consumption rates uniquely associated with the cores 222, 224, 230 and transmit the power consumption data to the PCM module 101 and/or a database (which may reside in memory 112). The PCM module 101 may work with the monitor module 114 to determine available current budgets for upcoming sub-durations and make adjustments to power consumption levels of processing components residing on the SoC 102” and [0086], “The memory 112 is a non-volatile data storage device such as a flash memory or a solid-state memory device. Although depicted as a single device, the memory 112 may be a distributed memory device with separate data stores”)
Regarding claim 11, Rusu teaches the power consumption control apparatus is connected to the one or more processing units; (Fig. 1 (108)) and the power consumption control apparatus is configured to regulate current power consumption of the one or more processing units based on power consumption caused by the one or more processing units in a period of time.(Fig. 3, [0034], “the controller 108 operates on a low frequency clock that is independent of the main processor clock. The controller reads the power sensor value and the software control register during normal operation. The sensor value and register contents are evaluated with the fuse tables in order to compute a new voltage/frequency operating point for the processor.” And [0037], “The mechanism determines how much power the processor is consuming. Based on the processor power consumption is, the controller can find an appropriate operating point for the processor. At step 312, the mechanism decides whether the operating point of the processor should be adjusted. The controller of this embodiment compares the power consumption value with a table of values stored in memory to determine what the frequency and voltage should be set at.”)
Regarding claim 20, Nemani teaches wherein the method further comprises: for any one of the two or more processing units, obtaining power consumption signals of each processor core in the processing unit in each time period, obtaining, through calculation based on the power consumption signals, power consumption caused by the processor core in each of a plurality of time periods, and accumulating power consumption caused by processor cores in the processing unit in a same time period, to obtain power consumption caused by the processing unit in each of the plurality of time periods; and accumulating power consumption caused by the two or more processing units in time periods of one periodicity, to obtain the power consumption caused by the two or more processing units in each periodicity.([0064], “Returning to the FIG. 2 illustration, the monitor module 114 monitors a signal from one or more current sensors 157B to track power consumption of active components associated with the various rails. In some embodiments, the data tracked by the monitor module 114 may be continuously updated and stored in a database such that historical power consumption levels may be accessed by a PCM module 101 and used to accurately determine an available current budget for a next sub-duration of time.”)
As to claim 12, Horigan, Rusu and Nemani teaches this claim according to the reasoning provided in claim 1.
As to claim 14, Horigan, Rusu and Nemani teaches this claim according to the reasoning provided in claim 3.
As to claim 18, Horigan, Rusu and Nemani teach this claim according to the reasoning provided in claim 7.
As to claim 19, Horigan, Rusu and Nemani teach this claim according to the reasoning provided in claim 8.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rusu, Nemani, and Horigan as applied to claim 1 above, and further in view of Kim (US 20150113304).
Regarding claim 2, Rusu, Nemani, and Horigan do not teach but Kim teaches wherein the two or more processing units are located in a same voltage domain, and different processing units in the one or more processing units use different operating clocks. ([0046], “ Each processor core 22 may receive common electrical power 24 (for example, of a single voltage domain) and may provide for various address, data, and control lines 26, as is generally understood in the art, allowing for reading and writing of the memory 14 and the communication with other hardware of the processing system 12 shared by the processor cores 22, such as a power control unit (not shown).” And [0048], “the processing system 12 may receive a common clock signal 28 providing a timing signal for synchronous circuits within the cores 22. This common clock signal 28 may be connected to multiple phase locked loop systems 30 associated with each processor core 22, the phase locked loop systems 30 operating to multiply the frequency of the clock signal 28 upward for use by the processor core 22”)
Rusu, Nemani, Horigan and Kim are analogous art. Kim is cited to teach a similar concept of power management using throttling. Kim teaches providing a common voltage domain to core processing units while using individual throttle/frequency control for the core processing units and throttling cores during specific times to reduce power consumption. Based on Kim, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Rusu, Nemani, and Horigan to use a shared voltage domain but all for individual control of the clock frequency of the core processing units. Furthermore, using this configuration improves on Rusu, Nemani, and Horigan by individually on a per core basis reduce power consumption in a processor. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “The process of reducing processor core 22 functions reduces the power demand of the processor core 22 at the time of changing the frequency of output clock signal 40.”, [0062]
Claim(s) 6 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rusu, Nemani, and Horigan as applied to claim 1 above, and further in view of Muccini et al. (US 20210089106)
Regarding claim 6, Rusu, Nemani, and Horigan do not teach but Muccini teaches wherein when the preset current indicator comprises the current change rate indicator, when a current change rate of the one or more processing units in the period of time meets a plurality of regulation thresholds corresponding to the current change rate indicator, the first regulation threshold is a regulation threshold with a largest absolute value in the plurality of regulation thresholds that are met. ([0025], “ In particular, current slew-rate detector module 140 includes signal processing circuits that operate to detect and characterize the current slew-rate. Then, when the current slew-rate exceeds a one or more slew-rate threshold, current slew-rate detector module 140 operate to provide indications to BMC 122 via the I2C interface. Here, current slew-rate detector module 140 may implement multiple current slew-rate thresholds, as needed or desired. Here, when the current slew-rate exceeds a first threshold, current slew-rate detector module 140 will provide a warning indication that the current slew-rate is increasing, but is not at an alert level. When the current slew-rate exceeds a second threshold, current slew-rate detector module 140 will provide a warning indication that the current slew-rate has increased beyond the warning level to the alert level. Finally, when the current slew-rate exceeds a third threshold, current slew-rate detector module 140 will provide a critical indication that the current slew-rate is above the critical level.”)
Rusu, Nemani, Horigan, and Muccini are analogous art. Muccini is cited to teach a similar concept of power management using throttling. Muccini teaches providing a plurality of current rate change thresholds to determine power management actions. Based on Muccini, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Rusu, Nemani, and Horigan to use a plurality of thresholds to determine power management actions. Furthermore, using this configuration improves on Rusu, Nemani, and Horigan by improving when to throttle the system and by how much. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “BMC 122 operates to filter out hardware faults that would tend to unnecessarily exercise the throttling functions of power control system 100, permitting the power control system to tide through minor current slew-rate issues. Additionally, BMC 122 operates to provide indications to a user of the information handling system that current slew-rate issues may be responsible for throttling events or other impacts to system performance.”, [0027]
Response to Arguments
Applicant's arguments filed 12/19/2025 have been fully considered but they are not persuasive. The Applicant’s representative argues that Rusu and Nemani do not disclose the sensor can sense the change rate of current and therefore does not disclose “determining a preset current indicator”. The Examiner disagrees. Rusu is used to teach that the preset current indicator is set based on the current or power but does not teach a rate of change. On the other hand, recited in the Non-Final Office action of 09/25/2025, Horigan states “(col. 5, lines 40-44, “The current change response circuit 250 generates a throttle signal on a signal line 262 to throttle the processor 205 when a change in current supplied exceeds a threshold value.” And col. 6, “a current consumption change event may be detected. Two examples of such current change event detection are shown in blocks 315 and 320. In block 315, one embodiment senses when the rate of change of current (di/dt) exceeds a threshold or predetermined value.” Horigan teaches that one would want to measure and regulate a current rate of change in a processor system. The idea that a current rate of change could be used (as taught by Horigan) is combined with determining the current preset indicator based on power consumption as taught by Rusu. Additionally, Horigan and not Rusu (as the Applicant’s representative argues) is used to regulate the power consumption using a current change rate indicator, as show above, in claim 1. Therefore, the combination of Rusu and Horrigan teach these limitations as recited in the independent claims. The Applicant’s arguments are not persuasive and the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p.
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/CHERI L HARRINGTON/Examiner, Art Unit 2176 March 31, 2026
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176