DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s remarks and amendments filed 12/16/25 have been entered and considered. Claims 2, 3, 5-7, 14 and 17 have been cancelled. Newly admitted claims 21-25 have been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 15, 16, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Malhan et al (US 2010/0025693 A1).
Regarding claim 1, Malhan et al discloses a method of making a power device (Figure 2), the method comprising: forming a substrate layer (Figure 2, reference 1), wherein the substrate layer comprises a doped semiconductor material (Figure 2, reference 1; paragraph 0038) and a highly doped region (Figure 2, reference 4); forming a drift region (Figure 2, reference 2) of a high voltage diode (Figure 2, reference R2) in the substrate layer (Figure 2, reference 1), wherein a doping concentration of the highly doped region (Figure 2, reference 4) is greater than a doping concentration of the drift region (Figure 2, reference 2; paragraph 0038) and wherein the highly doped region (Figure 2, reference 4) in the substrate (Figure 2, reference 1) is doped with a first conductivity type (paragraph 0038), and the drift region is doped with the first conductivity type (Figure 2, reference 2; paragraph 0038); forming a wide-bandgap semiconductor transistor (Figure 2, reference R1) over, and in physical contact with, a first section (Figure 2, area below reference R1 above reference 2) of a first surface of the substrate layer (Figure 2, reference 2 uppermost portion), wherein the first section includes at least part of the drift region (Figure 2, reference 2) of the high voltage diode (Figure 2, reference R2); forming a first terminal (Figure 2, reference 14) over a second section (Figure 2, area below reference R2 above reference 2) of the first surface of the substrate layer (Figure 2, reference 2); forming a second terminal (Figure 2, reference 13) over a second surface of the substrate layer, wherein the second surface is opposite the first surface (Figure 2, reference 1; lower portion); wherein the method comprises forming the drift region (Figure 2, reference 2) and the first (Figure 2, reference 14) and the second terminal (Figure 2, reference 13) such that a high voltage diode (Figure 2, reference R2) is formed in the substrate layer (Figure 2, reference 1), wherein at least part of the diode (Figure 2, reference R2) is located below at least part of the wide-bandgap semiconductor transistor (Figure 2, reference R1).
Regarding claim 4, Malhan et al discloses wherein the drift region comprises a doped semiconductor material with a first conductivity type (Figure 2, reference 2); and wherein forming the first terminal on the substrate layer comprises: forming a recess (Figure 2, reference 10c) in the wide-bandgap semiconductor transistor over the second section (Figure 2, area below reference R2 above reference 2) of the substrate (Figure 2, reference 1); and implanting a highly doped region of a second conductivity type (Figure 2, references 15, 16a and 16b) in the second section (Figure 2, area below reference R2 above reference 2) of the substrate layer (Figure 2, reference 1), wherein the second conductivity type (Figure 2, p-type) is different to the first conductivity type (Figure 2, n-type); and forming a contact (Figure 2, reference 14) over the highly doped region (Figure 2, references 15, 16a and 16b).
Regarding claim 15, Malhan et al discloses wherein: the first conductivity type is p-type (Figure 2, reference 2, interchangeable); the first terminal is a cathode terminal (Figure 2, reference 14) of the diode (Figure 2, reference R2); and the second terminal is an anode terminal (Figure 2, reference 13) of the diode (Figure 2, reference R2).
Regarding claim 16, Malhan et al discloses wherein: the first conductivity type is n-type (Figure 2, reference 2); the first terminal is a cathode terminal (Figure 2, reference 14) of the diode (Figure 2, reference R2); and the second terminal is an anode terminal (Figure 2, reference 13) of the diode (Figure 2, reference R2).
Regarding claim 19, Malhan et al discloses wherein the drift region (Figure 2, reference 2) in the substrate layer (Figure 2, reference 1) comprises forming a superjunction structure, wherein the superjunction structure comprises alternating n doped and p doped layers (Figure 2, reference 5).
Regarding claim 20, Malhan et al discloses where forming the second terminal (Figure 2, reference 13)comprises: forming a Schottky contact (Figure 2, reference 14; paragraph 0044) over a second surface of the substrate layer (Figure 2, reference 1, lowermost portion).
Allowable Subject Matter
Claims 8-13, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest method of making a power device, the method comprising: wherein: the first conductivity type is p-type; and forming the first terminal comprises: forming a recess in the wide-bandgap semiconductor transistor over the second section of the substrate; and forming a Schottky contact over the second section of the substrate layer; wherein the first terminal is a cathode terminal of the diode (claim 8) and wherein: the first conductivity type is n-type; and forming the first terminal comprises: forming a recess in the wide-bandgap semiconductor transistor over the second section of the substrate; and forming a Schottky contact over the second section of the substrate layer; wherein the first terminal is an anode terminal of the diode (claim 11) both incorporated into independent claim 1 and in the context of its recited process, along with its depending claims.
Claims 21-25 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: The prior art does not disclose not fairly suggest methods of making a power devices, the methods comprising: wherein forming the second terminal on the substrate layer comprises: forming a recess in the wide-bandgap semiconductor transistor over the third section of the substrate; implanting a second highly doped region of the first conductivity type in the third section of the substrate layer, and forming a contact over the second highly doped region; and forming the drift region and the first and the second terminal such that a high voltage diode is formed in the substrate layer, wherein at least part of the diode is located below at least part of the wide-bandgap semiconductor transistor (claim 21) and wherein at least part of the diode is located below at least part of the wide-bandgap semiconductor transistor; and wherein: the wide-bandgap semiconductor transistor is a gallium nitride high electron mobility transistor (GaN HEMT); and the doped semiconductor material is silicon carbide (claim 24) as described in the independent claims and in the context of their recited processes, along with their depending claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Applicant did not include all allowable claimed subject matter in to the independent claim. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
March 11, 2026