Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Application filed on 5/26/2023 and IDS filed on 2/3/2025. Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recited “configuring N sets of OPC test patterns with different pattern densities, where N is greater than or equal to 2; and creating the OPC model by utilizing the OPC test patterns, the OPC model comprising variation of a critical dimension (CD) of a test pattern with pattern density”, however it is not apparent how configuring N sets of OPC test patterns with different pattern densities would result in a OPC model with variation in critical dimension.
As per claims 2-20 are rejected to for incorporating the above limitations into the claims by dependency.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claim(s) 1-7, 9-17, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parikh et al. (U.S. Pub. No. 2006/0141366 A1).
As per claim 1, Parikh discloses:
A modeling method for an optical proximity correction (OPC) model, the modeling method comprising:
configuring N sets of OPC test patterns with different pattern densities, where N is greater than or equal to 2 (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[prior art include different test patterns with different spacing between patterns – correlate the to the test patterns as cited above]) ; and
creating the OPC model by utilizing the OPC test patterns, the OPC model comprising variation of a critical dimension (CD) of a test pattern with pattern density (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 2, Parikh discloses all of the features of claim 1 as discloses above wherein Parikh also discloses wherein each of the sets of OPC test patterns with different pattern densities at least comprises a primary pattern P.sub.i and at least one auxiliary pattern A.sub.i each provided around the primary pattern P.sub.i at a distinct designed distance from the primary pattern P.sub.i (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[Figure 4, i.e. pattern 412 and 414]).
As per claim 3, Parikh discloses all of the features of claim 2 as discloses above wherein Parikh also discloses wherein creating the OPC model by utilizing the OPC test patterns comprises: collecting wafer data for each of the sets of OPC test patterns with different pattern densities, wherein the wafer data comprises an actual on-wafer CD of the primary pattern P.sub.i, and based on the wafer data, establishing a mapping relationship reflecting variation of the actual on-wafer CD of the primary pattern P.sub.i with pattern density of OPC test patterns, as the OPC model (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 4, Parikh discloses all of the features of claim 3 as discloses above wherein Parikh also discloses wherein the pattern density comprises local pattern density or global pattern density (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[prior art include pattern density (Figure 4), consider local pattern density]).
As per claim 5, Parikh discloses all of the features of claim 4 as discloses above wherein Parikh also discloses wherein the local pattern density is a percentage of an aggregate area of a plurality of auxiliary patterns A.sub.i within a predetermined region in an area of the predetermined region (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[Figure 4, i.e. pattern 412 and 414]).
As per claim 6, Parikh discloses all of the features of claim 5 as discloses above wherein Parikh also discloses wherein the predetermined region has a size of X*Y, where X ranges from 30 nm to 1000 nm, and Y ranges from 30 nm to 1000 nm (See Para [0034], i.e. around 90 nm areas or less).
As per claim 7, Parikh discloses all of the features of claim 3 as discloses above wherein Parikh also discloses wherein the mapping relationship reflecting variation of the actual on-wafer CD of the primary pattern P.sub.i with pattern density of OPC test patterns comprises: a function describing variation of the actual on-wafer CD of the primary pattern P.sub.i with a designed area of an auxiliary pattern A.sub.i and a designed distance between the primary pattern P.sub.i and the auxiliary pattern A.sub.i; and/or a function describing variation of the actual on-wafer CD of the primary pattern P.sub.i with a ratio of a designed area of an auxiliary pattern A.sub.i within a predetermined region to an area of the predetermined region (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 9, Parikh discloses all of the features of claim 7 as discloses above wherein Parikh also discloses wherein the distance between the primary pattern P.sub.i and the auxiliary pattern A.sub.i is not greater than 100 times the CD of the primary pattern P.sub.i. (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[Figure 4, i.e. pattern 412 and 414]).
As per claim 10, Parikh discloses:
A modeling system for an optical proximity correction (OPC) model, which is used to implement the modeling method of claim 1, the modeling system (See claim 1) comprising: an OPC test pattern configuration module for configuring N sets of OPC test patterns with different pattern densities, where N is greater than or equal to 2, each of the sets of OPC test patterns with different pattern densities(See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[prior art include different test patterns with different spacing between patterns – correlate the to the test patterns as cited above]) at least comprising a primary pattern P.sub.i and at least one auxiliary pattern A.sub.i each provided around the primary pattern P.sub.i at a distinct designed distance from the primary pattern P.sub.i (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[Figure 4, i.e. pattern 412 and 414]); and a model creation module for collecting wafer data for each of the sets of OPC test patterns with different pattern densities, which comprises an actual on-wafer critical dimension (CD) of the primary pattern P.sub.i, and based on the wafer data, establishing a mapping relationship reflecting variation of the actual on-wafer CD of the primary pattern P.sub.i with pattern density of OPC test patterns, as the OPC model (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 11, Parikh discloses:
An optical proximity correction (OPC) method, comprising: creating an OPC model using a modeling method of claim 1 (See claim 1), which adds a mapping relationship between a critical dimension (CD) of a pattern and pattern density-related variables (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature); determining a test layout corresponding to a prefabricated layout, which has at least one pattern to be corrected, and determining pattern density of the pattern to be corrected in the test layout using a predefined pattern detection strategy (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047]); and based on the determined pattern density and the mapping relationship in the OPC model, determining a CD correction amount for the pattern to be corrected for the current OPC run and performing an OPC operation on the pattern to be corrected according to the CD correction amount (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 12, Parikh discloses all of the features of claim 11 as discloses above wherein Parikh also discloses wherein the mapping relationship that adds the mapping relationship between the CD of the pattern and the pattern density-related variables comprises: a function describing variation of an actual on-wafer CD of a primary pattern P.sub.i with a designed area of an auxiliary pattern A.sub.i and a designed distance between the primary pattern P.sub.i and the auxiliary pattern A.sub.i; and/or a function describing variation of an actual on-wafer CD of a primary pattern P.sub.i with a ratio of a designed area of an auxiliary pattern A.sub.i within a predetermined region to an area of a predetermined region (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 13, Parikh discloses all of the features of claim 12 as discloses above wherein Parikh also discloses wherein determining the pattern density of the pattern to be corrected in the test layout using the predefined pattern detection strategy comprises: detecting an area of a surrounding pattern of the pattern to be corrected, and determining an area value of the surrounding pattern whose area is greater than a predetermined threshold and a distance between the surrounding pattern and the pattern to be corrected (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 14, Parikh discloses all of the features of claim 13 as discloses above wherein Parikh also discloses wherein determining the CD correction amount for the pattern to be corrected for the current OPC run based on the determined pattern density and the mapping relationship in the OPC mode comprises: inputting the area value and the distance to the function in the OPC model that describes variation of the actual on-wafer CD of the primary pattern P.sub.i with the designed area of the auxiliary pattern A.sub.i and the designed distance between the primary pattern P.sub.i and the auxiliary pattern A.sub.i and taking a difference between an output of the function and a designed CD for the pattern to be corrected as the CD correction amount for the pattern to be corrected for the current OPC run (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 15, Parikh discloses all of the features of claim 14 as discloses above wherein Parikh also discloses wherein determining the pattern density of the pattern to be corrected in the test layout using the predefined pattern detection strategy comprises: setting a predetermined region around the pattern to be corrected, the predetermined region encompassing the pattern to be corrected and a plurality of surrounding patterns each spaced from the pattern to be corrected at a certain distance; and determining an area of the predetermined region and an aggregate area of all the surrounding patterns except for the pattern to be corrected contained in the predetermined region (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 16, Parikh discloses all of the features of claim 15 as discloses above wherein Parikh also discloses wherein determining the CD correction amount for the pattern to be corrected for the current OPC run based on the determined pattern density and the mapping relationship in the OPC mode comprises: inputting the area of the predetermined region and the aggregate area of all the surrounding patterns except for the pattern to be corrected contained in the predetermined region to the function in the OPC model that describes variation of the actual on-wafer CD of the primary pattern P.sub.i with the ratio of the designed area of the auxiliary pattern A.sub.i within the predetermined region to the area of the predetermined region and taking a difference between an output of the function and the designed CD for the pattern to be corrected as the CD correction amount for the pattern to be corrected for the current OPC run (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 17, Parikh discloses all of the features of claim 16 as discloses above wherein Parikh also discloses wherein determining the CD correction amount for the pattern to be corrected for the current OPC run based on the determined pattern density and the mapping relationship in the OPC mode comprises: inputting the area value, the distance, the area of the predetermined region and the aggregate area of all the surrounding patterns except for the pattern to be corrected contained in the predetermined region into the OPC model and taking a difference between an output of the OPC model and the designed CD for the pattern to be corrected as the CD correction amount for the pattern to be corrected for the current OPC run (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
As per claim 19, Parikh discloses all of the features of claim 17 as discloses above wherein Parikh also discloses wherein the distance between the surrounding pattern and the pattern to be corrected is not greater than 100 times the CD of the pattern to be corrected (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047] –[Figure 4, i.e. pattern 412 and 414]).
As per claim 20, Parikh discloses:
An optical proximity correction (OPC) method, comprising: creating an OPC model using a modeling method of claim 1 (See claim 1), which adds a mapping relationship between a critical dimension (CD) of a pattern and pattern density-related variables (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature); determining a test layout corresponding to a prefabricated layout, which has at least one pattern to be corrected, and determining pattern density of the pattern to be corrected in the test layout using a predefined pattern detection strategy (See Para [0037], i.e. a layout mask is designed containing a plurality of different symmetric and asymmetric structures. One or more wafers are then processed according to the symmetric and asymmetric layout, See Para [0039], i.e. test mask layout comprises a plurality of differing symmetric and asymmetric features…a degree of asymmetry is varied over a substantially wide range and at a level of granularity dictated by a user, See Figure 4 & Para [0043]-[0047]); and based on the determined pattern density and the mapping relationship in the OPC model, determining a CD correction amount for the pattern to be corrected for the current OPC run and performing an OPC operation on the pattern to be corrected according to the CD correction amount, wherein the OPC method is implemented by an OPC system, the OPC) system comprising: a modeling module for creating an OPC model using the modeling method, which adds a mapping relationship between a critical dimension (CD) of a pattern and pattern density-related variables; a pattern density determination module for determining a test layout corresponding to a prefabricated layout, which has at least one pattern to be corrected, and determining pattern density of the pattern to be corrected in the test layout using a predefined pattern detection strategy (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature); and a correction module for determining, based on the determined pattern density and the mapping relationship in the OPC model, a CD correction amount for the pattern to be corrected for the current OPC run and performing an OPC operation on the pattern to be corrected according to the CD correction amount (See Para [0036], i.e. employs a density based response of asymmetrical features and structures to generate an OPC model to correct (compensate) the feature size CD to better replicate the design layout. Thus, the CDs or sizes of the features are optimized, See Para [0037], i.e. Critical dimensions of the resultant wafer features are then measured at one or both stages…difference or deviation between the desired CD and the measured CD of the wafer features is then calculated, plotted, mapped, or otherwise determined for the generation of OPC data or for the correction of the OPC data already employed…OPC model, See Para [0040], i.e. critical dimension measurements are made of the resultant symmetric and asymmetric structures formed in the resist, See Para [0041], i.e. the difference or deviation between the desired CD and the measured CD of the layout features is, for example, evaluated, plotted, or mapped for creation of an OPC model that operates to minimize the differences between the desired feature and the resultant feature).
Allowable Subject Matter
7. Claims 8 and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claims 8 and/or 18.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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