DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 3 and 17 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6 and 11-14 are rejected under 35 U.S.C. (a)(1) and/or (a)(2) as being anticipated by Doppalapudi 20210006238 .
Claim 1. Doppalapudi teaches an apparatus [Fig. 1-9], comprising :
a data path, a clock path, a digital control coupled to the data path and the clock path [Fig. 1, data signal DIN, CLK, digital logic circuit 112, par. 24-28]; and
a driver [Fig. 1 and 4, 108-119] coupled to the data path, the clock path, and the digital control wherein the driver comprises a phase detector detect a phase error in data signals from the data path [Fig. 2-3 par. 7, 25-26, 31, error detector 110 measures quadrature error between an in-phase clock and a quadrature clock for data signals], the driver is to transmit the phase error to the digital control and the digital control is to adjust a timing of the data path based on the phase error [Fig. 1-4, output from error detector 110 to digital circuit 112 to correction circuits 114-115, error detection and compensation; par. 8 and 26, error data associated with duty cycle distortion a s Duty Cycle Distortion (DCD)—is the deviation of a signal's active "on" time from its ideal or intended value.].
Claim 2. Doppalapudi teaches the apparatus of claim 1, wherein to adjust the timing of the data path based on the phase error, the digital control is to adjust a timing of a clock multiplexer which distributes clock signals from the clock path to the data path [Fig. 1-7, output from error detector 110 to digital circuit 112 to correction circuits 114-115, par. 26-27, 36, error detection and compensation based on timing data, adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error].
Claim 4. Doppalapudi teaches the apparatus of claim 1, wherein: the driver comprises a duty cycle sensor to determine a target duty cycle and averaged measured duty cycles, to determine a pulse width delta based on the target duty cycle and the averaged measured duty cycles [Fig. 3, 7, par. 6, 4, 28, 30-31, the error detector circuit 110 can measure duty cycle error and can determine an average of first error detector output and second error detector output],, and to transmit the pulse width delta to the digital control; and the digital control is to adjust a timing of a phase generator in the clock path based on the pulse width delta. [Fig. 1, 3 and 5-6, par. 33-34, The duty cycle correction circuit 502 can include a current mode logic (CML) buffer 504 and a digital-to-analog converter (DAC) 505; output from error detector 110 to digital circuit 112 provide error to correction circuits 114-115, par. 26-27, 31-33].
Claim 5. Doppalapudi teaches the apparatus of claim 1, further comprising a quadrature sampler coupled to an output of a quadrature generator in the clock path in the clock path [Fig. 1, MUX 104 connects to D0-D1 and clocks , buffer 118 generates 4 clocks/quadrature clock], wherein the quadrature sampler is to determine phase and duty cycle errors of clock signals output from the quadrature generator and to transmit the phase and duty cycle errors to the digital control, wherein the digital control is to adjust a timing of the quadrature generator based on the phase and duty cycle errors. [par. 6-8, 21, 22, and 335- 36 multiplexing transmitter system with quadrature error detection and/or a duty cycle detection and ; digital logic circuit 112 that is associated with the error detector output; bit pattern represent timing data, using duty cycle correction circuit and quadrature error adjust phase shift error].
Claim 6. Doppalapudi teaches the apparatus of claim 1, further comprising a phase sampler in the clock path, [Fig. 1-2, par. 21-23, , Mux 102 having D1-0 and clocks as inputs ] wherein the phase sampler is to determine phase and duty cycle errors of clock signals in the clock path and to transmit the phase and duty cycle errors to the digital control, and the digital control is to adjust a timing of a phase generator in the clock path based on the phase and duty cycle errors [par. 6-8, 22, multiplexing transmitter system with quadrature error detection and/or a duty cycle detection; determining first error data associated with duty cycle distortion for an in-phase clock provided to the transmitter; adjusting the in-phase clock for the transmitter; adjusting a quadrature clock for the transmitter based on second error data associated with duty cycle distortion for the quadrature clock].
Claim 11. Doppalapudi teaches the apparatus of claim 1, further comprising at least one of a transmitter circuit, an integrated circuit, a System on Chip, a System in Package or a computing device in which the data path, the clock path, the digital control and the driver are provided [par. 2-9, 22, 69-70 electronic circuits, and more particularly to transmitter circuitry
Claim 12, Doppalapudi teaches an apparatus [Fig. 1-9], comprising:
an input node to receive data signals from a data path and clock signals from a clock path [Fig. 1, D0-1 from Din and Clocks to Mux 104] ; a
phase detector to detect a phase error in the data signals and to transmit the phase error to a digital control [par. 7, 25-26, error detector 110 measures quadrature error between an in-phase clock and a quadrature clock for data signals, Fig. 1, output from error detector 110 to digital circuit 112];
a duty cycle sensor to determine a target duty cycle and average measured duty cycles to determine a pulse width delta based on the target duty cycle and the averaged measured duty cycles, [Fig. 3, 7, par. 6, 4, 28, 30-31, the error detector circuit 110 can measure duty cycle error and can determine an average of first error detector output and second error detector output], and to transmit the pulse width delta to the digital control; and an output node to transmit an analog multi-level signal based on the data signals and clock signals [Fig. 1, 3 and 5, par. 33-34, The duty cycle correction circuit 502 can include a current mode logic (CML) buffer 504 and a digital-to-analog converter (DAC) 505; output from error detector 110 to digital circuit 112 to correction circuits 114-115, par. 26-27, 31-33].
Claim 13. Doppalapudi teaches the apparatus of claim 12, wherein the digital control is to adjust a timing of a phase generator in the clock path based on at least one of the pulse width delta or the phase error [par. 26-27, Fig. 5, 7-8, error detection and compensation, see timing diagram, par. 36par. 8 and 26, error data associated with duty cycle distortion a s Duty Cycle Distortion (DCD)—is the deviation of a signal's active "on" time from its ideal or intended value]
Claim 14. Doppalapudi teaches the apparatus of claim 12, wherein the duty cycle sensor is to determine the pulse width delta as a pulse width delta at which a measured duty cycle corresponds to the target duty cycle [ par. 8 and 26, error data associated with duty cycle distortion a s Duty Cycle Distortion (DCD)—is the deviation of a signal's active "on" time from its ideal or intended value. In a perfect clock or PWM signal, a 50% duty cycle means the signal is high exactly half the time. An error occurs when this ratio becomes skewed]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-9, 15, 18-20 re rejected under 35 U.S.C. 103 as being unpatentable over Doppalapudi.
Claim 7. Doppalapudi teaches the apparatus of claim 6, wherein: the phase sampler comprises multiplexer which receive the clocks signals as inputs[par. 21-23, Fig. 1-2, MUX 102 having D1-0 and clocks as inputs ]; and outputs of the multiplexer are coupled to a plurality of sensors which are to determine the phase and duty cycle error of the clock signals [Fig. 3, MUX output coupled to error detection circuit 110 , par. 31]. Doppalapudi does not show plural multiplexers, however, Doppalapudi discusses m multiplexer is an electronic device that selects a signal from a group of signals (e.g., a group of signals received as input) and outputs the selected signal [par. 20] and further discloses 4 serializers [par. 21. DIN signal can include 64 bits and the serializer 108 can be a 64:4 serializer]. Thus it would have been obvious to one having ordinary skill in the art to realized that there are plurality of multiplexers to properly handle the different size data stream as suggested .
Claim 8. Doppalapudi teaches the apparatus of claim 7, wherein the plurality of sensors comprise a sensor to determine the phase error of the clock signals based on at least one of a rising edge-to-rising edge comparison or a falling edge-to-falling edge comparison [Fig. 7, see Fig. 7, par. 31, measurement at edges of waveform- a phase detector is circuit that compares two periodic signals and generates a phase difference; phase error is defined by the time difference (Δ t) between their corresponding edges ]
Claim 9. Doppalapudi teaches the apparatus of claim 7, wherein the plurality of sensors comprise a sensor to determine the phase error of the clock signals based on a positive to negative comparison [par. 31; comparator 310 can determine if a differential average between the average value of the first output data stream DOUTP to the average value of the second output data stream DOUTM is positive or negative.]
Claim 15, Doppalapudi teaches apparatus [Fig. 1-9] comprising: multiplexer to receive clock signals from a clock path in a transmitter [Fig. 1 and 2, par. 20, 30, multiplexer core 104 utilizing multiplexers wherein the clock signals are to be generated by a phase generator;
a set of phase sensors coupled to outputs of the set of multiplexers, wherein the phase sensors are to determine phase errors of the clock signals; and an output multiplexer coupled to outputs of the phase sensors, wherein the output multiplexer is to provide the phase errors to a digital control, and the digital control is to adjust a timing of the phase generator based on the phase errors. [Fig. 7, see Fig. 7, par. 31, measurement at edges of waveform- a phase detector is circuit that compares two periodic signals and generates a phase difference; phase error is defined by the time difference (Δ t) between their corresponding edges ]. As for the recitation of plurality of multiplexers, same analysis is applied as discussed in claim 7 above.
Claim 18. Doppalapudi teaches the apparatus of claim 15, the rest of the claim repeat the limitation of claims 8 and 9 and therefore rejected accordingly.
Claim 19. Doppalapudi teaches the apparatus of claim 18, the rest of the claim repeats the limitation of claim 9 and rejected accordingly.
Claim 20. Doppalapudi teaches the apparatus of claim 15, wherein the clock signals comprise positive phase clock signals and negative phase clock signals, and the apparatus further comprises a set of duty cycle sensors for both the positive phase clock signals and negative phase clock signals.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Doppalapudi in view of NPL, titled “Implementing Multiplexers with Pass-Transistor Logic”.
Claim 10. Doppalapudi as discussed in claim 7, include multiple multiplexers, and as shown, and disclose clock signal connecting to the multiplexer but does not specifically teaches the multiplexer comprised different segments each having a a bootstrapped n-type metal oxide silicon field effect connecting to the MOSFET as claimed. However, NPL teaches efficient multiplexers that can be created by using MOSFETs in a pass-transistor configuration [sub title] and further teaches [Page 3, last two paragraphs] a 4-1 multiplexer having a set of segments using either PMOS or NMOS and indicated that of an NMOS transistors are more superior. Note the term bootstrapping means to pull up the power to the operating point of a transistor. It would have been obvious to one having ordinary skill in the before the effective filing date to implement the multiplexers using nMOSFET for efficiency and better performance as taught by NPL
Claim 16 repeats essentially the same the limitation of claim 10 and therefore rejected accordingly.
Conclusion
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/KIM HUYNH/Primary Patent Examiner, Art Unit 2176
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