DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 5 and 18 are objected to because of the following informalities:
In claim 5 line 2, “a drain region” ---, should be corrected to ---, “the drain region” ---.
In claim 5 line 4, “a drain region” ---, should be corrected to ---, “the drain region” ---.
In claim 18 line 4, “a third body” ---, should be corrected to ---, “the third body” ---.
In claim 18 line 7, “an interconnect” ---, should be corrected to ---, “the interconnect” ---.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-10, 12-15, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gossner (US Publication No. 20080002320) in view of Ker et al (US Publication No. 20080151446).
Regarding claim 1, Gossner discloses an electrostatic discharge (ESD) circuit (i.e., such as the ESD device in fig. 3 as shown below, para. [0044]- [0046]) comprising: a first grounded gate NMOS (GGNMOS) transistor (A) including: a body region (a1/16, a2/17) in a substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a source region (SA) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a first body contact region (a1) electrically connected (i.e., such as electrically connected via terminal a1/16; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (a1/16, a2/17) of the first GGNMOS transistor (A) and electrically coupled (i.e., Y is electrically coupled to Z via W) to the source region (SA) of the first GGNMOS transistor (A); a second body contact region (a2) electrically connected (i.e., such as electrically connected via terminal a2/17; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (a1/16, a2/17) of the first GGNMOS transistor (A) and non-substrate isolated (i.e., such as a2/17 is separated from a1/16; for instance, the n-doped wells 24 insulate the p-doped well 23 together with the n-doped layer 22 from the environment, in particular from substrate 21. A construction like that illustrated in FIG. 2 with the n- and p-doped wells 23 and 24 and the n-doped layer 22 is also designated as a "triple well" construction; see for example fig. 2, para. [0028]- [0036]) from first body contact region (a1) of the first GGNMOS transistor (A); a second GGNMOS transistor (B) including: a body region (b1/16, b2/17) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a source region (SB) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a first body contact region (b1) electrically connected (i.e., such as electrically connected via terminal b1/16; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (b1/16, b2/17) of the second GGNMOS transistor (B) and electrically coupled (i.e., Y is electrically coupled to Z via W) to the source region (SB) of the second GGNMOS transistor (B); a second body contact region (b2) electrically connected (i.e., such as electrically connected via terminal b2/17; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (b1/16, b2/17) of the second GGNMOS transistor (B) and non-substrate isolated (i.e., such as b2/17 is separated from b1/16; for instance, the n-doped wells 24 insulate the p-doped well 23 together with the n-doped layer 22 from the environment, in particular from substrate 21. A construction like that illustrated in FIG. 2 with the n- and p-doped wells 23 and 24 and the n-doped layer 22 is also designated as a "triple well" construction; see for example fig. 2, para. [0028]- [0036]) from first body contact region (b1) of the second GGNMOS transistor (B); wherein the second body contact region (a2) of the first GGNMOS transistor (A) is electrically connected (i.e., a2 is electrically connected to b2 via X) to the second body contact region (b2) of the second GGNMOS transistor (B).
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Gossner does not explicitly disclose that the transistors are a GGNMOS version.
Ker discloses an ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, and the second GGNMOS transistor is M2; see for example fig. 7, para. [0050]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the GGNMOS device in Gossner, as taught by Ker, as it provides the advantage of optimizing the circuit design towards faster switching-speed.
Regarding claim 2, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein the source region (SA) of the first GGNMOS transistor (A) is electrically coupled (i.e., SA is electrically coupled to SB via Z) to the source region (SB) of the second GGNMOS transistor (B).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, and the second GGNMOS transistor is M2; see for example fig. 7, para. [0050]).
Regarding claim 3, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein: the source region (SA) of the first GGNMOS transistor (A) is located in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) laterally (i.e., such as laterally; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) on at least two opposing sides (i.e., such as the two opposing sides of n+/24 insulated by p+/23 to fabricate 17; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) of the second body contact region (a2) of the first GGNMOS transistor (A); the source region (SB) of the second GGNMOS transistor (B) is located in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) laterally (i.e., such as laterally; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) on at least two opposing sides (i.e., such as the two opposing sides of n+/24 insulated by p+/23 to fabricate 17; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) of the second body contact region (b2) of the second GGNMOS transistor (B).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, and the second GGNMOS transistor is M2; see for example fig. 7, para. [0050]).
Regarding claim 4, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein: the first GGNMOS transistor (A) includes a drain region (DA); the second GGNMOS transistor (B) includes a drain region (DB); the drain region (DA) of the first GGNMOS transistor (A) is located in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) laterally (i.e., such as laterally; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) on at least two opposing sides (i.e., such as the two opposing sides of n+/24 insulated by p+/23 to fabricate 17; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) of the second body contact region (a2) of the first GGNMOS transistor (A); the drain region (DB) of the second GGNMOS transistor (B) is located in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) laterally (i.e., such as laterally; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) on at least two opposing sides (i.e., such as the two opposing sides of n+/24 insulated by p+/23 to fabricate 17; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) of the second body contact region (b2) of the second GGNMOS transistor (B).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, and the second GGNMOS transistor is M2; see for example fig. 7, para. [0050]).
Regarding claim 5, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein: the first GGNMOS transistor (A) includes a drain region (DA) electrically coupled (i.e., terminal DA is electrically coupled to L via K) to a first line (L); the second GGNMOS transistor (B) includes a drain region (DB) electrically coupled (i.e., terminal DB is electrically coupled to L via K) to the first line (L); the source region (SA) of the first GGNMOS transistor (A) is electrically coupled (i.e., W is electrically coupled to M via N) to a second line (M); the source region (SB) of the second GGNMOS transistor (B) is electrically coupled (i.e., W is electrically coupled to M via N) to the second line (M).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, and the second GGNMOS transistor is M2; see for example fig. 7, para. [0050]).
Regarding claim 6, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein during an ESD event (i.e., such as an ESD event; see for example fig. 3 as shown above, para. [0044]- [0046]) affecting the first line (L), the first GGNMOS transistor (A) and the second GGNMOS transistor (B) are conductive (ON) to discharge ESD current (i.e., such as to discharge ESD current; see for example fig. 3 as shown above, para. [0044]- [0046]) to the second line (M).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, and the second GGNMOS transistor is M2; see for example fig. 7, para. [0050]).
Regarding claim 8, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); further comprising: a third GGNMOS transistor (C) including: a body region (c1/16, c2/17) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a source region (SC) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a first body contact region (c1) electrically connected (i.e., such as electrically connected via terminal c1/16; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (c1/16, c2/17) of the third GGNMOS transistor (C) and electrically coupled (i.e., Y is electrically coupled to Z via W) to the source region (SC) of the third GGNMOS transistor (C); a second body contact region (c2) electrically connected (i.e., such as electrically connected via terminal c2/17; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (c1/16, c2/17) of the third GGNMOS transistor (C) and non-substrate isolated (i.e., such as c2/17 is separated from c1/16; for instance, the n-doped wells 24 insulate the p-doped well 23 together with the n-doped layer 22 from the environment, in particular from substrate 21. A construction like that illustrated in FIG. 2 with the n- and p-doped wells 23 and 24 and the n-doped layer 22 is also designated as a "triple well" construction; see for example fig. 2, para. [0028]- [0036]) from first body contact region (c1) of the third GGNMOS transistor (C); wherein the second body contact region (c2) of the third GGNMOS transistor (C) is electrically connected (i.e., c2 is electrically connected to a2 via X) to the second body contact region (a2) of the first GGNMOS transistor (A).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Regarding claim 9, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); further comprising: a gate material structure (GA) located directly over a first area (i.e., such as area 13/10; see for example fig. 2, para. [0028]- [0036]) of the body region (a1/16, a2/17) of the first GGNMOS transistor (A), the first area (i.e., such as area 13/10; see for example fig. 2, para. [0028]- [0036]) located directly laterally (i.e., such as laterally; see for example the device fabrication layout in fig. 2, para. [0028]- [0036]) between the first body contact region (a1) of the first GGNMOS transistor (A) and the second body contact region (a2) of the first GGNMOS transistor (A).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Regarding claim 10, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein the first GGNMOS transistor (A) is substrate isolated (i.e., such as substrate isolated; for instance, an insulating layer, for example an n-doped layer and n-doped wells arranged round the above-mentioned p-doped well, are biased in order to insulate the p-doped well from the substrate of the transistor; see for example fig. 2, para. [0029]) from the second GGNMOS transistor (B).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Regarding claim 12, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); a semiconductor die (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]) comprising: a first line (L); a second line (M); a clamp device (P) for electrically connecting (i.e., P is electrically connected to L via K and electrically connected to via N) the first line (L) to the second line (M) to discharge ESD current (i.e., such as to discharge ESD current; see for example fig. 3 as shown above, para. [0044]- [0046]) from the first line (L) to the second line (M) during an ESD event (i.e., such as an ESD event; see for example fig. 3 as shown above, para. [0044]- [0046]) affecting the first line (L), the clamp device (P) including: a first grounded gate NMOS (GGNMOS) transistor (A) including: a body region (a1/16, a2/17) in a substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a drain region (DA) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) electrically coupled (i.e., terminal DA is electrically coupled to L via K) to the first line (L); a source region (SA) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) electrically coupled (i.e., W is electrically coupled to M via N) to the second line (M); a first body contact region (a1) electrically connected (i.e., such as electrically connected via terminal a1/16; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (a1/16, a2/17) of the first GGNMOS transistor (A) and electrically coupled (i.e., Y is electrically coupled to Z via W) to the source region (SA) of the first GGNMOS transistor (A); a second body contact region (a2) electrically connected (i.e., such as electrically connected via terminal a2/17; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (a1/16, a2/17) of the first GGNMOS transistor (A) and non-substrate isolated (i.e., such as a2/17 is separated from a1/16; for instance, the n-doped wells 24 insulate the p-doped well 23 together with the n-doped layer 22 from the environment, in particular from substrate 21. A construction like that illustrated in FIG. 2 with the n- and p-doped wells 23 and 24 and the n-doped layer 22 is also designated as a "triple well" construction; see for example fig. 2, para. [0028]- [0036]) from first body contact region (a1) of the first GGNMOS transistor (A); a second GGNMOS transistor (B) including: a drain region (DB) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) electrically coupled (i.e., terminal DB is electrically coupled to L via K) to the first line (L); a body region (b1/16, b2/17) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a source region (SB) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) electrically coupled (i.e., W is electrically coupled to M via N) to the second line (M); a first body contact region (b1) electrically connected (i.e., such as electrically connected via terminal b1/16; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (b1/16, b2/17) of the second GGNMOS transistor (B) and electrically coupled (i.e., Y is electrically coupled to Z via W) to the source region (SB) of the second GGNMOS transistor (B); a second body contact region (b2) electrically connected (i.e., such as electrically connected via terminal b2/17; see for example the device fabrication in fig. 2, para. [0028]- [0036]) to the body region (b1/16, b2/17) of the second GGNMOS transistor (B) and non-substrate isolated (i.e., such as b2/17 is separated from b1/16; for instance, the n-doped wells 24 insulate the p-doped well 23 together with the n-doped layer 22 from the environment, in particular from substrate 21. A construction like that illustrated in FIG. 2 with the n- and p-doped wells 23 and 24 and the n-doped layer 22 is also designated as a "triple well" construction; see for example fig. 2, para. [0028]- [0036]) from first body contact region (b1) of the second GGNMOS transistor (B); wherein the second body contact region (a2) of the first GGNMOS transistor (A) is electrically connected (i.e., a2 is electrically connected to b2 via X) to the second body contact region (b2) of the second GGNMOS transistor (B).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Regarding claim 13, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above. Also, is rejected for the same reasons that have already been stated/discussed above in rejected claim 10. {See rejection of claim 10}
Regarding claim 14, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above. Also, is rejected for the same reasons that have already been stated/discussed above in rejected claim 3. {See rejection of claim 3}
Regarding claim 15, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above. Also, is rejected for the same reasons that have already been stated/discussed above in rejected claim 4. {See rejection of claim 4}
Regarding claim 17, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); the semiconductor die (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]): further comprising: a third GGNMOS transistor (C) including: a drain region (DC) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) electrically coupled (i.e., terminal DC is electrically coupled to L via K) to the first line (L); a body region (c1/16, c2/17) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]); a source region (SC) in the substrate (i.e., such as substrate 21; for instance, the semiconductor structure illustrated in FIG. 2 is formed on a p-doped substrate 21. The thickness of the substrate 21 and the rest of the elements are not illustrated to scale in FIG. 2; in general, the substrate 21 will be considerably thicker than the layers lying on top of it; see for example fig. 2, para. [0028]- [0036]) electrically coupled (i.e., W is electrically coupled to M via N) to the second line (M). As for the rest of the limitations/features in claim 17 is rejected for the same reasons that have already been stated/discussed above in rejected claim 8. {See rejection of claim 8}
Regarding claim 19, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above. Also, is rejected for the same reasons that have already been stated/discussed above in rejected claim 9. {See rejection of claim 9}
Claims 7, 11, 16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gossner (US Publication No. 20080002320) in view of Ker et al (US Publication No. 20080151446) and further in view of Nakano et al (US Publication No. 20020185681).
Regarding claim 7, Gossner in view of Ker and the teachings of Gossner as modified by Ker have been discussed above.
Gossner further discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein during an ESD event (i.e., such as an ESD event; see for example fig. 3 as shown above, para. [0044]- [0046]) where the first GGNMOS transistor (A) becomes conductive (ON).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Neither Gossner nor Ker explicitly discloses holes from the body region of the first GGNMOS transistor transfer through the second body contact region of the first GGNMOS transistor, through the second body contact region of the second GGNMOS transistor, to the body region of the second GGNMOS transistor.
Nakano discloses (i.e., see for example fig. 7, para. [0061]), a power MOS transistor formed of an array of
source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells; wherein holes
(i.e., plurality of contact holes 16 respectively corresponding to the body contact regions 14 are formed
in the electrically insulating layer 6; see for example fig. 7, para. [0061]) from the body region (i.e., plurality
of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e.,
Tr10/power MOS; see for example fig. 18, para. [0061]) transfer (i.e., in effect, that P.sup. + region has been moved to a separate location. Hence the size of the area occupied by each source cell can be substantially reduced; see for example para. [0070]) through the second body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]), through the second body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the second GGNMOS transistor (i.e., Tr11/power MOS; see for example fig. 18, para. [0061]), to the body region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the second GGNMOS transistor (i.e., Tr11/power MOS; see for example fig. 18, para. [0061]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the
claimed invention to have optionally included the contact holes-MOS structure in Gossner, as taught by
Nakano, as it provides the advantage of optimizing the circuit design towards improving robustness and
performance of the GGNMOS device during ESD events.
Regarding claim 11, Gossner in view of Ker and further in view of Nakano and the teachings of Gossner as modified by Ker have been discussed above. Also, the teachings of Gossner as modified by Nakano have been discussed above as well.
Nakano further discloses (i.e., see for example fig. 7, para. [0061]); wherein the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]) includes a third body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) electrically connected (i.e., such as electrically connected, for instance, the source electrodes are each formed over the upper face of the substrate, in contact with the source regions through respective ones of the contact holes. Such a transistor is characterized in having a plurality of body contact regions extending from the substrate upper face, each having a corresponding substrate potential-setting electrode, to constitute a substrate contact cell, with each of these body contact regions being located outside the areas occupied by the source cells. The potential of the substrate region that is of the first conduction type can thereby be set as required, i.e., as the potential of the substrate potential-setting electrodes; see for example fig. 7, para. [0014]) to the body region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]), electrically connected (i.e., such as electrically connected, for instance, the source electrodes are each formed over the upper face of the substrate, in contact with the source regions through respective ones of the contact holes. Such a transistor is characterized in having a plurality of body contact regions extending from the substrate upper face, each having a corresponding substrate potential-setting electrode, to constitute a substrate contact cell, with each of these body contact regions being located outside the areas occupied by the source cells. The potential of the substrate region that is of the first conduction type can thereby be set as required, i.e., as the potential of the substrate potential-setting electrodes; see for example fig. 7, para. [0014]) to the second body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]) by at least an interconnect (i.e., 18; the second-layer source connecting lead 18; see for example fig. 4, para. [0064]), and non-substrate isolated (i.e., such as an electrically insulating layer formed on that upper face, and a plurality of contact holes respectively corresponding to the source cells formed in the electrically insulating layer. Each of the source cells occupies an area that is defined by the corresponding contact hole and a region around the periphery of that contact hole. The transistor further includes a channel region that is of a second conduction type, formed in the substrate region of the first conduction type, extending downward from the upper face of the substrate, a plurality of source regions which are of the first conduction type, and respectively correspond to the source cells, each formed in the channel region extending from the upper face, and an array of gate electrodes, each formed above the upper face of the substrate. Each gate electrode covers a part of the channel region, separated from that channel region by a gate insulation film; see for example fig. 7, para. [0014]) from first body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Regarding claim 16, Gossner in view of Ker and further in view of Nakano and the teachings of Gossner as modified by Ker have been discussed above. Also, the teachings of Gossner as modified by Nakano have been discussed above as well.
Nakano further discloses (i.e., see for example fig. 7, para. [0061]); wherein holes (i.e., plurality of contact holes 16 respectively corresponding to the body contact regions 14 are formed in the electrically insulating layer 6; see for example fig. 7, para. [0061]) are transferable (i.e., in effect, that P.sup. + region has been
moved to a separate location. Hence the size of the area occupied by each source cell can be substantially
reduced; see for example para. [0070]) between the second body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]) and the second body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the second GGNMOS transistor (i.e., Tr11/power MOS; see for example fig. 18, para. [0061]) during an ESD event (i.e., such as an ESD event; see for example fig. 18, para. [0083]) affecting the first line (i.e., such as the first line terminal connected to R44; see for example fig. 18, para. [0083]).
Ker furthermore discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Regarding claim 18, Gossner in view of Ker and further in view of Nakano and the teachings of Gossner as modified by Ker have been discussed above. Also, the teachings of Gossner as modified by Nakano have been discussed above as well.
Gossner discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein the first GGNMOS transistor (A) is substrate isolated (i.e., such as substrate isolated; for instance, an insulating layer, for example an n-doped layer and n-doped wells arranged round the above-mentioned p-doped well, are biased in order to insulate the p-doped well from the substrate of the transistor; see for example fig. 2, para. [0029]) from the second GGNMOS transistor (B).
Ker further discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Nakano furthermore discloses (i.e., see for example fig. 7, para. [0061]); the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]) includes a third body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) electrically connected (i.e., such as electrically connected, for instance, the source electrodes are each formed over the upper face of the substrate, in contact with the source regions through respective ones of the contact holes. Such a transistor is characterized in having a plurality of body contact regions extending from the substrate upper face, each having a corresponding substrate potential-setting electrode, to constitute a substrate contact cell, with each of these body contact regions being located outside the areas occupied by the source cells. The potential of the substrate region that is of the first conduction type can thereby be set as required, i.e., as the potential of the substrate potential-setting electrodes; see for example fig. 7, para. [0014]) to the body region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]), electrically connected (i.e., such as electrically connected, for instance, the source electrodes are each formed over the upper face of the substrate, in contact with the source regions through respective ones of the contact holes. Such a transistor is characterized in having a plurality of body contact regions extending from the substrate upper face, each having a corresponding substrate potential-setting electrode, to constitute a substrate contact cell, with each of these body contact regions being located outside the areas occupied by the source cells. The potential of the substrate region that is of the first conduction type can thereby be set as required, i.e., as the potential of the substrate potential-setting electrodes; see for example fig. 7, para. [0014]) to the second body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]) by at least an interconnect (i.e., 18; the second-layer source connecting lead 18; see for example fig. 4, para. [0064]), and non-substrate isolated (i.e., such as an electrically insulating layer formed on that upper face, and a plurality of contact holes respectively corresponding to the source cells formed in the electrically insulating layer. Each of the source cells occupies an area that is defined by the corresponding contact hole and a region around the periphery of that contact hole. The transistor further includes a channel region that is of a second conduction type, formed in the substrate region of the first conduction type, extending downward from the upper face of the substrate, a plurality of source regions which are of the first conduction type, and respectively correspond to the source cells, each formed in the channel region extending from the upper face, and an array of gate electrodes, each formed above the upper face of the substrate. Each gate electrode covers a part of the channel region, separated from that channel region by a gate insulation film; see for example fig. 7, para. [0014]) from first body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) from first body contact region (i.e., plurality of body contact regions 14; see for example fig. 7, para. [0061]) of the first GGNMOS transistor (i.e., Tr10/power MOS; see for example fig. 18, para. [0061]).
Regarding claim 20, Gossner in view of Ker and further in view of Nakano and the teachings of Gossner as modified by Ker have been discussed above. Also, the teachings of Gossner as modified by Nakano have been discussed above as well.
Gossner discloses the circuit (i.e., such as the ESD device in fig. 3 as shown above, para. [0044]- [0046]); wherein the first GGNMOS transistor (A) is substrate isolated (i.e., such as substrate isolated; for instance, an insulating layer, for example an n-doped layer and n-doped wells arranged round the above-mentioned p-doped well, are biased in order to insulate the p-doped well from the substrate of the transistor; see for example fig. 2, para. [0029]) from the second GGNMOS transistor (B).
Ker further discloses the ESD protection device (i.e., see for example fig. 7, para. [0048]- [0051]); wherein the transistors are a GGNMOS version (i.e., such as the first GGNMOS transistor is M1, the second GGNMOS transistor is M2, and the third GGNMOS transistor is M3; see for example fig. 7, para. [0050]).
Nakano furthermore discloses (i.e., see for example fig. 7, para. [0061]); at least an interconnect (i.e., 18; the second-layer source connecting lead 18; see for example fig. 4, para. [0064]). As for the rest of the limitations/features in claim 20 is rejected for the same reasons that have already been stated/discussed above in rejected claim 12. {See rejection of claim 12}
Conclusion
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838