DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed 06/05/2023 have all been considered and made of record.
Joint Inventors
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Objections
Claim 17 is objected to because of the following informalities:
Line 1 of claim 17 should read “…further comprising a processing unit…”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6, 9, 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Taha (US 20230084003 A1).
With regards to claim 1, Taha discloses an apparatus, comprising:
a semiconductor substrate including a photonic integrated circuit (PIC), the PIC including waveguides (Taha/Fig1/Semiconductor substrate 122 and PIC 104), and the semiconductor substrate defining a cavity having sidewalls (Figs33a&33b/Cavity 3384b [Rightmost instance]);
a connector (Connector [Region indicated below]);
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a glass waveguide substrate optically coupled to the waveguides of the PIC via the connector (Fig1/Glass waveguide substrate 108); and
wherein the connector is characterized by a feature including glass and extending from the glass waveguide substrate into the cavity (Figs33a&33b/Feature 3382b; Paragraph 227; Lines 16-18; Paragraph 99/Lines 7-18), the feature having at least two regions that contact the sidewalls (Figs33a&33b/Regions as indicated below; Paragraph 227/Lines 21-24).
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With regards to claim 2, Taha discloses the apparatus of claim 1, further comprising an adhesive layer located between the semiconductor substrate and the glass waveguide substrate (Paragraph 159/Lines 3-6).
With regards to claim 6, Taha discloses the apparatus of claim 1, wherein a portion of the glass waveguide substrate overlaps on the semiconductor substrate, and a corresponding region of the semiconductor substrate is thinned with respect to another region of the semiconductor substrate to receive the portion of the glass waveguide substrate (Fig33b/Corresponding region [as indicated below]).
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With regards to claim 9, Taha discloses the apparatus of claim 1, wherein the waveguides in the PIC comprise silicon nitride (Fig18a; Paragraph 187/Lines 2-5).
With regards to claim 10, Taha discloses the apparatus of claim 1, wherein individual ones of the waveguides in the PIC are vertically optically coupled to the glass waveguide substrate (Fig1).
With regards to claim 11, Taha discloses the apparatus of claim 1, wherein the semiconductor substrate further includes an edge cavity located alongside the waveguides in the PIC (Fig33bEdge cavity as indicated below).
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With regards to claim 12, Taha discloses the apparatus of claim 1, wherein the waveguides in the PIC are horizontally optically coupled to the glass waveguide substrate along a facet (Fig1/Facet [vertical side of element 128]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 14 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Taha (US 20230084003 A1).
With regards to claim 14, Taha discloses a semiconductor assembly, comprising:
a package substrate (Taha/Figs33a&33b/Package substrate 3378);
an electronic integrated circuit (EIC) die attached on the package substrate (Figs33a&33b/EIC 3370);
a photonic integrated circuit (PIC) die comprising silicon waveguides in a silicon substrate, the PIC die defining two or more cavities having respective sidewalls, the PIC die attached on the package substrate and in communication with the EIC die (Figs33a&33b/Silicon substrate 122, PIC 104, and cavities 3384b); and
a glass waveguide substrate optically coupled at a first surface to the silicon waveguides via at least two features, wherein individual ones of the features extend from the first surface into a cavity and contact therein to respective sidewalls in at least two regions (Taha/Figs33a&33b/Features 3382 and regions on either side of both instances of 3384b).
Taha only presents a horizontal cross-section of a relevant device and is silent regarding a third feature. However, the addition of a third feature constitutes the duplication of an essential working part, and it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optically coupled at a first surface to the silicon waveguides via at least three features since doing so would further secure one substrate with respect to the other.
With regards to claim 17, Taha discloses the semiconductor assembly of claim 14, further a processing unit attached on the package substrate and electrically coupled to the EIC die and PIC die (Paragraph 194/Lines 11-13).
With regards to claim 18, Taha discloses the semiconductor assembly of claim 17, further comprising a heat spreader component located over the processing unit and the EIC die (Heat spreader 106; Paragraph 156/Lines 11-12).
Claims 3-5, 7-8, 15-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Taha (US 20230084003 A1) in view of Dautartas (US 20020084565 A1).
With regards to claim 3, Taha discloses the apparatus of claim 1, but is silent regarding the feature is substantially hemispherical. However, the practice of interfacing a substantially hemispherical feature with a cavity exists in the art as exemplified by Dautartas.
Taha and Dautartas are considered to be analogous in the field of IC packaging. Taha and Dautartas both disclose stacked substrates coupled via a positive feature and respective cavity. Dautartas further teaches the feature as substantially hemispherical (Dautartas/Fig3/Substantially hemispherical feature [Portion of element 40b within element 20]; Paragraph 15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the interfacing portion of the feature of Taha such that it was substantially hemispherical as suggested by Dautartas since doing so would facilitate mechanical alignment of the semiconductor substrate and waveguide substrate by configuring the shape of the feature to actively center one substrate with respect to the other when brought into contact with a negative space.
With regards to claim 4, Taha discloses the apparatus of claim 1, but is silent regarding the diameter of the features. However, the practice of configuring positive interfacing features to have a diameter in a range of about 40 microns to about 100 microns within an optical package exists in the art as exemplified by Dautartas.
Taha and Dautartas are considered to be analogous in the field of optical packaging. Taha and Dautartas both disclose stacked substrates coupled via a positive feature and respective cavity. Dautartas further teaches positive interfacing features to have a diameter in a range of about 40 microns to about 100 microns (Dautartas/Paragraph 55/Lines 2-3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a diameter in the range of about 40-100 microns for the features of Taha since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With regards to claim 5, Taha discloses the apparatus of claim 1, but is silent regarding the sidewalls including at least one portion defined by a slope of substantially 54.7 degrees. However, the practice of configuring feature-receiving cavities to have a slope of 54.7 degrees exists in the art as exemplified by Dautartas.
Taha and Dautartas are considered to be analogous in the field of optical packaging. Taha and Dautartas both disclose stacked substrates coupled via a positive feature and respective cavity. Dautartas further teaches cavity sidewalls as having a slope of 54.7 degrees (Dautartas/Paragraph 66/Lines 13-15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an angle of 54.7 degrees for the slope of the cavities because doing so would facilitate formation of the cavities via etching.
With regards to claims 7 and 8, Taha discloses the apparatus of claim 1, but is silent regarding the cavity having an inverted pyramidal shape or being a v-groove. However, the practice of interfacing a positive feature with a pyramidal cavity and/or a v-groove exists in the art as exemplified by Dautartas.
Taha and Dautartas are considered to be analogous in the field of optical packaging. Taha and Dautartas both disclose stacked substrates coupled via a positive feature and respective cavity. Dautartas further teaches a cavity having an inverted pyramidal shape and/or a v-groove (Dautartas/Figs6f-6g; Paragraph 18). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an inverted pyramid or v-groove as the shape of the cavity of Taha since doing so would facilitate mechanical alignment of the semiconductor substrate and waveguide substrate by configuring the shape of the cavity to actively center one substrate with respect to the other when the substrates are brought together. Furthermore, examiner notes that Dautartas teaches inverted pyramidal cavities and v-grooves as equivalent structures known in the art within the context of substrate interfacing. Therefore, because these two cavities were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute one for the other.
With regards to claims 15 and 16, Taha discloses the semiconductor assembly of claim 14, but is silent regarding the cavity having an inverted pyramidal shape or being a v-groove. However, the practice of interfacing a positive feature with a pyramidal cavity and/or a v-groove exists in the art as exemplified by Dautartas.
Taha and Dautartas are considered to be analogous in the field of optical packaging. Taha and Dautartas both disclose stacked substrates coupled via a positive feature and respective cavity. Dautartas further teaches a cavity having an inverted pyramidal shape and/or a v-groove (Dautartas/Figs6f-6g; Paragraph 18). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an inverted pyramid or v-groove as the shape of the cavity of Taha since doing so would facilitate mechanical alignment of the semiconductor substrate and waveguide substrate by configuring the shape of the cavity to actively center one substrate with respect to the other when the substrates are brought together. Furthermore, examiner notes that Dautartas teaches inverted pyramidal cavities and v-grooves as equivalent structures known in the art within the context of substrate interfacing. Therefore, because these two cavities were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute one for the other.
With regards to claim 19, Taha discloses a method, comprising:
providing a crystalline substrate having a photonic integrated circuit (PIC) with waveguides therein (Taha/Fig1/Crystalline substrate 122 and PIC 104);
creating one or more cavities at predetermined locations in the crystalline substrate, wherein the cavities have sidewalls, (Figs33a&33b/One or more cavities 3384b and sidewalls [left and right sides of cavity]);
providing a glass waveguide substrate (Figures 1, 33a, and 33b/Glass waveguide substrate 108);
creating on the glass waveguide substrate, for individual ones of the cavities, a respective feature that extends from the glass waveguide substrate into the cavity and has at least two regions thereon that contacts respective sidewalls (Figs33a&33b/Features 3382b and regions [as indicated below]); and
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attaching the glass waveguide substrate to the crystalline substrate such that individual ones of the cavities have therein a respective feature and the waveguides are optically aligned with the glass waveguide substrate (Figs33a&33b).
Taha is silent regarding the waveguides being silicon in the embodiment relied upon, but does disclose silicon as a waveguide material (Paragraph 238/Lines 1-4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select silicon as the waveguide material since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice (In re Leshin, 125 USPQ 416). Taha is silent regarding whether or not etching is used to form the cavities, but does disclose etching as a method of forming cavities in a different embodiment (Paragraph 140; Lines 19-23; Paragraph 249/Lines 7-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an etching process to form the cavities since doing so would allow for precise feature formation and would facilitate high-volume production. Taha is silent regarding angles of individual ones of the sidewalls correspond to 111 facets of the crystalline substrate. However, the practice of configuring sidewalls of a cavity to correspond to 111 facets of a crystalline substrate exists in the art as exemplified by Dautartas.
Taha and Dautartas are considered to be analogous in the field of optical packaging. Taha and Dautartas both disclose stacked substrates coupled via a positive feature and respective cavity. Dautartas further teaches cavity sidewalls as having a slope of 54.7 degrees (Dautartas/Paragraph 66/Lines 13-15) which is commonly understood to coincide with the <111> plane of a 111 silicon wafer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configuring sidewalls of the cavity of Taha to correspond to 111 facets of a crystalline substrate because doing so would facilitate formation of the cavities in a standard silicon wafer.
With regards to claim 20, Taha discloses the method of claim 19, further comprising providing an adhesive layer between the PIC die and the glass waveguide substrate (Paragraph 159/Lines 3-6). Taha is silent regarding individual ones of the sidewalls being at an angle of about 54.7 degrees with respect to a horizontal plane. However, the practice of configuring feature-receiving cavities to have a slope of 54.7 degrees exists in the art as exemplified by Dautartas.
Taha and Dautartas are considered to be analogous in the field of optical packaging. Taha and Dautartas both disclose stacked substrates coupled via a positive feature and respective cavity. Dautartas further teaches cavity sidewalls as having a slope of 54.7 degrees (Dautartas/Paragraph 66/Lines 13-15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an angle of 54.7 degrees for the slope of the cavities of Taha because doing so would facilitate formation of the cavities via anisotropic etching.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Taha (US 20230084003 A1) in view of Vora (US 20070194416 A1).
With regards to claim 13, Taha discloses the apparatus of claim 1, wherein the connector is a first connector, the cavity is a first cavity with first cavity sidewalls, and further comprising:
the semiconductor substrate defining a second cavity having second sidewalls (Figs33a&33b/Second cavity 3384b [Leftmost instance]; Second sidewalls [as indicated below]);
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a second feature that extends from the glass waveguide substrate into the second cavity at a first location, the second feature having at least two regions that contact the second sidewalls (Figs33a&33b/Second feature 3382b [Leftmost instance]); and
wherein the glass waveguide substrate is optically coupled to the waveguides in the PIC further via the second feature (Fig33a).
Taha only presents a horizontal cross-section of a relevant device and is silent regarding a third feature that extends from the glass waveguide substrate into the second cavity at a second location, away from the first location, the third feature having at least two regions that contact the second sidewalls. However, the practice of configuring a second cavity to receive multiple features exists in the art as exemplified by Vora.
Taha and Vora are considered to be analogous in the field of IC packaging. Taha and Vora both disclose stacked substrates coupled via positive features and respective cavities (Vora/Figs6a-6b). Vora further teaches a third feature that extends from the glass waveguide substrate into a second cavity at a second location, away from the first location, the third feature having at least two regions that contact the second sidewalls (Vora/Figs6a-6b/Third instance of features 608, second cavity of cavities 606, regions of contact as shown in fig6b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the apparatus of Taha such that a third feature extended from the glass waveguide substrate into the second cavity at a second location, away from the first location, the third feature having at least two regions that contact the second sidewalls as suggested by Vora since doing so would further secure one substrate to the other and further prevent rotation.
Conclusion
This prior art, made of record, but not relied upon, is considered pertinent to applicant’s disclosure since the following references have similar structure and/or use similar structure and/or similar optical elements to what is disclosed and/or claimed in the instant application:
University Wafer (https://web.archive.org/web/20230316094356/https://www.universitywafer.com/silicon-wafer-orientation.html [03/16/2023]) [Si 111 and 54.7 degrees]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marc E Manheim whose telephone number is (703)756-1873. The examiner can normally be reached 6:30am - 5pm E.T., Monday - Tuesday and Thursday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARC E MANHEIM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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