DETAILED ACTION
Claims 1-20 are pending. Claims 1-20 are considered in this Office action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 11 of the current application (Hereby known as ‘527) are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims, 1 and 11, respectively, of copending Application No. 18/325,553 (Hereby known as ‘553). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding Claims 1 and 11, Claims 1 and 11 of the current application (‘527) recite substantially similar steps of '553 - Claims 1 and 11 respectively.
Claims 1 and 11 of ‘527 recite the steps of:
identifying resource constraints for the multiple computing devices; using identified resource constraints, creating a presentation model having a plurality of modifiable parameters based at least in part based on the resource constraints; and using at least one inference engine supporting neural network processing, with the inference engine executing a particular neural network model based at least in part on the presentation model.
Whereas Claims 1 and 11 of ‘553 states:
identifying resource constraints for the multiple computing devices; using identified resource constraints, creating multiple presentation models at least in part based on identified processing metrics, with the multiple presentation models including multiple processing pipelines configurable for execution on multiple computing devices; and using an inference engine to provide an execution model for the multiple processing pipelines based at least in part on the multiple presentation models, with the execution model having improved processing metrics as compared to at least one of the multiple presentation models.
It would have been obvious to have modified the method and system taught of the ’553 application as it is a mere substitution of an execution model with a particular neural network model as they are both defined similarly in the Specifications, which are also similar in the Applications
Thus, Claims 1 and 11 of the current application are obvious variants of claims 1 and 11 in ‘553.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Alice - Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claims 1 and 11 recite limitations for identifying resource constraints for the multiple computing devices using identified resource constraints (Analyzing the Information, an Evaluation, a Mental Process; a Fundamental Economic Process, i.e. managing business metrics; a Certain Method of Organizing Human Activity), creating a presentation model having a plurality of modifiable parameters based at least in part based on the resource constraints (Analyzing the Information, an Evaluation, a Mental Process; a Fundamental Economic Process, i.e. managing business metrics; a Certain Method of Organizing Human Activity), and executing a particular neural network model based at least in part on the presentation model (Transmitting the Analyzed Information, a Judgment, a Mental Process; a Fundamental Economic Process, i.e. managing business metrics; a Certain Method of Organizing Human Activity), which under their broadest reasonable interpretation, covers performance of the limitation in the mind for the purposes of a Fundamental Economic Process, i.e. managing business metrics, but for the recitation of generic computer components. That is, other than reciting use of multiple computing devices, an inference engine supporting neural network processing, apparatus, pipeline processing architecture generator, and using at least one inference engine supporting neural network processing, with the inference engine executing a particular neural network model based at least in part on the presentation model, nothing in the claim element precludes the step from practically being performed or read into the mind for the purposes of a Fundamental Economic Process. For example, identifying resource constraints and using the identified resource constraints to create a presentation model having a plurality of modifiable parameters based on them encompasses a data analyst or manager who thinks about and decides on resource constraints, and then creates a model to better help make decisions where they can change the parameters, such as y=Fx, where F can be changed, which is an observation, evaluation, and judgment. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas, an observation, evaluation, and judgment. Further, as described above, the claims recite limitations for a Fundamental, a “Certain Method of Organizing Human Activity”. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim recites the above stated additional elements to perform the abstract limitations as above. The computing devices, inference engine supporting neural network processing, apparatus, and pipeline processing architecture generator are recited at a high-level of generality (i.e., as a generic software/module performing a generic computer function of storing, retrieving, sending, and processing data) such that they amount to no more than mere instructions to apply the exception using generic computer components. Even if taken as an additional element, the receiving and transmitting steps above are insignificant extra-solution activity as these are receiving, storing, and transmitting data as per the MPEP 2106.05(d). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception, when considered both individually and as an ordered combination. As discussed above with respect to integration of the abstract idea into a practical application, the additional element being used to perform the abstract limitations stated above amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. The claim is not patent eligible. Applicant’s Specification states:
“[00273] FIG. 23 is a block diagram depicting an embodiment of a processing system 2302. Processing system 2302 may be used in embodiments of pipeline processing architecture generator 118. As depicted, processing system 2302 incudes communication manager 2304,memory 2306,system resource allocator, statistics collection module 2310,memory allocation module 2312, pipeline merging module 2314,processor 2316,user interface 2318,source rate control module 2320,memory management module 2322,memory co-location module 2324, and data bus 2326.”
Which shows that any generic computer with software can be used to perform the abstract limitations, such as a laptop, phone, desktop, etc., and from this interpretation, one would reasonably deduce the aforementioned steps are all functions that can be done on generic components, and thus application of an abstract idea on a generic computer, as per the Alice decision and not requiring further analysis under Berkheimer, but for edification the Applicant’s specification has been used as above satisfying any such requirement. This is “Applying It” by utilizing current technologies. For the receiving and transmitting steps that were considered extra-solution activity in Step 2A above, if they were to be considered additional elements, they have been re-evaluated in Step 2B and determined to be well-understood, routine, conventional, activity in the field. The background does not provide any indication that the additional elements, such as the apparatus, computing devices, etc., nor the transmitting steps as above, are anything other than a generic, and the MPEP Section 2106.05(d) indicates that mere collection or receipt, storing, or transmission of data is a well‐understood, routine, and conventional function when it is claimed in a merely generic manner (as it is here). For these reasons, there is no inventive concept. The claim is not patent eligible.
Claims 2-10 and 11-20 contain the identified abstract ideas, further narrowing them, with the additional elements of a network, multi-core CPUs, multi-core GPUs, system memory, multi-core custom hardware accelerators, NPUs, DLAs, and FPGA-based custom accelerators which are all highly generalized as per Applicant’s Specification when considered as part of a practical application or under prong 2 of the Alice analysis of the MPEP, thus not integrated into a practical application, nor are they significantly more for the same reasons and rationale as above.
After considering all claim elements, both individually and in combination, Examiner has determined that the claims are directed to the above abstract ideas and do not amount to significantly more. Therefore, the claims and dependent claims are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. See Alice Corporation Pty. Ltd. v. CLS Bank International, No. 13–298.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 9-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. Publication No. 2022/038,3117) in view of Vallelunga (U.S. Publication No. 2022/041,4745).
Regarding Claims 1 and 11, Kim, a system and method for Bayesian personalization, teaches a processing method for multiple computing devices ([0028] multiple computing devices used in the shared models of the system), comprising:
identifying resource constraints for the multiple computing devices ([0023] resource constraints are used for each edge device which are multiple computing devices);
using identified resource constraints, creating a presentation model having a plurality of modifiable parameters based at least in part based on the resource constraints ([0072] and [0172] neuro models are created based on constraints from the overall system.
Although Kim teaches neural network processing (as above), and an inference engine being used to create a model as in [0145-155], it does not explicitly state a neural network model based on another model.
Vallelunga, a system and method for back end server modification and model visualization, teaches using at least one inference engine supporting neural network processing, with the inference engine executing a particular neural network model based at least in part on the presentation model ([0048] test model uses a neural network as in [0028] for inference)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the neural network processing, modeling, and inference engine used to create a model of Kim with the modeling based on models of Vallelunga as they are both analogous art along with the claimed invention which teach solutions to ai modeling and information management, and the combination would lead to an improved system which would improve accuracy of the system as taught in [0086] of Vallelunga.
Examiner notes Kim teaches an apparatus, a plurality of computing devices, and a pipeline processing architecture generator ([0007] apparatus with processor, in communication with multiple devices as in [0004] and uses engines/generators as in [0058])
Regarding Claims 2 and 12, Kim teaches wherein the creating is based on one or more processing metrics associated with the computing devices, the processing metrics including at least one of a latency, an execution time, a memory consumed, an input/output data transfer time, a numerical accuracy and an inference time ([0028] accuracy is tracked along with [0040] memory consumption)
Regarding Claims 3 and 13, Kim does not teach an editor.
Vallelunga teaches further comprising generating one or more user cases via a drag-and-drop visual editor ([0058] a drag and drop editor is used to model)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the neural network processing, modeling, and inference engine used to create a model of Kim with the modeling based on models of Vallelunga as they are both analogous art along with the claimed invention which teach solutions to ai modeling and information management, and the combination would lead to an improved system which would improve accuracy of the system as taught in [0086] of Vallelunga.
Regarding Claims 4 and 14, Kim teaches further comprising generating one or more user cases via text input adherent to a domain-specific language ([0170] domain specific language)
Regarding Claims 5 and 15, Although Kim teaches an inference engine as in Claim 1 above.
Vallelunga teaches is associated with a processing pipeline that further includes any combination of one or more computational stages such as an input stage, a preprocessing stage, a postprocessing stage, and an output, wherein the processing pipeline is implemented on the computing devices as in [0092] where there are multiple stages including outputs.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the neural network processing, modeling, and inference engine used to create a model of Kim with the modeling based on models of Vallelunga as they are both analogous art along with the claimed invention which teach solutions to ai modeling and information management, and the combination would lead to an improved system which would improve accuracy of the system as taught in [0086] of Vallelunga.
Regarding Claims 6 and 16, Kim teaches wherein the inference engine can load and unload one or more neural network models generated from the presentation model by the neural network processing ([0173] the media/engine can load instructions from the models into software)
Regarding Claims 7 and 17, Kim teaches wherein one or more computing graphs associated with the presentation model are combined in any combination of sequential, parallel, and merged combination ([0027] merged models are used)
Regarding Claims 9 and 19, Kim teaches wherein the computing graphs are split so as to be executed on multiple compute devices attached to a network ([0003] everything is performed over a network on [0004-5] multiple devices)
Regarding Claims 10 and 20, Kim teaches wherein the computing devices include any combination of multi-core CPUs, multi-core GPUs, system memory, multi-core custom hardware accelerators, neural processing units (NPUs), deep learning accelerators (DLAs), and FPGA-based custom accelerators ([0029] mutli-core GPUs, NPUs, etc.)
Allowable Subject Matter
Claims 8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if the independent claims were amended in such a way as to overcome the 35 USC 101 rejection and any other rejections.
Conclusion
The prior art made of record is considered pertinent to applicant's disclosure.
US 20220414745 A1
Vallelunga; Jeronimo et al.
BACK END SERVER MODIFICATION AND MODEL VISUALIZATION
US 20220383117 A1
KIM; Jangho et al.
BAYESIAN PERSONALIZATION
US 20220365509 A1
Coffman; Valerie R. et al.
METHODS AND APPARATUS FOR MACHINE LEARNING PREDICTIONS OF MANUFACTURE PROCESSES
US 20220138004 A1
Nandakumar; Purushottaman
SYSTEM AND METHOD FOR AUTOMATED PRODUCTION AND DEPLOYMENT OF PACKAGED AI SOLUTIONS
US 20220130422 A1
Allibhai; Shamir et al.
TEXT-DRIVEN EDITOR FOR AUDIO AND VIDEO ASSEMBLY
US 20220122587 A1
Thomson; David et al.
TRAINING OF SPEECH RECOGNITION SYSTEMS
US 20190318029 A1
Simkin; David et al.
Back End Server Modification And Visualization
US 20180314751 A1
Filippi; Nicholas J. et al.
DETERMINING AFFINITIES FOR DATA SET SUMMARIZATIONS
US 20180314393 A1
Filippi; Nicholas J. et al.
LINKING DATA SET SUMMARIZATIONS USING AFFINITIES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH M WAESCO whose telephone number is (571)272-9913. The examiner can normally be reached on 8 AM - 5 PM M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BETH BOSWELL can be reached on (571) 272-6737. The fax phone number for the organization where this application or proceeding is assigned is 571-273-1348.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH M WAESCO/Primary Examiner, Art Unit 3625B 1/9/2026