Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION 2 . This Office Action responds to the Application filed on 5/30/2023. Claims 1-20 are pending. Claim Rejections - 35 USC § 112 3. The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. 4. Claims 7, 8, 15, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 and similarly claim 15 recited “ wherein the replacing the one or more connections comprises transforming a connection between a router and a hardware core of the SoC ”, however it is not apparent what the connection between and a hardware core of the SOC is transform to. Claim 8 and similarly claim 16 recited “ wherein the replacing the one or more connections comprises transforming a connection between a first router and a second router of the SoC ”, however it is not apparent what the connection between the first router and the second router of the SoC is transform to. Claim Rejections - 35 USC § 102 5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. 6. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Abramovici (U.S. Pub. No. 2011/0148457 A1) . As per claim 1, Abramovici discloses: A method for redacting Network-on-Chip ( NoC ) functionality in a System-on-Chip (SoC) architecture, comprising: receiving a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language (See Para [0025], i.e. software code, such as hardware description language (step 204). In this step, the design intent is converted into software code that represents the electronic system at the clock-cycle by clock-cycle level ) ; converting one or more routing tables related to the RTL source code with one or more configurable logic tables (See Para [0030], See Para [0033], i.e. constructs a fake FSM by modifying the design of the original FSM. The exemplary embodiment inserts in the original FSM a reconfigurable module that can be configured by configuration bits –[ FSM is considered as table that transition states ]) ; replacing one or more connections related to the RTL source code with one or more programmable multiplexers (See Para [0036], i.e. replacement MUX controlled by a configuration bit can be directly used to replace an FSM output signal without any state substitution , See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ) ; generating a transformed RTL source code for the SoC based on the one or more configurable logic tables and the one or more programmable multiplexers (See Figure 2, i.e. 204 RTL Coding, See Para [0033]-[0037], i.e. modifying the design of the original FSM … replacement MUX controlled by a configuration bit –[ prior art directed to designing of circuit design using RTL, the prior art directed to generation of obfuscated design by replacing of original circuit design with configurable FSM and Mux , therefore the modification is on original design in the RTL environment ]) ; and providing an attack-resistant obfuscated SoC based on the transformed RTL source code (See Para [0007] -[ 0010], i.e. p rotects the electronic system from counterfeiting and reverse-engineering by securing the FSM functionality of the control logic …obfuscates the behavior of the FSMs both from the standpoint of the foundry as well as from adversaries , See Para [0040]-[0051]). As per claim 2, Abramovici discloses all of the feature s of claim 1 as discloses above wherein Abramovici also discloses wherein the converting the one or more routing tables comprises determining a set of configurable parameters for the one or more configurable logic tables (See Para [0040] -[ 0051], i.e. have the n configuration bits stored in a secure memory. The level of obfuscation may differ depending on the number of configuration bits ). As per claim 3, Abramovici discloses all of the feature s of claim 2 as discloses above wherein Abramovici also discloses generating a set of programmable control bits for the one or more programmable multiplexers based on the set of configurable parameters (See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit ). As per claim 4, Abramovici discloses all of the feature s of claim 2 as discloses above wherein Abramovici also discloses applying an activation package associated with the set of configurable parameters to the attack-resistant obfuscated SoC to obtain an original design for the SoC (See Para [0022], i.e. assign a unique key to the reconfigurable module so that the configuration data is encrypted with the key , See Para [0040]-[0051], i.e. configuration data or the initial state may be encrypted with a key assigned to the chip ). As per claim 5, Abramovici discloses all of the feature s of claim 1 as discloses above wherein Abramovici also discloses wherein the one or more programmable multiplexers are related to one or more switch configurations for the SoC. (See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit ) As per claim 6, Abramovici discloses all of the feature s of claim 1 as discloses above wherein Abramovici also discloses configuring the one or more programmable multiplexers as a set of multiplexers to reduce multiplexer- demuliplexer heterogeneity associated with topology obfuscation (See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ). As per claim 7, Abramovici discloses all of the feature s of claim 1 as discloses above wherein Abramovici also discloses wherein the replacing the one or more connections comprises transforming a connection between a router and a hardware core of the SoC (See Para [0036], i.e. replacement MUX controlled by a configuration bit can be directly used to replace an FSM output signal without any state substitution , See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ). As per claim 8, Abramovici discloses all of the feature s of claim 1 as discloses above wherein Abramovici also discloses wherein the replacing the one or more connections comprises transforming a connection between a first router and a second router of the SoC (See Para [0036], i.e. replacement MUX controlled by a configuration bit can be directly used to replace an FSM output signal without any state substitution , See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ). As per claim 9, Abramovici discloses: An apparatus comprising at least one processor and at least one memory including program code, the at least one memory and the program code configured to, with the at least one processor, cause the apparatus to at (See Figure 1, i.e. memory 112 and computing device 102) least: receive a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language (See Para [0025], i.e. software code, such as hardware description language (step 204). In this step, the design intent is converted into software code that represents the electronic system at the clock-cycle by clock-cycle level ) ; convert one or more routing tables related to the RTL source code with one or more configurable logic tables (See Para [0030], See Para [0033], i.e. constructs a fake FSM by modifying the design of the original FSM. The exemplary embodiment inserts in the original FSM a reconfigurable module that can be configured by configuration bits –[ FSM is considered as table that transition states ]) ; replace one or more connections related to the RTL source code with one or more programmable multiplexers (See Para [0036], i.e. replacement MUX controlled by a configuration bit can be directly used to replace an FSM output signal without any state substitution , See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ) ; generate a transformed RTL source code for the SoC based on the one or more configurable logic tables and the one or more programmable multiplexers (See Figure 2, i.e. 204 RTL Coding, See Para [0033]-[0037], i.e. modifying the design of the original FSM … replacement MUX controlled by a configuration bit –[ prior art directed to designing of circuit design using RTL, the prior art directed to generation of obfuscated design by replacing of original circuit design with configurable FSM and Mux , therefore the modification is on original design in the RTL environment ]) ; and provide an attack-resistant obfuscated SoC based on the transformed RTL source code (See Para [0007] -[ 0010], i.e. protects the electronic system from counterfeiting and reverse-engineering by securing the FSM functionality of the control logic…obfuscates the behavior of the FSMs both from the standpoint of the foundry as well as from adversaries, See Para [0040]-[0051]). As per claim 10, Abramovici discloses all of the feature s of claim 9 as discloses above wherein Abramovici also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: determine a set of configurable parameters for the one or more configurable logic tables (See Para [0040] -[ 0051], i.e. have the n configuration bits stored in a secure memory. The level of obfuscation may differ depending on the number of configuration bits ). As per claim 11, Abramovici discloses all of the feature s of claim 10 as discloses above wherein Abramovici also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: generate a set of programmable control bits for the one or more programmable multiplexers based on the set of configurable parameters (See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit ) As per claim 12, Abramovici discloses all of the feature s of claim 10 as discloses above wherein Abramovici also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: apply an activation package associated with the set of configurable parameters to the attack-resistant obfuscated SoC to obtain an original design for the SoC (See Para [0022], i.e. assign a unique key to the reconfigurable module so that the configuration data is encrypted with the key , See Para [0040]-[0051], i.e. configuration data or the initial state may be encrypted with a key assigned to the chip ). As per claim 13, Abramovici discloses all of the feature s of claim 9 as discloses above wherein Abramovici also discloses wherein the one or more programmable multiplexers are related to one or more switch configurations for the SoC (See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit ) As per claim 14, Abramovici discloses all of the feature s of claim 9 as discloses above wherein Abramovici also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: configure the one or more programmable multiplexers as a set of multiplexers to reduce multiplexer- demuliplexer heterogeneity associated with topology obfuscation (See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ). As per claim 15, Abramovici discloses all of the feature s of claim 9 as discloses above wherein Abramovici also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: transform a connection between a router and a hardware core of the SoC (See Para [0036], i.e. replacement MUX controlled by a configuration bit can be directly used to replace an FSM output signal without any state substitution , See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ). As per claim 16, Abramovici discloses all of the feature s of claim 9 as discloses above wherein Abramovici also discloses wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: transform a connection between a first router and a second router of the SoC (See Para [0036], i.e. replacement MUX controlled by a configuration bit can be directly used to replace an FSM output signal without any state substitution , See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ). As per claim 17, Abramovici discloses: A non-transitory computer storage medium comprising instructions, the instructions being configured to cause one or more processors to at least perform operations configured (See Figure 1, i.e. memory 112 and computing device 102) to: receive a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language (See Para [0025], i.e. software code, such as hardware description language (step 204). In this step, the design intent is converted into software code that represents the electronic system at the clock-cycle by clock-cycle level ) ; convert one or more routing tables related to the RTL source code with one or more configurable logic tables (See Para [0030], See Para [0033], i.e. constructs a fake FSM by modifying the design of the original FSM. The exemplary embodiment inserts in the original FSM a reconfigurable module that can be configured by configuration bits –[ FSM is considered as table that transition states ]) ; replace one or more connections related to the RTL source code with one or more programmable multiplexers (See Para [0036], i.e. replacement MUX controlled by a configuration bit can be directly used to replace an FSM output signal without any state substitution , See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit 704 connected to MUX 202 and the transition replacement is controlled by MUX 702 and configuration bit 704 ) ; generate a transformed RTL source code for the SoC based on the one or more configurable logic tables and the one or more programmable multiplexers (See Figure 2, i.e. 204 RTL Coding, See Para [0033]-[0037], i.e. modifying the design of the original FSM … replacement MUX controlled by a configuration bit –[ prior art directed to designing of circuit design using RTL, the prior art directed to generation of obfuscated design by replacing of original circuit design with configurable FSM and Mux , therefore the modification is on original design in the RTL environment ]) ; and provide an attack-resistant obfuscated SoC based on the transformed RTL source code (See Para [0007] -[ 0010], i.e. protects the electronic system from counterfeiting and reverse-engineering by securing the FSM functionality of the control logic…obfuscates the behavior of the FSMs both from the standpoint of the foundry as well as from adversaries, See Para [0040]-[0051]). As per claim 18, Abramovici discloses all of the feature s of claim 17 as discloses above wherein Abramovici also discloses wherein the operations are further configured to: determine a set of configurable parameters for the one or more configurable logic tables (See Para [0040] -[ 0051], i.e. have the n configuration bits stored in a secure memory. The level of obfuscation may differ depending on the number of configuration bits ). As per claim 19, Abramovici discloses all of the feature s of claim 18 as discloses above wherein Abramovici also discloses wherein the operations are further configured to: generate a set of programmable control bits for the one or more programmable multiplexers based on the set of configurable parameters (See Para [0037], i.e. The reconfigurable module may include multiplexer (MUX) 702 and configuration bit ). As per claim 20, Abramovici discloses all of the feature s of claim 18 as discloses above wherein Abramovici also discloses wherein the operations are further configured to: apply an activation package associated with the set of configurable parameters to the attack-resistant obfuscated SoC to obtain an original design for the SoC (See Para [0022], i.e. assign a unique key to the reconfigurable module so that the configuration data is encrypted with the key , See Para [0040]-[0051], i.e. configuration data or the initial state may be encrypted with a key assigned to the chip ). Conclusion 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NHA T NGUYEN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1405 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8:00AM-5:00PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jack Chiang can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-7483 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NHA T NGUYEN/ Primary Examiner, Art Unit 2851