Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References:
Gulati (US 8929153) – memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, relates to claimed first signal line and a second signal line.
Non-patent Literature – Kim, Yoongu – Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors, Published ACM SIGARCH, Vol 42, Issue 3, page 361-372, relates to claimed memory core.
Scheueriein, R.E., Offset word-line architecture for scaling DRAMs to the gigabit liver, IEEE Journal of Solid-State Circuits, Vol 23, Issue 1, 1988, pages 41-47, relates to claimed first signal line and second signal line.
Drawings filed 5/30/2023 are accepted.
Oath filed 5/30/2023 has been placed in the file.
In order to potentially overcome the rejections, the Examiner suggests amending the claimed limitations to further clarify the memory core comprising switching circuit that switches between a first mode and second mode in relation to the transistors (Claim 1); how the semiconductor apparatus comprising a control circuit that performs matrix calculation (Claim 7); and the memory core comprising switching circuit that switches between a first mode and second mode in relation to the transistors (Claim 14), subject to and limited to the original Applicant’s disclosure.
Allowable Subject Matter
Claims 4, 10, 12, 13, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
For Claims 4, the prior art discloses and/or renders obvious the limitations from Claims 1. The prior art does not appear to disclose the limitations from Claims 4 when viewed in combination with their respective base claims.
For Claims 10, 12-13, the prior art discloses and/or renders obvious the limitations from Claim 7. The prior art does not appear to disclose the limitations from Claims 10, 12-13 when viewed in combination with their respective base claims.
For Claim 15, the prior art discloses and/or renders obvious the limitations from Claims 14. The prior art does not appear to disclose the limitations from Claim 15 when viewed in combination with their respective base claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 202100407586) and in view of Naffziger (US 6166946)
Claim 1. Li discloses A memory core (eg., 0024 Fig. 1 - a memory array 110) comprising:
a first signal line (eg., 0026 Fig. 2- Each column of memory cells in each of the memory blocks configured to have a multiplexer, a bit line);
a second signal line (eg., 0026 Fig. 2 - Each row of memory cells in memory array 110 are configured to have at least one word line);
a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element (eg., 0027 Fig. 2 - fifth transistor M5 and the sixth transistor M6 are enabled, the method of driving the voltage inversion of the node 202 or node 204 is used to write the data into the memory cell 200 through the bit line BL ); and
Li does not disclose, but Naffziger discloses
switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and the second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor (eg., col 4:65 – col 5:5, FIG. 3, the memory cell 100 includes, similar to conventional memory cell 15, a storage element 18, ports 21 and 24, bit lines 32 and 34, and switching elements 26, 28, 42, and 44.; col 8:3-8 - switching elements 42 and 44 (FIG. 3) are activated during the first half of the cycle of the CK signal, thereby forcing the values of bit lines 32 and 34 to V.sub.dd or, in other words, to a logical high. During the last half of the cycle of the CK signal, the switching elements 42 and 44 are deactivated, thereby isolating bit lines 32 and 34 from V.sub.dd.; col 8:9-13 - during the first half of the cycle of the CK signal, AND gates 155 and 157 are configured to deassert the values transmitted across lines 116 and 126, respectively, regardless of the values of the read signal and the write signal respectively received from lines 161 and 163).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with Naffziger, providing the benefit of performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle (see Naffziger, col 1:6-10).
Claim 2. Li does not disclose, but Naffziger discloses
wherein, in the first mode, the first signal line operates as a word line, and the second signal line operates as a bit line (eg., col 8:51-59 - Since the mode signal is a logical high, the value stored in the storage element 18 is read via bit line 34 and the value to be written into the storage element 18 is transmitted to bit line 32. If the value to be written into the storage element 18 is a logical high, then the value of port 21 is forced to a logical low, and the value of port 24 is, therefore, forced to a logical high. As a result, the write operation and the read operation are performed during the same cycle of the CK signal).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with Naffziger, providing the benefit of performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle (see Naffziger, col 1:6-10).
Claim 3. Li does not disclose, but Naffziger discloses
wherein, in the second mode, the first signal line operates as the bit line, and the second signal line operates as the word line (eg., col 8:60-67 - However, if the value to be written into the storage element 18 is a logical low, then the values at ports 21 and 24 remain unchanged. Therefore, at the beginning of the next cycle of the CK signal, the mode signal toggles to a logical low, and the value on input line 128 (i.e., the value to be written into the storage element 18) is maintained on input line 128).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with Naffziger, providing the benefit of performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle (see Naffziger, col 1:6-10).
Claim 14. Li discloses A memory core (eg., 0025 Fig. 1 - the memory array 110 comprises a plurality of memory cells.) comprising:
a word line and a bit line arranged in a matrix form (eg., 9927 Fig. 2 - memory cell 200 is connected to external elements (e.g. bit line BL, inverted bit line /BL and word line WL) ); a
a first transistor coupled between the bit line and a data storage element; a second transistor coupled between the word line and the data storage element (eg., 0027 Fig. 2 - fifth transistor M5 and the sixth transistor M6 are enabled, the method of driving the voltage inversion of the node 202 or node 204 is used to write the data into the memory cell 200 through the bit line BL ); and
Li does not disclose, but Naffziger discloses
a switching circuit configured to:
control the first transistor according to a level of the word line and turn off the second transistor when a mode selection signal has a level defining an operation mode of the memory core as a first mode and control the second transistor according to a level of the bit line and turn off the first transistor when the mode selection signal has a level defining the operation mode of the memory core as a second mode (eg., col 4:65 – col 5:5, FIG. 3, the memory cell 100 includes, similar to conventional memory cell 15, a storage element 18, ports 21 and 24, bit lines 32 and 34, and switching elements 26, 28, 42, and 44.; col 8:3-8 - switching elements 42 and 44 (FIG. 3) are activated during the first half of the cycle of the CK signal, thereby forcing the values of bit lines 32 and 34 to V.sub.dd or, in other words, to a logical high. During the last half of the cycle of the CK signal, the switching elements 42 and 44 are deactivated, thereby isolating bit lines 32 and 34 from V.sub.dd.; col 8:9-13 - during the first half of the cycle of the CK signal, AND gates 155 and 157 are configured to deassert the values transmitted across lines 116 and 126, respectively, regardless of the values of the read signal and the write signal respectively received from lines 161 and 163).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with Naffziger, providing the benefit of performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle (see Naffziger, col 1:6-10).
Claims 5, 6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 202100407586) and in view of Naffziger (US 6166946) and further in view of Kim (US 20160064056)
Claim 5. Li in view of Naffziger does not disclose, but Kim discloses
wherein the memory core further includes: a word line driver; and a bit line sense amplifier,
wherein, in the first mode, the switching circuit is configured to couple the first signal line to the word line driver and configured to couple the second signal line to the bit line sense amplifier (eg., [0074] Referring to FIGS. 6 and 7, portion 390 of the first bank array 310 includes the sub array block SCB, the bit-line sense amplifier regions BLSAB, the sub word-line driver regions SWB and conjunction regions CONJ.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with
Naffziger, with Kim, providing the benefit of off-voltage level of the second word-line after deactivation of the first word-line is controlled to have different voltage level from the off-voltage level of the second word-line during the first word-line activated. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other (see Kim, 0005).
Claim 6. Li in view of Naffziger does not disclose, but Kim discloses
wherein the memory core further includes: a word line driver; and a bit line sense amplifier,
wherein, in the second mode, the switching circuit is configured to couple the first signal line to the bit line sense amplifier and configured to couple the second signal line to the word line driver. (eg., [0074] Referring to FIGS. 6 and 7, portion 390 of the first bank array 310 includes the sub array block SCB, the bit-line sense amplifier regions BLSAB, the sub word-line driver regions SWB and conjunction regions CONJ.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with
Naffziger, with Kim, providing the benefit of off-voltage level of the second word-line after deactivation of the first word-line is controlled to have different voltage level from the off-voltage level of the second word-line during the first word-line activated. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other (see Kim, 0005).
Claim 16. Li in view of Naffziger does not disclose, but Kim discloses
wherein the memory core further includes: a word line driver; and a bit line sense amplifier,
wherein, in the first mode, the switching circuit is configured to couple the word line to the word line driver and configured to couple the bit line to the bit line sense amplifier (eg., [0074] FIGS. 6 and 7, portion 390 of the first bank array 310 includes the sub array block SCB, the bit-line sense amplifier regions BLSAB, the sub word-line driver regions SWB and conjunction regions CONJ.).
wherein, in the second mode, the switching circuit is configured to couple the word line to the bit line sense amplifier and configured to couple the bit line to the word line driver (eg., [0074] Referring to FIGS. 6 and 7, portion 390 of the first bank array 310 includes the sub array block SCB, the bit-line sense amplifier regions BLSAB, the sub word-line driver regions SWB and conjunction regions CONJ.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with
Naffziger, with Kim, providing the benefit of off-voltage level of the second word-line after deactivation of the first word-line is controlled to have different voltage level from the off-voltage level of the second word-line during the first word-line activated. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other (see Kim, 0005).
Claims 7, 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 202100407586) and in view of Naffziger (US 6166946) and further in view of He (US 20240103879)
Claim 7. Li discloses A semiconductor apparatus (eg., 0024 Fig. 1 - memory device 100) comprising:
a memory core including a plurality of unit memory regions having a plurality of unit cells coupled between a plurality of first signal lines and a plurality of second signal lines (eg., 0025 Fig. 1, 2 - memory cells are arranged by n columns and are divided into k memory blocks 110-1˜110-k. Each memory block of the memory blocks 110-1˜110-k corresponds to the operations of reading and writing),
wherein each of the plurality of unit cells is configured to perform data input/output (I/O) according to a level of a corresponding first signal line through a corresponding second signal line when an operation mode of the memory core is set to a first mode and configured to perform data I/O according to a level of the corresponding second signal line through the corresponding first signal line when the operation mode of the memory core is set to a second mode (eg., 0027 Fig. 2 - fifth transistor M5 and the sixth transistor M6 are NMOS transistors, and can be regarded as transmission transistors. The memory cell 200 is connected to external elements (e.g. bit line BL, inverted bit line /BL and word line WL) through the fifth transistor M5 and the sixth transistor M6. ) );
a data I/O circuit coupled between the memory core and an I/O pad circuit (eg., 0026 Fig. 1 - connect each column of memory cells to a corresponding input/output interface of the input/output circuit 140 through the multiplexer configured for the column of the plurality of memory cells. ); and
Li does not disclose, but Naffziger discloses
controlling mode switching between the first mode and the second mode and a data exchange between the plurality of unit memory regions and the data I/O circuit (eg., col 4:65 – col 5:5, FIG. 3, the memory cell 100 includes, similar to conventional memory cell 15, a storage element 18, ports 21 and 24, bit lines 32 and 34, and switching elements 26, 28, 42, and 44.; col 8:3-8 - switching elements 42 and 44 (FIG. 3) are activated during the first half of the cycle of the CK signal, thereby forcing the values of bit lines 32 and 34 to V.sub.dd or, in other words, to a logical high. During the last half of the cycle of the CK signal, the switching elements 42 and 44 are deactivated, thereby isolating bit lines 32 and 34 from V.sub.dd.; col 8:9-13 - during the first half of the cycle of the CK signal, AND gates 155 and 157 are configured to deassert the values transmitted across lines 116 and 126, respectively, regardless of the values of the read signal and the write signal respectively received from lines 161 and 163).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with Naffziger, providing the benefit of performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle (see Naffziger, col 1:6-10).
Li in view of Naffziger does not disclose, but He discloses
a control circuit configured to, in response to a transposed matrix calculation command, perform a transposed matrix calculation by (eg., 0049 Fig. 5- A load-and transpose instruction is received (block 502). training data having a plurality of matrixes is loaded (block 504) and the plurality of matrixes are transposed to form a plurality of transposed matrixes (block 506). An application 110, for instance, provides the single load and transpose instruction 202 as an input to a control unit of the SIMD processor unit 106. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with
Naffziger, with He, providing the benefit the transpose instruction reduces a number of operations and instructions otherwise involved in loading data elements and therefore increases operational efficiency of devices that employ these techniques (see He, 0009).
Claim 8. Li does not disclose, but Naffziger discloses
wherein, in the first mode, the first signal line operates as a word line and the second signal line operates as a bit line (eg., col 8:51-59 - Since the mode signal is a logical high, the value stored in the storage element 18 is read via bit line 34 and the value to be written into the storage element 18 is transmitted to bit line 32. If the value to be written into the storage element 18 is a logical high, then the value of port 21 is forced to a logical low, and the value of port 24 is, therefore, forced to a logical high. As a result, the write operation and the read operation are performed during the same cycle of the CK signal).
wherein, in the second mode, the first signal line operates as the bit line and the second signal line operates as the word line (eg., col 8:60-67 - However, if the value to be written into the storage element 18 is a logical low, then the values at ports 21 and 24 remain unchanged. Therefore, at the beginning of the next cycle of the CK signal, the mode signal toggles to a logical low, and the value on input line 128 (i.e., the value to be written into the storage element 18) is maintained on input line 128).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with Naffziger, providing the benefit of performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle (see Naffziger, col 1:6-10).
Claim 9. Li discloses wherein the unit cell includes: a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element (eg., 0027 Fig. 2 - fifth transistor M5 and the sixth transistor M6 are enabled, the method of driving the voltage inversion of the node 202 or node 204 is used to write the data into the memory cell 200 through the bit line BL ); and
Li does not disclose, but Naffziger discloses
a switching circuit configured to, in response to a mode selection signal, switch the operation mode of the memory core between the first mode and the second mode, the first mode controlling the first transistor according to the level of the first signal line and turning off the second transistor and the second mode controlling the second transistor according to the level of the second signal line and turning off the first transistor (eg., col 4:65 – col 5:5, FIG. 3, the memory cell 100 includes, similar to conventional memory cell 15, a storage element 18, ports 21 and 24, bit lines 32 and 34, and switching elements 26, 28, 42, and 44.; col 8:3-8 - switching elements 42 and 44 (FIG. 3) are activated during the first half of the cycle of the CK signal, thereby forcing the values of bit lines 32 and 34 to V.sub.dd or, in other words, to a logical high. During the last half of the cycle of the CK signal, the switching elements 42 and 44 are deactivated, thereby isolating bit lines 32 and 34 from V.sub.dd.; col 8:9-13 - during the first half of the cycle of the CK signal, AND gates 155 and 157 are configured to deassert the values transmitted across lines 116 and 126, respectively, regardless of the values of the read signal and the write signal respectively received from lines 161 and 163).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with Naffziger, providing the benefit of performing a writing operation and a reading operation on a memory cell, such as a static-random-access-memory (SRAM) cell, during the same clock cycle (see Naffziger, col 1:6-10).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Li (US 202100407586) and in view of Naffziger (US 6166946) and further in view of He (US 20240103879) and Kim (US 20160064056)
Claim 11. Li in view of Naffziger does not disclose, but Kim discloses
wherein the memory core further includes: a word line driver; and a bit line sense amplifier,
wherein, in the first mode, the switching circuit is configured to couple the first signal line to the word line driver and configured to couple the second signal line to the bit line sense amplifier (eg., [0074] FIGS. 6 and 7, portion 390 of the first bank array 310 includes the sub array block SCB, the bit-line sense amplifier regions BLSAB, the sub word-line driver regions SWB and conjunction regions CONJ.).
wherein, in the second mode, the switching circuit is configured to couple the first signal line to the bit line sense amplifier and configured to couple the second signal line to the word line driver (eg., [0074] Referring to FIGS. 6 and 7, portion 390 of the first bank array 310 includes the sub array block SCB, the bit-line sense amplifier regions BLSAB, the sub word-line driver regions SWB and conjunction regions CONJ.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory array having signal lines and transistors as disclosed by Li with
Naffziger, with Kim, providing the benefit of off-voltage level of the second word-line after deactivation of the first word-line is controlled to have different voltage level from the off-voltage level of the second word-line during the first word-line activated. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other (see Kim, 0005).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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