DETAILED ACTION
This office action is in response to the amendment filed on 07/14/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/18/2025 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 19 is objected to because of the following informalities: Claim 19 “whether” on line 10 should be deleted. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 15, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Zhan et al US 10637537.
Regarding Claim 1, Zhan teaches (Figures 2-5) A voltage conversion circuit (Fig.2 ), comprising, and a buck-boost circuit (202) having an H-bridge structure (see fig. 3), a first resistor and a second resistor (306 and 328) coupled to pass current from within the buck-boost circuit (Col. 5 lines 51-60 and col. 6 lines 15-28); a detection circuit (212 and 214) including at least one sampling circuit (with 214) and a controller (212) for determining current through at least one of the first and second resistors (306 and 328); and wherein: the buck-boost circuit comprises a first bridge arm (Q1-Q2), a second bridge arm (Q3-Q4), and an inductor (L) coupled between the first bridge arm and the second bridge arm, two ends of the first bridge arm are connected to two ends of the second bridge arm in a one-to-one correspondence (304 and gnd), one end (304) of the first bridge arm is connected to one input end of the buck-boost circuit through the first detection resistor, the other end (gnd) of the first bridge arm is connected to the other input end of the buck-boost circuit, one end (322) of the second bridge arm is connected to one output end of the buck-boost circuit through the second detection resistor, and the other end (gnd) of the second bridge arm is connected to the other output end of the buck-boost circuit; and the detection circuit is configured to: separately performing voltage sampling on the first resistor (Voltage of 306) and the second resistor (Voltage of 328); and output a current detection signal (Vsum, Col. 5 lines 22-50) based on a maximum voltage sampled from the first resistor and the second resistor (max voltage of the resistor), wherein the maximum voltage is a voltage of at least one of the first and second resistor (306 and 328) and corresponds to an inductor current (current at L) of the inductor, and the current detection signal indicates a value of the inductor current (inductor current of L). (For Example: Col. 6-8)
Regarding Claims 3 and 17, Zhan teaches (Figures 2-5) wherein the buck-boost circuit (202) further comprises an input capacitor (305), one end of the input capacitor is connected to the high-potential input end of the buck-boost circuit (304), the other end of the input capacitor is connected to the low-potential input end of the buck-boost circuit (gnd), and the first detection resistor (306) is located between the input capacitor and the first bridge arm (Q1-Q2). (For Example: Col. 6-8)
Regarding Claim 5, Zhan teaches (Figures 2-5) wherein the buck-boost circuit (202) further comprises an output capacitor (326), one end of the output capacitor is connected to the high-potential output end of the buck-boost circuit (322), the other end of the output capacitor is connected to the low-potential output end of the buck-boost circuit (gnd), and the second detection resistor (328) is located between the output capacitor and the second bridge arm (Q3-Q4). (For Example: Col. 6-8)
Regarding Claim 6, Zhan teaches (Figures 2-5) wherein the detection circuit further comprises a first sampling circuit (346), a second sampling circuit (348), and a combiner circuit (344); the first sampling circuit is separately connected to the first detection resistor (306) and the combiner circuit (344), and the second sampling circuit (348) is separately connected to the second detection resistor (328) and the combiner circuit (344); the first sampling circuit is configured to output a first sampled signal (Vsumbuck) to the combiner circuit based on the first resistor voltage of the first detection resistor (Irsin), wherein a voltage of the first sampled signal meets a positive correlation with the first resistor voltage (with adder 346); the second sampling circuit (348) is configured to output a second sampled signal (Vsumboost) to the combiner circuit (344) based on the second resistor voltage of the second detection resistor (irsout, col. 8 lines 1-3), wherein a voltage of the second sampled signal meets a positive correlation with the second resistor voltage (with adder 348); and the combiner circuit (344) is configured to output the current detection signal (Vsum) based on the maximum voltage (voltage at resistor 306 and 328) in the first sampled signal and the second sampled signal (with mode signal, if Vin is larger than the converter operates in buck mode and if the Vin is smaller than the converter operates in buck mode, see col. 7). (For Example: Col. 6-8)
Regarding Claim 15, Zhan teaches (Figures 2-5) An electronic device (Vin source and Fig. 2 circuitry and load), comprising: a voltage conversion circuit (Fig.2 ); a buck-boost circuit (302) of an H-bridge structure; a first resistor and a second resistor (306 and 328) coupled to pass current from within the buck-boost circuit (Col. 5 lines 51-60 and col. 6 lines 15-28); a detection circuit (212 and 214) including at least one sampling circuit (with 214) and a controller (212) for determining current through at least one of the first and second resistors (306 and 328), and wherein: the buck-boost circuit comprises a first bridge arm (Q1-Q2), a second bridge arm (Q3-Q4), and an inductor (L), the inductor is located between the first bridge arm and the second bridge arm, two ends of the first bridge arm are connected to two ends of the second bridge arm in a one-to-one correspondence (304 and gnd), one end (304) of the first bridge arm is connected to one input end of the buck-boost circuit through the first detection resistor, the other end (gnd) of the first bridge arm is connected to the other input end of the buck-boost circuit, one end (322) of the second bridge arm is connected to one output end of the buck-boost circuit through the second detection resistor, and the other end (gnd) of the second bridge arm is connected to the other output end of the buck-boost circuit; and the detection circuit is configured to: separately performing voltage sampling on the first resistor (Voltage of 306) and the second resistor (Voltage of 328); and output a current detection signal (Vsum, Col. 5 lines 22-50) based on a maximum voltage sampled from the first resistor and the second resistor (max voltage of the resistor), wherein the maximum voltage is a voltage of at least one of the first and second resistor (306 and 328) and corresponds to an inductor current (current at L) of the inductor, and the current detection signal indicates a value of the inductor current (inductor current of L). (For Example: Col. 6-8)
Regarding Claim 19, Zhan teaches (Figures 2-5) A voltage conversion circuit (Fig. 2) comprising: a buck-boost circuit having an H-bridge structure (204); a first resistor and a second resistor (306 and 328) coupled to pass current from within the buck-boost circuit (Col. 5 lines 51-60 and col. 6 lines 15-28); a detection circuit (212 and 214) including at least one sampling circuit (with 214) and a controller (212) for determining current through at least one of the first and second resistors (306 and 328), wherein the detection circuit is configured to: separately performing voltage sampling on the first resistor (Voltage of 306) and the second resistor (Voltage of 328); and output a current detection signal (Vsum, Col. 5 lines 22-50) which indicated whether a maximum voltage sampled from either of the first and second resistor (voltage sampled used by 343 by from resistors 306 and 328), wherein the maximum voltage corresponds to an inductor current (inductor current) of the boost buck circuit (because the IL current is the current used to determine the Vsum). (For Example: Col. 6-8)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan in view of Kato JP2005237052.
Regarding Claims 2 and 16, Zhan teaches (Figures 2-5) the circuit.
Zhan does not teach wherein one end of the first bridge arm is connected to a low-potential input end of the buck-boost circuit through the first detection resistor, and the other end of the first bridge arm is connected to a high-potential input end of the buck-boost circuit; and one end of the second bridge arm is connected to a low-potential output end of the buck-boost circuit through the second detection resistor, and the other end of the second bridge arm is connected to a high-potential output end of the buck-boost circuit.
Kato teaches (Figure 1) wherein one end of the first bridge arm (bottom terminal of sw2) is connected to a low-potential input end (gnd) of the buck-boost circuit through the first detection resistor (rs2), and the other end of the first bridge arm is connected to a high-potential input end of the buck-boost circuit (top terminal of sw1); and one end of the second bridge arm (bottom terminal of sw3) is connected to a low-potential output end of the buck-boost circuit (gnd) through the second detection resistor (rs1), and the other end of the second bridge arm is connected to a high-potential output end of the buck-boost circuit (Top terminal of sw4).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include wherein one end of the first bridge arm is connected to a low-potential input end of the buck-boost circuit through the first detection resistor, and the other end of the first bridge arm is connected to a high-potential input end of the buck-boost circuit; and one end of the second bridge arm is connected to a low-potential output end of the buck-boost circuit through the second detection resistor, and the other end of the second bridge arm is connected to a high-potential output end of the buck-boost circuit, as taught by Kato to provide a regulator suitable for applications in which the difference between the input voltage and the output voltage is positive or negative.
Regarding Claims 4 and 18, Zhan teaches (Figures 2-5) wherein the buck-boost circuit (202) further comprises an input capacitor (305), one end of the input capacitor is connected to the high-potential input end of the buck-boost circuit (304), the other end of the input capacitor is connected to the low-potential input end of the buck-boost circuit (gnd), and the first detection resistor (306) is located between the input capacitor and the first bridge arm (Q1-Q2). (For Example: Col. 6-8)
Claim(s) 7-9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan in view of Lyle US 2015/0035504.
Regarding Claim 7, Zhan teaches (Figures 2-5) the circuit.
Zhan does not teach wherein the first sampling circuit comprises a first operational amplifier circuit, one input end of the first operational amplifier circuit is connected to one end of the first resistor, the other input end of the first operational amplifier circuit is connected to the other end of the first resistor, and an output end of the first operational amplifier circuit is configured to output the first sampled signal.
Lyle teaches (Figure 5) wherein the first sampling circuit (504) comprises a first operational amplifier circuit (504), one input end of the first operational amplifier circuit is connected to one end of the first resistor (Rs1), the other input end of the first operational amplifier circuit is connected to the other end of the first resistor (Rs1), and an output end of the first operational amplifier circuit is configured to output the first sampled signal (output of 504). (For Example: par. 39-40)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include wherein the first sampling circuit comprises a first operational amplifier circuit, one input end of the first operational amplifier circuit is connected to one end of the first resistor, the other input end of the first operational amplifier circuit is connected to the other end of the first resistor, and an output end of the first operational amplifier circuit is configured to output the first sampled signal, as taught by Lyle to improve the accuracy of the sensed signal.
Regarding Claims 8 and 9, Zhan teaches (Figures 2-5) the circuit.
Zhan does not teach wherein the second sampling circuit comprises a second operational amplifier circuit, one input end of the second operational amplifier circuit is connected to one end of the second resistor, the other input end of the second operational amplifier circuit is connected to the other end of the second resistor, and an output end of the second operational amplifier circuit is configured to output the second sampled signal.
Lyle teaches (Figure 5) wherein the second sampling circuit (202) comprises a second operational amplifier circuit (202), one input end of the second operational amplifier circuit is connected to one end of the second resistor (Rs2), the other input end of the second operational amplifier circuit is connected to the other end of the second resistor (Rs2, also see fig. 2), and an output end of the second operational amplifier circuit is configured to output the second sampled signal (output of 202). (For Example: par. 19 and 39-40)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include wherein the second sampling circuit comprises a second operational amplifier circuit, one input end of the second operational amplifier circuit is connected to one end of the second resistor, the other input end of the second operational amplifier circuit is connected to the other end of the second resistor, and an output end of the second operational amplifier circuit is configured to output the second sampled signal, as taught by Lyle to improve the accuracy of the sensed signal.
Regarding Claim 20, Zhan teaches (Figures 2-5) wherein the detection circuit (212 and 214) further comprises a first sampling circuit (343), a second sampling circuit (348). (For Example: Col. 6-8)
Zhan does not teach a combiner circuit wherein the combiner circuit combines the detected current levels produced by the first and second sampling circuits.
Lyle teaches (Figure 5) a combiner circuit (506) wherein the combiner circuit combines the detected current levels produced by the first and second sampling circuits (input to the 506 circuitry). (For Example: par. 43)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include a combiner circuit wherein the combiner circuit combines the detected current levels produced by the first and second sampling circuits, as taught by Lyle to improve the accuracy of the sensed signal.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan in view of Tietema et al. US 2020/0389093.
Regarding Claim 10, Zhan teaches (Figures 2-5) the combiner (344).
Zhan does not teach wherein the combiner circuit comprises a first diode and a second diode, an anode of the first diode is connected to the first sampling circuit, an anode of the second diode is connected to the second sampling circuit, a cathode of the first diode is connected to a cathode of the second diode through a first connection point, and the first connection point is configured to output the current detection signal.
Kato teaches (Figure 1) wherein the combiner circuit (R3 and D2-D3) comprises a first diode and a second diode (D2-D3), an anode of the first diode is connected to the first sampling circuit (36), an anode of the second diode is connected to the second sampling circuit (34), a cathode of the first diode is connected to a cathode of the second diode through a first connection point (38), and the first connection point is configured to output the current detection signal. (For Example: Par. 63-71)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include wherein the combiner circuit comprises a first diode and a second diode, an anode of the first diode is connected to the first sampling circuit, an anode of the second diode is connected to the second sampling circuit, a cathode of the first diode is connected to a cathode of the second diode through a first connection point, and the first connection point is configured to output the current detection signal, as taught by Tietema to improve the response time of the detection circuitry.
Regarding Claim 13, Zhan teaches (Figures 2-5) the combiner (344).
Zhan does not teach wherein the combiner circuit further comprises a ground resistor, one end of the ground resistor is connected to the first connection point, and the other end of the ground resistor is grounded.
Kato teaches (Figure 1) wherein the combiner circuit (D2-D3 and R3 ) further comprises a ground resistor (R3), one end of the ground resistor is connected to the first connection point (38), and the other end of the ground resistor is grounded (gnd through 30). (For Example: Par. 63-71)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include wherein the combiner circuit further comprises a ground resistor, one end of the ground resistor is connected to the first connection point, and the other end of the ground resistor is grounded, as taught by Tietema to improve the response time of the detection circuitry.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan in view of Lyle US 2015/0035504 and further in view of Tietema et al. US 2020/0389093.
Regarding Claim 11, Zhan teaches (Figures 2-5) the combiner (344).
Zhan does not teach wherein the combiner circuit comprises a first diode and a second diode, an anode of the first diode is connected to the first sampling circuit, an anode of the second diode is connected to the second sampling circuit, a cathode of the first diode is connected to a cathode of the second diode through a first connection point, and the first connection point is configured to output the current detection signal.
Kato teaches (Figure 1) wherein the combiner circuit (R3 and D2-D3) comprises a first diode and a second diode (D2-D3), an anode of the first diode is connected to the first sampling circuit (36), an anode of the second diode is connected to the second sampling circuit (34), a cathode of the first diode is connected to a cathode of the second diode through a first connection point (38), and the first connection point is configured to output the current detection signal. (For Example: Par. 63-71)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include wherein the combiner circuit comprises a first diode and a second diode, an anode of the first diode is connected to the first sampling circuit, an anode of the second diode is connected to the second sampling circuit, a cathode of the first diode is connected to a cathode of the second diode through a first connection point, and the first connection point is configured to output the current detection signal, as taught by Tietema to improve the response time of the detection circuitry.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan in view of You Cn109067176.
Regarding Claims 14, Zhan teaches (Figures 2-5) the circuit.
Zhan does not teach wherein the buck-boost circuit comprises a plurality of first bridge arms, a plurality of second bridge arms, and a plurality of inductors; and the plurality of first bridge arms are connected in parallel, the plurality of second bridge arms are connected in parallel, the plurality of inductors are connected to the plurality of first bridge arms and the plurality of second bridge arms in a one-to-one correspondence, one end of each inductor is connected to a first bridge arm corresponding to each inductor, and the other end of each inductor is connected to a second bridge arm corresponding to each inductor.
You teaches (Figure 2) wherein the buck-boost circuit (Fig. 2) comprises a plurality of first bridge arms (S11-D12), a plurality of second bridge arms (D21-S22), and a plurality of inductors (L1-L2); and the plurality of first bridge arms are connected in parallel (Fig. 2), the plurality of second bridge arms are connected in parallel (Fig. 2), the plurality of inductors are connected to the plurality of first bridge arms and the plurality of second bridge arms in a one-to-one correspondence, one end of each inductor (L1 and L2) is connected to a first bridge arm corresponding to each inductor, and the other end of each inductor is connected to a second bridge arm corresponding to each inductor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Zhan to include wherein the buck-boost circuit comprises a plurality of first bridge arms, a plurality of second bridge arms, and a plurality of inductors; and the plurality of first bridge arms are connected in parallel, the plurality of second bridge arms are connected in parallel, the plurality of inductors are connected to the plurality of first bridge arms and the plurality of second bridge arms in a one-to-one correspondence, one end of each inductor is connected to a first bridge arm corresponding to each inductor, and the other end of each inductor is connected to a second bridge arm corresponding to each inductor, as taught by You for maximum inductor current flow equalization control.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 12; prior art of record fails to disclose either by itself or in combination: “… wherein the combiner circuit further comprises a third operational amplifier circuit and a fourth operational amplifier circuit; one input end of the fourth operational amplifier circuit is connected to the second sampling circuit, and is configured to receive the second sampled signal; the other input end of the fourth operational amplifier circuit is connected to the cathode of the second diode, and an output end of the fourth operational amplifier circuit is connected to the anode of the second diode; one input end of the third operational amplifier circuit is connected to the first sampling circuit, and is configured to receive the first sampled signal; and the other input end of the third operational amplifier circuit is connected to the cathode of the first diode, and an output end of the third operational amplifier circuit is connected to the anode of the first diode”.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Response to Arguments
Applicant's arguments filed 07/14/2025 have been fully considered but they are not persuasive.
Applicant argued that “while Zhan is measuring a current outside of the buck-boost circuitry, the claims require measuring a current from first and second resistors coupled within the buck-boost 10 circuitry. As such, the Applicants respectfully submit that the rejection under 35USC§ 102 over Zhan are overcome”. However, Zhan teaches in Col. 5 lines 39-40 mentioned that the current monitored by the system is for monitored current within the buck-boost converter 202. Therefore, the claim limitations are met by the prior art.
Applicant argued that “The Applicant agrees but this is different from what is claimed. The claims require the resistors for detecting current to be coupled within the buck-boost circuitry. As may be seen in FIG. 3 of the present application, the first resistor is coupled between a common node coupling the negative input and the negative node of the input capacitor and the input switching.” First the examiner would like to thank the examiner for agreeing with the interpretation given by the examen. Second the Zhan reference teaches on Col. 5 lines 53-59 and Col. 6 lines 17-22 that the resistors used by the system are within the converter because they are part of the buck-boost converter as they are between the input capacitor of the converter and the output capacitor of the converter.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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