DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 recites the limitation "the look-up table" on line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-10, 12, 15-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al (US 2015/0207518).
Regarding claim 1, Liu et al. discloses a switched capacitor architecture in figure 2A and 2B that teaches: an ADC (104, 202,205) configured to generate a digital signal (implicit) based on a received input voltage (Vin) and a received reference voltage (Vref); capacitor array(C1, C2 inside 108; and a switching network (switches connecting C1, C2 inside 108) configured to switch a capacitor (C1 or C2) of the capacitor array (C1, C2 inside 108) between a first conductor (node 107 forms an electrical conducting connection) connected to a supply voltage source (Vref); The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device (see para. 0011), and a second conductor (node 103 forms an electrical conducting connection) connected to the reference voltage (VREF); wherein the analog-to-digital converter comprises a logic (Switch control logic 205) configured to control the switching network (switches connecting C1, C2 inside 108) to selectively switch between the first conductor and the second conductor based on the generated digital signal ( "The switch control logic 205 may comprise suitable circuitry for controlling the switching of the capacitors in the SC circuit 104 and the compensation circuit 108", (see para. 0026); "The value of cap required in compensation circuit 108 for each switching step depends on the cap network connection, which is known from the digital output of the comparator 202. ", (see para. 0030) "FIG. 2B depicts an example implementation of the circuits of FIG.1A, after a switching. Referring now to FIG. 2B, assuming, as an example for illustration, that the comparator 202 output is 1 for the first bit conversion, then the cap 2C in the SC circuit 104 is switched from Vref to ground. The charge needed to be provided by node 103 thus equals Vref*C/2. The current drawn by the SC circuit 104 is shown as waveform 250. At the same time, the cap Cl in the compensation circuit 108 may be switched as follows: the top plate is switched from node 107 to node 103 and bottom plate is switched from ground to node 107 (see para. 0028). (See figures 2A and 2B and their descriptions).
Regarding claim 2, Liu further teaches: wherein the circuit further comprises a digital-to-analog converter (104), connected to the second conductor (103), and configured to generate an output voltage based on a voltage at the second conductor (103) and an output of the logic 205) (see fig. 2A, 2B and descriptions).
Regarding claim 3, Liu further teaches: a comparator (202), configured to output to the logic (205) a comparison voltage based on a comparison of a sample of the input voltage with the output voltage of the digital-to-analog converter (104) (see figures 2A, 2B and descriptions).
Regarding claim 4, Liu further teaches: wherein the logic (205) is configured to control the switching network (107) to selectively switch between the first conductor and the second conductor based on the comparison voltage (202) (see figures 2A, 2B and descriptions).
Regarding claim 7, Liu further teaches: wherein the logic (205) further comprises a hardware logic, and wherein the hardware logic is configured to generate an output to control the switching network based on the comparison voltage (see figures 2A, 2B and descriptions).
Regarding claim 8, Liu further teaches: wherein the logic (205) is configured to control the switching network to change a voltage at the second conductor based on the comparison voltage (see figures 2A, 2B and descriptions).
Regarding claim 9, Liu further teaches: wherein the capacitor array comprises a plurality of capacitors, and wherein the plurality of capacitors is connected in parallel (see figures 2A, 2B and descriptions).
Regarding claim 10, Liu further teaches: wherein the circuit is configured as a successive approximation converter (see figures 2A, 2B and descriptions).
Regarding claim 15, Liu further teaches: wherein the analog-to-digital converter is connected to an input voltage source and a reference voltage source (see figures 2A, 2B and descriptions).
Regarding claim 16, Liu further teaches: wherein the analog-to-digital converter is configured to convert each analog voltage of a plurality of analog voltages to bit signal (see figures 2A, 2B and descriptions).
Regarding claim 18, claim 18 is similar to claim 1. Therefore, claim 18 is rejected as well as rejected in claim 1, such as: Liu et al. discloses a switched capacitor architecture in figure 2A and 2B that teaches: an ADC (104, 202,205) configured to generate a digital signal (implicit) based on a received input voltage (Vin) and a received reference voltage (Vref); capacitor array(C1, C2 inside 108; and a switching network (switches connecting C1, C2 inside 108) configured to switch a capacitor (C1 or C2) of the capacitor array (C1, C2 inside 108) between a first conductor (node 107 forms an electrical conducting connection) connected to a supply voltage source (Vref); The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device (see para. 0011), and a second conductor (node 103 forms an electrical conducting connection) connected to the reference voltage (VREF); wherein the analog-to-digital converter comprises a logic (Switch control logic 205) configured to control the switching network (switches connecting C1, C2 inside 108) to selectively switch between the first conductor and the second conductor based on the generated digital signal ( "The switch control logic 205 may comprise suitable circuitry for controlling the switching of the capacitors in the SC circuit 104 and the compensation circuit 108", (see para. 0026); "The value of cap required in compensation circuit 108 for each switching step depends on the cap network connection, which is known from the digital output of the comparator 202. ", (see para. 0030) "FIG. 2B depicts an example implementation of the circuits of FIG.1A, after a switching. Referring now to FIG. 2B, assuming, as an example for illustration, that the comparator 202 output is 1 for the first bit conversion, then the cap 2C in the SC circuit 104 is switched from Vref to ground. The charge needed to be provided by node 103 thus equals Vref*C/2. The current drawn by the SC circuit 104 is shown as waveform 250. At the same time, the cap Cl in the compensation circuit 108 may be switched as follows: the top plate is switched from node 107 to node 103 and bottom plate is switched from ground to node 107 (see para. 0028). (See figures 2A and 2B and their descriptions).
Regarding claim 19, Liu further teaches: generating an output voltage based on a voltage at the second conductor and an output of the logic (see figures 2A, 2B and descriptions).
Regarding claim 20, Liu further teaches: outputting to the logic a comparison voltage based on a comparison of a sample of the input voltage with the output voltage (see figures 2A, 2B and descriptions).
Claims 1-4, 6-10, 12, 15-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al (USP 9,935,643).
Regarding claim 1, Chang et al. discloses an ADC architecture in figure 2 (in combination with figures 3, 4 and 5) that teaches: an analog-to-digital converter (204, 212, 208 Fig.2) configured to generate a digital signal ("The SAR circuit 208 outputs an estimated digital output 224 ", column 3, lines 58-59) based on received input voltage (Vin, Fig.2) and a received reference voltage (Vref, Fig. 2); capacitor array (304 Fig.3; 504 Fig.SA shown in more detail in Fig. 5B; 556 fig.5C); and a switching network (316, 324, 320, 328, Fig.3; 516, 524, 520, 528, Fig.5A Fig.5C) configured to switched capacitor (304, Fig.3, 504, Fig.5A, 556 fig. 5c) of the capacitor array between a first conductor (332, Fig. 3; 532 Fig. 5A) connected to a supply voltage source (VDD,Fig.3, Fig.SA, Fig.5C),and a second conductor (connection between Vref capacitor and DAC 512,Fig.3, Fig. 5A) connected to the reference voltage (Vref Fig. 3, Fig. 5A) ; wherein the analog-to-digital converter comprises a logic (SAR circuit 208, Fig. 2) configured to control the switching network to selectively switch between the first conductor and the second conductor based on the generated digital signal ( "The first, second, third, and fourth switches 516, 520, 524, and 528 are responsive to inputs 540 indicative of various operating phases of the DAC 512. For example, the DAC 512 has a conversion phase, a tracking phase, etc. Accordingly, the inputs 540 correspond to digitized outputs of the DAC 512 indicative of the operating phase, which bits of a digital code are being converted, etc., in an embodiment.", column 6, lines 15-21; "Referring again to FIG. 5A, in a charging phase (e.g., a tracking phase or other phase of the DAC 512 where conversion is not being performed), the adaptive charging capacitor 504 is connected to the supply voltage 532 to be charged. The supply voltage 532 is greater than the reference voltage Vref. In the charging phase, each of the capacitors 556 is connected to the supply voltage 532. For example, the switches 524 and 528 and all of the switches 560 are closed while the switches 516 and 520 are opened. In a conversion phase (e.g., when the DAC 512 is drawing a relatively high level of current), the switches 524 and 528 are opened, and the DAC 512 output is being digitized to approximate the ADC input. Before the conversion ends, a portion of the digital outputs are provided as the input 544, which controls the adaptive charging module 564 to choose one (or none) of the 15 capacitors 556 by closing a respective one of the switches 560 while opening remaining ones of the switches 560. Then, the switch control module 548 closes switches 516 and 520, allowing the charges of the selected ones of the capacitors 556 to be shared with the decoupling capacitor 508. In an embodiment, there are 15 individual ones of the capacitors 556 in the adaptive charging capacitor 504, and for each conversion, only one of the capacitors 556 is connected to the decoupling capacitor 508. In other embodiments, multiple ones of the capacitors 556 are selected together to form an equivalent capacitor that provides a desired capacitance.", column 7, lines 4-30; clearly indicating that depending on the digital output, the switches of the respective capacitors are connected to VDD, VREF, ground) (see figures 2-5 and their descriptions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. as applied to claim 1 above, and further in view of Kolm et al. (US 2016/0308544).
Regarding claim 6, Liu fails to teach or suggest a memory to store a look-up table.
While, Kolm discloses an ADC architecture that teach a ADC comprise a memory which is configure to store a look-up table (see para. 0073).
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to include a memory to store a look-up table to satisfy the design needs.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. as applied to claim 1 above, and further in view of Craninckx et al. (US 2022/0271765).
Regarding claim 12, Liu fails to teach or suggest a sample and hold circuit to sample input voltage.
While, Craninckx discloses an ADC architecture that teach an ADC comprise a sample and hold stage (same as circuit) which is configure to sample input signal (same as voltage) (see para. 0008).
Therefore, it would be obvious to an ordinary skill in the art at the time of effective filing of the invention to include a sample and hold circuit to sample the input signal to satisfy the design needs.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest, objected features, which is: wherein the logic is configured to generate an output to control the switching network based on the comparison voltage and a look-up table.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest, objected features, which is: a reference voltage source configured to provide the reference voltage, wherein the reference voltage source comprises a low-dropout regulator.
Claims 13 and 14 are objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest, objected features, which is: wherein each capacitor of the capacitor array comprises a first terminal having a first polarity and a second terminal having a second polarity, opposite the first polarity; wherein the switching network is a first switching network, and wherein the first switching network is configured to selectively switch the first terminal of each capacitor of the capacitor array between the first conductor and the second conductor.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of record, considered individually or in combination, fails to fairly teach or suggest, objected features, which is: wherein the analog-to-digital converter is configured to decrease nonlinear memory effect introduced by the each reference voltage drop caused by each converted analog signal.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters. Reference USP 9,935, 643 does teach all the limitations as claimed in claims 2-4, 6-10, 12, 15-16 and 18-20 as well.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845
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