DETAILED ACTION
Response to Amendment
Amendment filed on 14 May2026 has been entered. Claims 1-20 are now pending in the application.
Amendments to the claims 8-9 to overcome the rejections under U.S.C 112(b) have been fully considered and the rejection under 35 U.S.C. 112(b) of claims 8-9 has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 14 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Michiwaki (US 20040112632).
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Annotated Fig. 6 Michiwaki.
Regarding claim 1, Michiwaki teaches, a method of making a printed circuit board (multilayer circuit board, Fig. 6, para. [0073-0074]), the method comprising:
forming a plurality of layers (see Figs. 2 to 7, multilayer board 1 which have the wiring patterns 1b, para. [0073]);
forming a stack including the plurality of layers such that topmost and bottommost layers of the stack are copper layers (copper foil sheets 7, see annotated Fig. 6) and such that inner layers of the stack include resin layers (multilayer board 1 may have an arbitrary number of layers, see Fig. 6, para. [0062-0063]) and further copper layers (see the wiring patterns 1b, Figs. 2 to 7);
thermocompressing the stack to form a panel such that the resin layers conform to the further copper layers and such that both the topmost and bottommost layers bend around a perimeter of the inner layers (see annotated Fig. 6, resin sheets 5a and 5b with the copper foil sheets 7 are pressed inward by a vacuum laminator…while being heated…the resin sheets 5a and 5b are bonded together in the opening 3 by a thermo compression bonding procedure, para. [0074]); and
separating a printed circuit board from the panel (see Fig. 1) such that the printed circuit board's widest extent defines its final width.
From the teaching of Michiwaki in para. [0073-0074], forming opening 3 on a laminated multilayer circuit board and then resin sheets 5a and 5b with the copper foil sheets 7 are pressed inward by a vacuum laminator, one of ordinary skill in the art would have thought that pressing the resin sheets 5a and 5b with the copper foil sheets 7 on a stack of copper layers and resin layers before curing the resin layers would bend the copper sheets 7 around the inner layers, that improves the method by reducing and/or eliminating the opening 3 formation step. Therefore, in view of the teachings of Michiwaki, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making of a printed circuit board of Michiwaki and thermocompress the multilayer stack as Michiwaki disclosed in para. [0074] before curing the resin layers that bends the topmost and bottommost layers around the perimeter of the inner layers. Doing so would enable making the printed circuit board with reduced process steps. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in thermocompressing the stack, or bending the topmost and bottommost copper layers. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Regarding claim 2, Michiwaki teaches the recited limitations with respect to claim 1. Michiwaki further teaches, the method of claim 1, further comprising: plating the bend in the topmost and bottommost layers prior to separating the printed circuit board from the panel (intermediate-product body is subjected to chemical copper plating and copper electroplating, para. [0072]).
Regarding claim 3, Michiwaki teaches the recited limitations with respect to claim 1. Michiwaki further teaches, the method of claim 1, wherein forming the plurality of layers includes etching the further copper layers (see the copper layers 1a, 1b, Figs. 2 to 7).
Regarding claim 5, Michiwaki teaches the recited limitations with respect to claim 1. Michiwaki further teaches, the method of claim 1, wherein forming the stack includes arranging an equal number of layers above and below a center layer of the stack such that the center layer of the stack is a resin layer (see the center layer in annotated Fig. 6 below).
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Annotated Fig. 6 Michiwaki.
Regarding claim 6, Michiwaki teaches the recited limitations with respect to claim 1. Michiwaki further teaches, the method of claim 5, wherein the center layer of the stack has a width that is equal to the final width (intermediate-product body is cut into a prescribed shape 50A by machining so that a flexible rigid printed wiring board 50 is completed, see Fig. 1 and 2, unless otherwise defined a width, Michiwaki reads the limitation).
Claim(s) 10-19 are rejected under 35 U.S.C. 103 as being unpatentable over Michiwaki as applied to claim 1 above, and further in view of Ueda (US 20090032285).
Regarding claims 10-13, Michiwaki does not teach the recited limitations. However, Ueda teaches, a method of making a printed circuit board in Fig. 2, including arranging a plurality of layers 10a to 10d, and 50a to 50c, such that inner layers of the stack are arranged between outer copper layers 40a and 40b, and such that inner layers include resin layers, in which,
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Annotated Fig. 2a, Ueda.
10. The method of claim 1, wherein: the resin layers include substrates (double-sided circuit boards 50a, 50b and 50c, Fig. 2a) and pre-preg layers (prepregs 10a to 10d), and arranging the plurality of layers includes alternating the substrates and the pre-preg layers (see Fig. 2a Ueda).
11. The method of claim 10, wherein: the substrates are coated on opposite sides by the further copper layers such that alternating the substrates (50b and 50c, Fig. 2a) and the pre-preg layers (prepregs 10a to 10d) includes arranging the pre-preg layers in direct contact with the further copper layers (see Fig. 2a).
12. The method of claim 11, wherein thermocompressing the stack includes forcing the pre-preg layers to flow into gaps in the further copper layers (heat and pressure are applied from above the metallic foil 4a on a top surface with a heated heater chip or the like…to melt resin components of the prepregs 1a, 1b and 1c, which adhere to the double-sided circuit boards 5a and 5b and the metallic foils 4a and 4b due to hardening of the resin components thereafter, para. [0009]).
13. The method of claim 12, wherein thermocompressing the stack further includes curing the pre-preg layers such that the cured pre-preg layers are indistinguishable from the substrates (heating and pressurizing arbitrary areas thereof and melting and then hardening a resin included in the multiple prepreg sheets so as to mutually bond them, para. [0066]).
Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Michiwaki and to include substrate layers 50a, 50b and 50c and prepreg layers 10a, 10b and 10c as taught by Ueda in Fig. 2a so that it enables forming a printed circuit board having thinner layers by melting and hardening the prepreg resin during the heating and pressing of the circuit board stack.
Regarding claim 14, Michiwaki teaches, a method of making a printed circuit board (multilayer circuit board, Fig. 6, para. [0073-0074]), the method comprising:
arranging a plurality of layers to form a stack (see Figs. 3 to 7) such that inner layers of the stack are arranged between outer copper layers (copper foil sheets 7, see annotated Fig. 6) and include copper coated substrates (multilayer board 1 includes an FR-4 board having first and second copper-clad surfaces, para. [0062]);
thermocompressing the stack in the copper coatings and such that both of the outer copper layers bend around a perimeter of the inner layers (see annotated Fig. 6, Michiwaki, resin sheets 5a and 5b with the copper foil sheets 7 are pressed inward by a vacuum laminator…while being heated…the resin sheets 5a and 5b are bonded together in the opening 3 by a thermo compression bonding procedure, para. [0074], copper foil sheets 7 prevent the material for the resin sheets 5a and 5b from considerably dropping in viscosity and undesirably flowing due to a temperature rise, para. [0092]); and
separating a printed circuit board from the thermocompressed stack (see Figs. 1 and 2).
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Annotated Fig. 2a, Ueda.
Michiwaki does not explicitly teach, a pre-preg layer. However, Ueda teaches a method of making a printed circuit board in Fig. 2, including arranging a plurality of layers 10a to 10d, and 50a to 50c, such that inner layers of the stack are arranged between outer copper layers 40a and 40b, and include copper coated substrates (double-sided circuit boards 50a, 50b and 50c, Fig. 2a) alternated with pre-preg layers (prepreg layers 10a to 10d, see annotated Fig. 2a, para. [0106]) and thermocompressing the stack (a thermocompression bonding process of thermocompression-bonding the first resin layer and the second resin layer to each other and curving the first signal conductor layer in the up-down direction, para. [0007]). Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Michiwaki and to replace the resin layer of Michiwaki with a prepreg layer 10c as taught by Ueda in Fig. 2a so that it enables forming a thinner circuit board by melting and hardening the prepreg resin during the heating and pressing of the circuit board stack.
Regarding claim 15, Michiwaki in view of Ueda teaches the recited limitations with respect to claim 14. Michiwaki further teaches, the method of claim 14, further comprising: plating the bent outer copper layers prior to separating the printed circuit board from the thermocompressed stack (intermediate-product body is subjected to chemical copper plating and copper electroplating, para. [0072]).
Regarding claims 16 and 17, Michiwaki in view of Ueda teaches the recited limitations with respect to claim 15. Ueda further teaches,
16. The method of claim 15, wherein: the substrates and the pre-preg layers are resin layers comprising a polymeric matrix material and a fibrous material (a filler-added epoxy resin, …referred to as a prepreg, para. [0101], double-sided circuit boards 50a, 50b and 50c used as cores were manufactured by sandwiching both the surfaces of the prepregs 10 with the metallic foils 40, para. [0117]), and arranging the plurality of layers includes arranging an equal number of layers above and below a center layer (circuit board 50b, Fig. 2a) of the stack such that the center layer of the stack is a resin layer (see Fig. 2a, double-sided circuit boards 50a, 50b and 50c…sandwiching both the surfaces of the prepregs 10 with the metallic foils 40 and applying heat and pressure on both the top and under surfaces thereof, para. [0117]).
17. The method of claim 16, wherein thermocompressing the stack cures the polymeric matrix material of the pre-preg layers (cores were manufactured by sandwiching both the surfaces of the prepregs 10 with the metallic foils 40 and applying heat and pressure on both the top and under surfaces thereof, para. [0117]).
Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Michiwaki and to replace the resin layer of Michiwaki with a prepreg layer 10c as taught by Ueda in Fig. 2a so that it enables forming a printed circuit board stack using conventional fabrication methods.
Regarding claim 18, Michiwaki teaches, a method of making a printed circuit board (multilayer circuit board, Fig. 6, para. [0073-0074]), the method comprising:
forming a plurality of laminated cores (see Figs. 2 to 7, multilayer board 1 which have the wiring patterns 1b, para. [0073]) including etching copper layers laminated on substrates (see the copper layers 1a);
forming a stack (see Figs. 3 to 7) such that topmost and bottommost layers of the stack are further copper layers (see copper foil sheets 7, annotated Fig. 6 above);
thermocompressing the stack such that the layers conform to form a panel and such that the topmost and bottommost layers bend toward each other and around a perimeter of the panel (see annotated Fig.6, Michiwaki, resin sheets 5a and 5b with the copper foil sheets 7 are pressed inward by a vacuum laminator…while being heated…the resin sheets 5a and 5b are bonded together in the opening 3 by a thermo compression bonding procedure, para. [0074], copper foil sheets 7 prevent the material for the resin sheets 5a and 5b from considerably dropping in viscosity and undesirably flowing due to a temperature rise, para. [0092]); and
separating a printed circuit board from the panel such that the printed circuit board's widest extent defines its final width (see Fig. 1).
Michiwaki does not explicitly teach, a pre-preg layer or the pre-preg layer alternated with the laminated core. However, Ueda teaches a method of making a printed circuit board in Fig. 2, including arranging a plurality of layers 10a to 10d, and 50a to 50c, such that inner layers of the stack are arranged between outer copper layers 40a and 40b, and include copper coated substrates (double-sided circuit boards 50a, 50b and 50c, Fig. 2a) alternated with pre-preg layers (prepreg layers 10a to 10d, see annotated Fig. 2a, para. [0106]) and thermocompressing the stack. Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Michiwaki and to replace the resin layer of Michiwaki with a prepreg layer 10c as taught by Ueda in Fig. 2a so that it enables forming a thinner circuit board by melting and hardening the prepreg resin during the heating and pressing of the circuit board stack.
Regarding claim 19, Michiwaki in view of Ueda teaches the recited limitations with respect to claim 14. Michiwaki further teaches, the method of claim 18, further comprising: plating the perimeter of the panel prior to separating the printed circuit board from the panel (intermediate-product body is subjected to chemical copper plating and copper electroplating, para. [0072]).
Allowable Subject Matter
Claims 4, 7 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8-9 would be allowable by virtue of its dependency.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
Claims 4 and 20 would be allowable for disclosing a method of making a printed circuit board, wherein etching the further copper layers includes removing copper from a substrate such that a leading edge of remaining copper extends 15 mils farther than half of the final width.
Claim 7 would be allowable for disclosing a method of making a printed circuit board, wherein: forming the plurality of layers includes reducing a first width of first resin layers relative to the final width by a step back distance, and the first resin layers are adjacent to the center layer of the stack.
Though, prior art of record Michiwaki teaches etching the further copper layers includes removing copper from a substrate, Michiwaki fails to teach removing copper from a substrate such that a leading edge of remaining copper extends 15 mils farther than half of the final width; or forming the plurality of layers includes reducing a first width of first resin layers relative to the final width by a step back distance, and the first resin layers are adjacent to the center layer of the stack.
Though, prior art of record Ueda teaches forming the circuit patterns 30 from the copper foils 40 on both sides by etching, Ueda does not teach removing copper from a substrate such that a leading edge of remaining copper extends 15 mils farther than half of the final width; or forming the plurality of layers includes reducing a first width of first resin layers relative to the final width by a step back distance, and the first resin layers are adjacent to the center layer of the stack.
Therefore, claims 4, 7 and 20 would be allowable. Claims 8-9 would be allowable by virtue of its dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729
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