DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 31 May 2023 was filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 8, the limitation “the second resin layers are adjacent to the first resin layers and exclude the center layer” renders claim indefinite because, claim 5 upon which claim 8 depends, recites “the stack includes arranging an equal number of layers above and below a center layer”. Claim 5 deemed to read as the printed circuit board stack includes a central layer. If so, it is unclear what does “exclude the center layer” mean as recited in claim 8.
Claim 9 depends on claim 8. Therefore, claims 8-9 are rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishio (WO 2022080067, see US 20230239996 for English Translation).
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Annotated Fig. 17, Nishio.
Regarding claim 1, Nishio teaches, a method of making a printed circuit board (circuit board 10, Fig. 1, see annotated Fig. 17, para. [0124]), the method comprising:
forming a plurality of layers (layers 20, 16a, 18a, 16b, 22, 18b, Fig. 17);
forming a stack (circuit board main body 12, Fig. 17) including the plurality of layers such that topmost (first ground conductor layer 20, Fig. 7, first ground conductor layer 20, and the second ground conductor layer 22, …a metal foil made of copper, para. [0057]) and bottommost layers (second signal conductor layer 18b, see annotated Fig. 17, para. [0070]) of the stack are copper layers (see para. [0057, 0070]) and such that inner layers of the stack include resin layers (resin layer 16a, resin layer 16b, para. [0069]) and further copper layers (conductor layer 18a, conductor layer 22, Fig 17, the resin layer 16b whose upper main surface and lower main surface are bonded with metal foils made of copper, para. [0070]);
thermocompressing the stack (a thermocompression bonding process of thermocompression-bonding the first resin layer and the second resin layer to each other and curving the first signal conductor layer in the up-down direction, para. [0007]) to form a panel such that the resin layers conform to the further copper layers and such that the copper layers bend around a perimeter of the inner layers (a first curved portion Ca in which the first signal conductor layer 18a is curved in the up-down direction,…the resin layer 16b is curved in the up-down direction, a second curved portion Cb, para. [0051-0052]; second signal conductor layer 18b includes a curved portion Cf in which the second signal conductor layer 18b is curved in the up-down direction, para. [0128], see curved portions Cc to Cf in Fig. 17); and
separating a printed circuit board from the panel such that the printed circuit board’s widest extent defines its final width (large-sized mother resin layers are laminated and subjected to thermocompression bonding to form a mother circuit board, and the mother circuit board is cut into a plurality of circuit boards 10, para. [0068]).
Note: the recited limitation “the printed circuit board’s widest extent defines its final width” does not add any structure, function or contribute any patentable weight compared to prior art Nishio.
Regarding claim 3, Nishio teaches the recited limitations with respect to claim 1. Nishio further teaches, the method of claim 1, wherein forming the plurality of layers includes etching the further copper layers (second ground conductor layer 22 are formed on the upper main surface and the lower main surface of the resin layer 16a, respectively, by performing etching on the two metal foils by using a mask, para. [0069-0070]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nishio as applied to claim 1 above, and further in view of Mikado (US 20080289859).
Regarding claim 2, Nishio does not teach plating the perimeter of the panel. However, Mikado teaches, a method of making a printed circuit board in Figs 6 to 8 including forming a plurality of layers in Fig. 7; and in para. [0041], forming a stack including the plurality of layers such that topmost and bottommost layers of the stack are copper layers and such that inner layers of the stack include resin layers and further copper layers, in which,
method of claim 1, further comprising: plating the perimeter of the panel (see Fig. 8, the wiring patterns are formed by plating, para. [0099]) prior to separating the printed circuit board from the panel. Therefore, in view of the teachings of Mikado, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Nishio and to include plating the perimeter of the panel as taught by Mikado in Fig. 8 so that it enables manufacturing a bendable circuit board panel using conventional printed circuit board manufacturing methods.
Claim(s) 5-6, 10-14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nishio as applied to claim 1 above, and further in view of Ueda (US 20090032285).
Regarding claim 5, Nishio does not teach, arranging an equal number of layers above and below a center layer. However, Ueda teaches, a method of making a printed circuit board in Fig. 2, including arranging a plurality of layers 10a to 10d, and 50a to 50c, such that inner layers of the stack are arranged between outer copper layers 40a and 40b, and such that inner layers include resin layers, in which,
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Annotated Fig. 2a, Ueda.
the method of claim 1, wherein forming the stack includes arranging an equal number of layers above and below a center layer (circuit board 50b, see annotated Fig. 2a above) of the stack such that the center layer of the stack is a resin layer (see Fig. 2a, double-sided circuit boards 50a, 50b and 50c…sandwiching both the surfaces of the prepregs 10 with the metallic foils 40 and applying heat and pressure on both the top and under surfaces thereof, para. [0117], in which prepreg layer comprises resin. If applicant disagrees, see claim 16 of the application). Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Nishio and to replace the resin layer 16a of Nishio with a circuit board layer 50b as taught by Ueda in Fig. 2a so that it enables forming a thinner circuit board by melting and hardening the prepreg resin during the heating and pressing of a circuit board stack.
Regarding claim 6, Nishio in view of Ueda teaches the recited limitations with respect to claim 5. Nishio further teaches, the method of claim 5, wherein the center layer of the stack has a width that is equal to the final width (the mother circuit board is cut into a plurality of circuit boards 10, para. [0068], unless otherwise defined, selection of final width determines at cutting the mother circuit board).
Regarding claims 10-13, Nishio does not teach the recited limitations. However, Ueda further teaches,
10. The method of claim 1, wherein: the resin layers include substrates (double-sided circuit boards 50a, 50b and 50c, Fig. 2a) and pre-preg layers (prepregs 10a to 10d), and arranging the plurality of layers includes alternating the substrates and the pre-preg layers (see Fig. 2a below).
11. The method of claim 10, wherein: the substrates are coated on opposite sides by the further copper layers such that alternating the substrates (50b and 50c, Fig. 2a) and the pre-preg layers (prepregs 10a to 10d) includes arranging the pre-preg layers in direct contact with the further copper layers (see Fig. 2a).
12. The method of claim 11, wherein thermocompressing the stack includes forcing the pre-preg layers to flow into gaps in the further copper layers (heat and pressure are applied from above the metallic foil 4a on a top surface with a heated heater chip or the like…to melt resin components of the prepregs 1a, 1b and 1c, which adhere to the double-sided circuit boards 5a and 5b and the metallic foils 4a and 4b due to hardening of the resin components thereafter, para. [0009]).
13. The method of claim 12, wherein thermocompressing the stack further includes curing the pre-preg layers such that the cured pre-preg layers are indistinguishable from the substrates (heating and pressurizing arbitrary areas thereof and melting and then hardening a resin included in the multiple prepreg sheets so as to mutually bond them, para. [0066]).
Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Nishio and to include substrate layers 50a, 50b and 50c and prepreg layers 10a, 10b and 10c as taught by Ueda in Fig. 2a so that it enables forming a printed circuit board having thinner layers by melting and hardening the prepreg resin during the heating and pressing of the circuit board stack.
Regarding claim 14, Nishio teaches, a method of making a printed circuit board (circuit board 10, Fig. 1, see annotated Fig. 17, para. [0124]), the method comprising:
arranging a plurality of layers (layers 20, 16a, 18a, 16b, 22, 18b, Fig. 17) to form a stack (circuit board main body 12, Fig. 17) such that inner layers of the stack are arranged between outer copper layers (first ground conductor layer 20, second signal conductor layer 18b, see annotated Fig. 17, first ground conductor layer 20, and the second ground conductor layer 22, …a metal foil made of copper, para. [0057);
thermocompressing the stack (a thermocompression bonding process of thermocompression-bonding the first resin layer and the second resin layer to each other and curving the first signal conductor layer in the up-down direction, para. [0007]) such that the layers are forced into gaps in the copper coatings and such that the outer copper layers bend around a perimeter of the inner layers (a first curved portion Ca in which the first signal conductor layer 18a is curved in the up-down direction,…the resin layer 16b is curved in the up-down direction, a second curved portion Cb, para. [0051-0052]; second signal conductor layer 18b includes a curved portion Cf in which the second signal conductor layer 18b is curved in the up-down direction, para. [0128], see curved portions Cc to Cf in Fig. 17); and
separating a printed circuit board from the thermocompressed stack (large-sized mother resin layers are laminated and subjected to thermocompression bonding to form a mother circuit board, and the mother circuit board is cut into a plurality of circuit boards 10, para. [0068]).
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Annotated Fig. 2a, Ueda.
Nishio does not explicitly teach a pre-preg layer. However, Ueda teaches a method of making a printed circuit board in Fig. 2, including arranging a plurality of layers 10a to 10d, and 50a to 50c, such that inner layers of the stack are arranged between outer copper layers 40a and 40b, and include copper coated substrates (double-sided circuit boards 50a, 50b and 50c, Fig. 2a) alternated with pre-preg layers (prepreg layers 10a to 10d, see annotated Fig. 2a, para. [0106]) and thermocompressing the stack (a thermocompression bonding process of thermocompression-bonding the first resin layer and the second resin layer to each other and curving the first signal conductor layer in the up-down direction, para. [0007]).
Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Nishio and to replace the resin layer 16a of Nishio with a prepreg layer 10c as taught by Ueda in Fig. 2a so that it enables forming a thinner circuit board by melting and hardening the prepreg resin during the heating and pressing of the circuit board stack.
Regarding claim 18, Nishio teaches, a method of making a printed circuit board (circuit board 10, Fig. 1, see annotated Fig. 17, para. [0124]), the method comprising:
forming a plurality of laminated cores (double-sided circuit boards 50a, 50b and 50c, Fig. 1a) including etching copper layers laminated on substrates (circuit patterns 30 of the double-sided circuit boards 50a, 50b and 50c, para. [0107]);
forming a stack (see Fig. 1a) such that topmost and bottommost layers of the stack are further copper layers (copper layers 40a and 40b) and such that inner layers of the stack include layers alternated with the laminated cores (plurality of layers 10a to 10d, and 50a to 50c);
thermocompressing the stack (a thermocompression bonding process of thermocompression-bonding the first resin layer and the second resin layer to each other and curving the first signal conductor layer in the up-down direction, para. [0007]) such that the layers conform to the etched copper layers to form a panel and such that the further copper layers bend around a perimeter of the panel (a first curved portion Ca in which the first signal conductor layer 18a is curved in the up-down direction,…the resin layer 16b is curved in the up-down direction, a second curved portion Cb, para. [0051-0052]; second signal conductor layer 18b includes a curved portion Cf in which the second signal conductor layer 18b is curved in the up-down direction, para. [0128], see curved portions Cc to Cf in Fig. 17); and
separating a printed circuit board from the panel such that the printed circuit board’s widest extent defines its final width (large-sized mother resin layers are laminated and subjected to thermocompression bonding to form a mother circuit board, and the mother circuit board is cut into a plurality of circuit boards 10, para. [0068]).
Nishio does not explicitly teach a pre-preg layer or the pre-preg layer alternated with the laminated core. However, Ueda teaches a method of making a printed circuit board in Fig. 2, including arranging a plurality of layers 10a to 10d, and 50a to 50c, such that inner layers of the stack are arranged between outer copper layers 40a and 40b, and include copper coated substrates (double-sided circuit boards 50a, 50b and 50c, Fig. 2a) alternated with pre-preg layers (prepreg layers 10a to 10d, see annotated Fig. 2a, para. [0106]) and thermocompressing the stack. Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Nishio and to replace the resin layer 16a of Nishio with a prepreg layer 10c as taught by Ueda in Fig. 2a so that it enables forming a thinner circuit board by melting and hardening the prepreg resin during the heating and pressing of the circuit board stack.
Claim(s) 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nishio in view of Ueda and further in view of Mikado.
Regarding claims 15 and 19, modified Nishio does not teach plating the perimeter of the panel. However, Mikado further teaches,
15. The method of claim 14, further comprising: plating (see Fig. 8, the wiring patterns are formed by plating, para. [0099]) the bent outer copper layers prior to separating the printed circuit board from the thermocompressed stack.
19. The method of claim 18, further comprising: plating (see Fig. 8, the wiring patterns are formed by plating, para. [0099]) the perimeter of the panel prior to separating the printed circuit board from the panel.
Therefore, in view of the teachings of Mikado, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Nishio and to include plating the perimeter of the panel as taught by Mikado in Fig. 8 so that it enables manufacturing a bendable circuit board panel using conventional manufacturing methods.
Regarding claims 16 and 17, Ueda further teaches,
16. The method of claim 15, wherein: the substrates and the pre-preg layers are resin layers comprising a polymeric matrix material and a fibrous material (a filler-added epoxy resin, …referred to as a prepreg, para. [0101], double-sided circuit boards 50a, 50b and 50c used as cores were manufactured by sandwiching both the surfaces of the prepregs 10 with the metallic foils 40, para. [0117]), and arranging the plurality of layers includes arranging an equal number of layers above and below a center layer (circuit board 50b, Fig. 2a) of the stack such that the center layer of the stack is a resin layer (see Fig. 2a, double-sided circuit boards 50a, 50b and 50c…sandwiching both the surfaces of the prepregs 10 with the metallic foils 40 and applying heat and pressure on both the top and under surfaces thereof, para. [0117]).
17. The method of claim 16, wherein thermocompressing the stack cures the polymeric matrix material of the pre-preg layers (cores were manufactured by sandwiching both the surfaces of the prepregs 10 with the metallic foils 40 and applying heat and pressure on both the top and under surfaces thereof, para. [0117]).
Therefore, in view of the teachings of Ueda, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making the printed circuit board of Nishio and to replace the resin layer 16a of Nishio with a prepreg layer 10c as taught by Ueda in Fig. 2a so that it enables forming a printed circuit board stack using conventional fabrication methods.
Allowable Subject Matter
Claims 4, 7 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8-9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
Claims 4 and 20 would be allowable for disclosing a method of making a printed circuit board, wherein etching the further copper layers includes removing copper from a substrate such that a leading edge of remaining copper extends 15 mils farther than half of the final width.
Claim 7 would be allowable for disclosing a method of making a printed circuit board, wherein: forming the plurality of layers includes reducing a first width of first resin layers relative to the final width by a step back distance, and the first resin layers are adjacent to the center layer of the stack.
Though, prior art of record Nishio and Mikado teach etching the further copper layers includes removing copper from a substrate, both Nishio and Mikado fail to teach removing copper from a substrate such that a leading edge of remaining copper extends 15 mils farther than half of the final width; or forming the plurality of layers includes reducing a first width of first resin layers relative to the final width by a step back distance, and the first resin layers are adjacent to the center layer of the stack.
Though, prior art of record Ueda teaches forming the circuit patterns 30 from the copper foils 40 on both sides by etching, Ueda does not teach removing copper from a substrate such that a leading edge of remaining copper extends 15 mils farther than half of the final width; or forming the plurality of layers includes reducing a first width of first resin layers relative to the final width by a step back distance, and the first resin layers are adjacent to the center layer of the stack.
Therefore, claims 4, 7 and 20 would be allowable. Claims 8-9 would be allowable by virtue of its dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Prior art Mizori (US 20220204766) teaches a method of making a printed circuit board including forming a plurality of layers; forming a stack including the plurality of layers such that topmost and bottommost layers of the stack are copper layers and such that inner layers of the stack include resin layers and further copper layers; thermocompressing the stack to form a panel such that the resin layers conform to the further copper layers and such that the copper layers bend around a perimeter of the inner layers.
Prior art Michiwaki (US 20040112632) teaches a method of making a printed circuit board including forming a plurality of layers; forming a stack including the plurality of layers such that topmost and bottommost layers of the stack are copper layers and such that inner layers of the stack include resin layers and further copper layers; thermocompressing the stack such that the copper layers bend around a perimeter of the inner layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729 /THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729