Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/02/2026 has been entered.
Response to Arguments
Applicant’s arguments filed 02/26/2026, with respect to the rejections of independent claims 1, 9, and 17 and their corresponding dependent claims under 35 USC 103 have been fully considered and are persuasive. However, upon further consideration, new grounds of rejection are made in view of the previously applied references from Brusilovsky and Benoit, in addition to a newly applied reference from Mukherjee (US 11604873 B1). Mukherjee teaches the amended limitation “adjusts an instruction cycle for the processing unit to process a first instruction or any one instruction”. Examiner respectfully submits that the combination of Brusilovsky and Benoit is sufficient to teach the remaining claim limitations.
Regarding Applicant’s argument, beginning on P. 7 of Applicant Arguments, that Benoit’s solution fails to solve the issue detected by Benoit, Examiner respectfully disagrees. As highlighted in Applicant Arguments, Brusilovsky teaches an attack indicator that is compared with an expected/stored value during boot up to detect tampering upon value mismatch. Responsive to the tampering detection, Brusilovsky may initiate some defensive action such as enabling a limping mode or shutting down. Benoit adds detection of faults, incrementing a counter in response to the detection(s), and initiating countermeasures when fault thresholds are reached or exceeded. The thresholds represent varying levels of threat detection and the countermeasures include at least adjustment of processor timing. These functional steps naturally combine to achieve similar outcomes to those of the claimed invention. Each disclosure contributes attack detection and responsive action. Therefore, Examiner respectfully submits that Brusilovsky’s techniques to detect some instance of system tampering or compromise and Benoit’s processing adjustments based on detected attack conditions would have been obvious to combine under the KSR rationale. The combined implementation of these known techniques would produce the obvious benefit of a system capable of detecting compromise at boot time and subsequently adjusting system behavior to mitigate the potential damage caused by the compromise.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 9-11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brusilovsky (US 20140184411 A1), hereinafter Brusilovsky in view of Benoit et al. (US 20170286680 A1), hereinafter Benoit, and Mukherjee (US 11604873 B1), hereinafter Mukherjee.
Regarding Claim 1:
Brusilovsky teaches a security processing device for handling attacks (Brusilovsky – Paragraph [0014]: As used herein, the phrase "network element" refers to any computing device associated with a communication network. By way of example only, such computing device may be a router, a switch, a base station, a mobile terminal, etc. Embodiments of the invention are not limited to any particular type of network element; and Paragraph [0030]: In step 206, at a subsequent power up cycle of the network element 100, the network element goes through a secure boot-up validation procedure (secure boot process), during which the stored protected alarm indication data is analyzed for integrity attacks, and possibly for replay and confidentiality attacks if such protection was implemented), comprising: an attack detector, configured to detect whether an attack event occurs (Brusilovsky – Paragraph [0023]: Examples of intrusion sensors 118 include, but are not limited to … electronic intrusion detectors (e.g., software that detects network hacking activities, etc.), and generate an attack trigger signal when an occurrence of the attack event is detected (Brusilovsky – Paragraph [0029]: In step 204, upon triggering of an alarm condition (i.e., an alarm condition is detected by one or more of the set of sensors 116), for example, a case intrusion, the alarm storage and processing unit 12 (possibly now being powered by the backup power source 114 depending on the alarm condition type) receives the alarm indication data from the set of sensors 116); a programming time controller, electrically connected to the attack detector, and configured to update a first flag value when the attack trigger signal is received (Brusilovsky – Paragraph [0029]: This means that the unit 112 receives the Alarm_Status value set to logic "1" indicating an alarm has been detected. The unit 112 then integrity protects the value using secret cryptographic key Ka, as explained above, to generate protected value (Alarm_Status)Ka. Again, the alarm condition indicator value may also be replay protected and/or confidentiality protected before being stored in unit 112. Thus, the unit 112 processes any alarm indication data it receives and stores it in non-volatile memory); a non-volatile memory device, [electrically connected to the programming time controller], and configured to store the first flag value and a second flag value (Brusilovsky – Paragraph [0029]: Thus, the unit 112 processes any alarm indication data it receives and stores it in non-volatile memory; and Paragraph [0031]: For example, the alarm condition indicator value being analyzed is compared against a securely stored (e.g., in TRE 110) reference alarm condition indicator value; and Paragraph [0040]: Also, the term "memory" as used herein is intended to include electronic memory associated with a processor, such as random access memory (RAM), read-only memory (ROM), non-volatile memory (NVM), or other types of memory, in any combination; Examiner’s Comment: Examiner respectfully submits that the teaching of Brusilovsky to store one flag value in a non-volatile memory renders it obvious to one of ordinary skill in the art to store a second/reference value in the non-volatile memory); and a processing unit, electrically connected to the programming time controller, wherein when the security processing device is reset or boot-up, the programming time controller updates the second flag value (Brusilovsky – Paragraph [0030]: In step 206, at a subsequent power up cycle of the network element 100, the network element goes through a secure boot-up validation procedure (secure boot process), during which the stored protected alarm indication data is analyzed for integrity attacks, and possibly for replay and confidentiality attacks if such protection was implemented; and Paragraph [0031]: More specifically, in one embodiment, the secure boot process analyzes an integrity (and possibly replay and/or confidentiality, if instituted) protection status of the Alarm_Status variable. For example, the alarm condition indicator value being analyzed is compared against a securely stored (e.g., in TRE 110) reference alarm condition indicator value. If these two values are the same, upon successful check, then it is assumed that there was no tampering with the data. However, if the values are different, then the network element assumes that the data has been tampered with. Note that if the reference value remains constant, the attacker can substitute (replay) the alarm condition indicator value with the expected (constant) value. To protect against such a replay attack, the expected reference value may be changed at every successful check or reset (e.g., by adding freshness based on time, etc. to the reference value and alarm condition indicator value computations); and Paragraph [0037]: It is to be understood that one or more of the computing devices 302 shown in FIG. 3 represent a network element 100 as described above in the context of FIGS. 1 and 2; and Paragraph [0039]: As shown, computing device 302-1 comprises processor 310, memory 312, and network interface 314) and adjusts [an instruction cycle for the processing unit to process a first instruction or any one instruction] based on the first flag value and the second flag value when the first flag value does not match the second flag value (Brusilovsky – Paragraph [0032]: If any security breach of the alarm indication data due to tampering is evident (integrity or replay/confidentiality protection is compromised, as explained above), the methodology moves from step 206 to step 212. In step 212, the network element 100 decides whether to: (1) enable a limping mode (step 216), wherein the device is allowed minimal functionality, for example, connection to its service center; or (2) if the alarm or security violation is too serious, shut down the network element (step 214)).
Brusilovsky does not expressly teach a non-volatile memory device, electrically connected to the programming time controller; and adjusts an instruction cycle for the processing unit to process a first instruction or any one instruction.
However, Benoit teaches a non-volatile memory device, electrically connected to the programming time controller (Benoit – Figure 8: diagram of a system-on-a-chip (SoC) with connected hardware elements including a NVM (internal shared HW resources 830) and a programming time controller (system clock controller 802)); adjusts [an instruction] cycle for the processing unit to process a first instruction or any one instruction (Benoit – Figure 9: operations in response to an ongoing transient fault attack; Paragraph [0047]: … In some examples, the timing of some processes running on the processor is adaptively adjusted relative to other processes based on faults or perturbations. This is helpful in defending against attacks that rely on the precise timing of injected transient faults, i.e. attacks that rely on time localization. Hardware examples described herein of adaptive adjustments include selectively adjusting the clock of the processor and, in particular, selectively skipping or “gating” clock cycles. By skipping some clock cycles, malicious attacks that rely on the precise timing of injected transient faults become far more difficult since the timing of the operations of the processor is offset due to the skipped clock cycles; Paragraph [0068]: At 910, the adaptive controller 904 also increases an aggressiveness of the transient fault defense and/or adjusts or modifies the system clock … Insofar as adjusting or modifying the system clock, the adaptive controller 904, depending upon its programming, can selectively increase or decrease the clock rate (to thereby affect the time localization of events within the SoC processor to hinder transient fault attacks that rely on time localization) and/or selectively skip or gate clock cycles (to thereby also affect the time localization of events within the SoC processor), including gating clock cycles by generating a random or pseudorandom hash that specifies the particular cycles to skip. The system clock controller 902 responds, at 912, by adjusting or modifying the system clock, as instructed; and Figure 12: processor clock adjustments in response to transient fault attack; and Paragraph [0076]: A default clock 1202 is illustrated, which can be, for example, a 8.5 GHz clock. In response to the detection of a first new transient fault, the clock rate might be slowed to half its rate, as indicated by slowed clock 1204. This can help thwart malicious attacks that rely on the precise timing of injection of transient faults since the processor will then be operating a different rate than the rate that the attacker assumes the processor is using).
Benoit further teaches a processing unit, electrically connected to the programming time controller (Benoit – Figure 8: diagram of a system-on-a-chip (SoC) with connected hardware elements including a processing unit (application processing circuit 810) and a programming time controller (system clock controller 802)).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Brusilovsky, further incorporating Benoit to arrive at the conclusion of the claimed invention. Brusilovsky is directed to a system for detecting tampering when an observed alarm/attack value does not match an expected/stored value. When such tampering is detected, the device enters a limited mode or may shut down to prevent further damage. Benoit is directed to a system for detecting faults and responsively adjusting processor timing to mitigate fault attacks relying on precise timing. Combining these known techniques would result in a system providing the predictable benefits of both the detection means taught by Brusilovsky, and the responsive means taught by Benoit. That is, initiating mitigation efforts including adjusting processor operations in response to detecting system compromise in persistent memory would have been obvious in view of the KSR rationale.
The combination of Brusilovsky and Benoit does not expressly teach adjusts an instruction cycle for the processing unit to process a first instruction or any one instruction.
However, Mukherjee teaches adjusts an instruction cycle for the processing unit to process a first instruction or any one instruction (Mukherjee – Figure 5: ; and Col. 13, Line 46-57: FIG. 5 is a flow chart of an example of a technique 500 for side-channel attack mitigation using random numbers of noisy instructions. The technique 500 includes fetching 510 an instruction from a memory into a processor pipeline of a processor core; generating 520 a random number; fissioning 530 the instruction into a set of micro-operations that includes one or more micro-operations that perform the instruction and the random number of noisy micro-operations; executing 540 the set of micro-operations using one or more execution units of the processor pipeline; and, retiring 550, responsive to completion of execution of the set of micro-operations, the instruction; and Col. 14, Line 24-54: The technique 500 includes generating 520 a random number. For example, the random number may be in integer selected from a range of allowed numbers of noisy micro-operations to be added to the fissioned 530 instruction … The technique 500 includes fissioning 530 the instruction into a set of micro-operations that includes one or more micro-operations that perform the instruction and the random number of noisy micro-operations. Each of the noisy micro-operations does not affect the architectural state (e.g., the architectural state 420). For example, one of the random number of noisy micro-operations may have a zero register (e.g., the zero register 422) of the architectural state as a destination register. For example, one of the random number of noisy micro-operations may be a load micro-operation, which may have the zero register as its destination register. The noisy micro-operations may alter a microarchitectural state (e.g., the microarchitectural state 430). Thus, the noisy micro-operations may impact side-channels without changing the final outputs determined by a process that includes the instruction. By randomly choosing the number of noisy micro-operations to inject during fissioning 530 of the instruction, side-channel signals that might otherwise be exploited in a side-channel attack may be obscured. Examiner’s Comment: Examiner respectfully submits that the described technique in the above citation from Mukherjee is consistent with the description from the instant application describes in parag. [0023], which discloses that adjusting the instruction cycle of the instruction executed by the processing unit 14 may be to make the programing time controller 12 instruct the processing unit 14 to expand the instruction to be processed into several instructions, so as to adjust the time for the processing unit 14 to process the original instruction accordingly).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Brusilovsky and Benoit, further incorporating Mukherjee to arrive at the conclusion of the claimed invention. One would be motivated to incorporate Mukherjee’s techniques for mitigating side-channel attacks by modifying the process of executing at least one instruction into Brusilovsky and Benoit’s device for handling attacks. The additional functionality introduced by Mukherjee provides a particular approach for mitigating attacks detectable by the teachings of Benoit and/or Brusilovsky, enhancing the device’s defensive capabilities against detected attacks .
Regarding Claim 2:
The combination of Brusilovsky, Benoit, and Mukherjee teaches the security processing device according to claim 1.
Brusilovsky further teaches wherein the security processing device updates the first flag value via inverting the first flag value, increasing the first flag value by a specific value or decreasing the first flag value by the specific value (Brusilovsky – Paragraph [0027]: As shown in methodology 200, provisioning of an alarm condition indicator occurs in step 202. By default, when the network element 100 is powered up for the first time, the alarm condition indicator (variable Alarm_Status in this example, although other alarm indication data could be provisioned here as well including, but not limited to, alarm metadata and auxiliary data as mentioned above) is populated with a logic "0" value indicating "no alarm detected."; and Paragraph [0029]: In step 204, upon triggering of an alarm condition (i.e., an alarm condition is detected by one or more of the set of sensors 116), for example, a case intrusion, the alarm storage and processing unit 12 (possibly now being powered by the backup power source 114 depending on the alarm condition type) receives the alarm indication data from the set of sensors 116. This means that the unit 112 receives the Alarm_Status value set to logic "1" indicating an alarm has been detected).
The motivation to combine the arts is the same as that of Claim 1.
Regarding Claim 3:
The combination of Brusilovsky, Benoit, and Mukherjee teaches the security processing device according to claim 1.
Brusilovsky further teaches wherein when the security processing device is reset or boot-up, and when the first flag value and the second flag value are different from each other, the programming time controller utilizes the first flag value to update the second flag value (Brusilovsky – Paragraph [0031]: More specifically, in one embodiment, the secure boot process analyzes an integrity (and possibly replay and/or confidentiality, if instituted) protection status of the Alarm_Status variable. For example, the alarm condition indicator value being analyzed is compared against a securely stored (e.g., in TRE 110) reference alarm condition indicator value. If these two values are the same, upon successful check, then it is assumed that there was no tampering with the data. However, if the values are different, then the network element assumes that the data has been tampered with. Note that if the reference value remains constant, the attacker can substitute (replay) the alarm condition indicator value with the expected (constant) value. To protect against such a replay attack, the expected reference value may be changed at every successful check or reset (e.g., by adding freshness based on time, etc. to the reference value and alarm condition indicator value computations)).
The motivation to combine the arts is the same as that of Claim 1.
Regarding Claim 9:
Claim 9 is a device claim with limitations corresponding to those of security processing device Claim 1. Therefore, Claim 9 is rejected with the same combination and rationale as those of the rejection of Claim 1.
In addition, Brusilovsky further teaches an electronic device (Brusilovsky – Figure 1: illustration of a tamper-resistant network element; and Paragraph [0014]: As used herein, the phrase "network element" refers to any computing device associated with a communication network); and a functional circuit, electrically connected to the security processing device (Brusilovsky – Paragraph [0040]: It should be understood that the term "processor" as used herein is intended to include one or more processing devices, including a signal processor, a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other type of processing circuitry, as well as portions or combinations of such circuitry elements).
Regarding Claim 10:
Claim 10 is a device claim with limitations corresponding to those of method Claim 2. Therefore, Claim 10 is rejected with the same combination and rationale as those of the rejection of Claim 2.
Regarding Claim 11:
Claim 11 is a device claim with limitations corresponding to those of method Claim 3. Therefore, Claim 11 is rejected with the same combination and rationale as those of the rejection of Claim 3.
Regarding Claim 17:
Claim 17 is a method claim with steps of the method corresponding to the limitations of device Claims 1 and 9. Therefore, Claim 17 is rejected with the same combination and rationale as those of the rejections of Claim 1 and Claim 9.
Claim(s) 4, 5, 12, 13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brusilovsky in view of Benoit, Mukherjee and Hong (US 20200089502 A1), hereinafter Hong.
Regarding Claim 4:
The combination of Brusilovsky, Benoit, and Mukherjee teaches the security processing device according to claim 1.
Benoit further teaches to adjust the time for the processing unit to process the first instruction (Benoit – Figure 9: operations in response to an ongoing transient fault attack; and Paragraph [0068]: At 910, the adaptive controller 904 also increases an aggressiveness of the transient fault defense and/or adjusts or modifies the system clock … Insofar as adjusting or modifying the system clock, the adaptive controller 904, depending upon its programming, can selectively increase or decrease the clock rate (to thereby affect the time localization of events within the SoC processor to hinder transient fault attacks that rely on time localization) and/or selectively skip or gate clock cycles (to thereby also affect the time localization of events within the SoC processor), including gating clock cycles by generating a random or pseudorandom hash that specifies the particular cycles to skip. The system clock controller 902 responds, at 912, by adjusting or modifying the system clock, as instructed; and Figure 12: processor clock adjustments in response to transient fault attack ;and Paragraph [0076]: A default clock 1202 is illustrated, which can be, for example, a 8.5 GHz clock. In response to the detection of a first new transient fault, the clock rate might be slowed to half its rate, as indicated by slowed clock 1204. This can help thwart malicious attacks that rely on the precise timing of injection of transient faults since the processor will then be operating a different rate than the rate that the attacker assumes the processor is using).
The combination of Brusilovsky, Benoit, and Mukherjee does not expressly teach wherein the programming time controller instructs the processing unit to expand the first instruction into a plurality of second instructions.
However, Hong teaches wherein the programming time controller instructs the processing unit to expand the first instruction into a plurality of second instructions (Hong – Figure 2: illustration of a function broken up into a plurality of instructions; and Paragraph [0034]: The operation 102 divides up the code segment into fixed and relocatable instructions. FIG. 2 illustrates, by way of example, a diagram of an embodiment of a simple function broken up into fixed instructions 202 and relocatable instructions 204; and Paragraph [0036]: After all fixed or relocatable instructions have been identified, the remaining instructions in the code base are relocatable instructions 204A-204D or fixed instructions 202A-202D, respectively. The sets of fixed instructions 202A-D and relocatable instructions 204A-204D can then be passed to the operation 104. Note that, in assembly, the fixed instructions 202A-202B and 202D equate to a single assembly instruction).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Brusilovsky, Benoit, and Mukherjee, further incorporating Hong to arrive at the conclusion of the claimed invention. One would be motivated to incorporate Hong’s teaching to expand an instruction into a plurality of sub-instructions into Brusilovsky, Benoit, and Mukherjee’s device for handling attacks. This combination would allow for a system to adjust its processing at a more granular level in order to thwart timing-based attacks.
Regarding Claim 5:
The combination of Brusilovsky, Benoit, Mukherjee, and Hong teaches the security processing device according to claim 4.
Hong further teaches wherein the plurality of the second instructions include the first instruction and a pseudo instruction, or the plurality of the second instructions are a plurality of instructions generated by disassembling the first instruction (Hong – Figure 2: illustration of a function broken up into a plurality of instructions; and Paragraph [0034]: The operation 102 divides up the code segment into fixed and relocatable instructions. FIG. 2 illustrates, by way of example, a diagram of an embodiment of a simple function broken up into fixed instructions 202 and relocatable instructions 204; and Paragraph [0036]: After all fixed or relocatable instructions have been identified, the remaining instructions in the code base are relocatable instructions 204A-204D or fixed instructions 202A-202D, respectively. The sets of fixed instructions 202A-D and relocatable instructions 204A-204D can then be passed to the operation 104. Note that, in assembly, the fixed instructions 202A-202B and 202D equate to a single assembly instruction).
The motivation to combine the arts is the same as that of Claim 4.
Regarding Claim 12:
Claim 12 is a device claim with limitations corresponding to those of method Claim 4. Therefore, Claim 12 is rejected with the same combination and rationale as those of the rejection of Claim 4.
Regarding Claim 13:
Claim 13 is a device claim with limitations corresponding to those of method Claim 5. Therefore, Claim 13 is rejected with the same combination and rationale as those of the rejection of Claim 5.
Regarding Claim 18:
The combination of Brusilovsky, Benoit, and Mukherjee teaches the security processing method according to claim 17.
The combination of Brusilovsky, Benoit, and Mukherjee does not expressly teach wherein the programming time controller instructs the processing unit to expand the first instruction into a plurality of second instructions.
However, Hong teaches wherein in the processing step, the programming time controller instructs the processing unit to expand the first instruction into a plurality of second instructions, [or the programming time controller instructs the processing unit to delay a fetch time of the first instruction by a specific time to adjust the time for the processing unit to process the first instruction] (Hong – Figure 2: illustration of a function broken up into a plurality of instructions; and Paragraph [0034]: The operation 102 divides up the code segment into fixed and relocatable instructions. FIG. 2 illustrates, by way of example, a diagram of an embodiment of a simple function broken up into fixed instructions 202 and relocatable instructions 204; and Paragraph [0036]: After all fixed or relocatable instructions have been identified, the remaining instructions in the code base are relocatable instructions 204A-204D or fixed instructions 202A-202D, respectively. The sets of fixed instructions 202A-D and relocatable instructions 204A-204D can then be passed to the operation 104. Note that, in assembly, the fixed instructions 202A-202B and 202D equate to a single assembly instruction).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Brusilovsky, Benoit, and Mukherjee, further incorporating Hong to arrive at the conclusion of the claimed invention. One would be motivated to incorporate Hong’s teaching to expand an instruction into a plurality of sub-instructions into Brusilovsky, Benoit, and Mukherjee’s device for handling attacks. This combination would allow for a system to adjust its processing at a more granular level in order to thwart timing-based attacks.
Claim(s) 6, 7, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brusilovsky in view of Benoit, Mukherjee, and Srinivas et al. (US 20190065751 A1), hereinafter Srinivas.
Regarding Claim 6:
The combination of Brusilovsky, Benoit, and Mukherjee teaches the security processing device according to claim 1.
The combination of Brusilovsky, Benoit, and Mukherjee does not expressly teach wherein the programming time controller instructs the processing unit to delay a fetch time of the first instruction by a specific time to adjust the time for the processing unit to process the first instruction.
However, Srinivas teaches wherein the programming time controller instructs the processing unit to delay a fetch time of the first instruction by a specific time to adjust the time for the processing unit to process the first instruction (Srinivas – Paragraph [0027]: In some embodiments, the time that the boot loader is started is randomized so that the time when the device 100 begins executing instructions is not fixed. That is, the first instructions in the boot loader are a delay loop that executes for a randomly selected number of times before the actual boot load instructions are executed. The delay loop may request a random number from the random number generator 106 and use that random number to determine how many times a “dummy” instruction, e.g., a NOP, is to be executed before allowing the boot load instructions to execute. As the random number generated by the random number generator 106 can be large, a fixed number of bits of the random number may be used to determine the delay loop count to keep the delay within reasonable bounds).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Brusilovsky, Benoit, and Mukherjee, further incorporating Srinivas to arrive at the conclusion of the claimed invention. One would be motivated to incorporate Srinivas’s teaching to randomize an instruction fetch delay into Brusilovsky, Benoit, and Mukherjee’s device for handling attacks. This addition would further enhance the system’s security against timing-based attacks.
Regarding Claim 7:
The combination of Brusilovsky, Benoit, Mukherjee, and Srinivas teaches the security processing device according to claim 6.
Srinivas further teaches wherein the specific time is determined by a random number (Srinivas – Paragraph [0027]: In some embodiments, the time that the boot loader is started is randomized so that the time when the device 100 begins executing instructions is not fixed. That is, the first instructions in the boot loader are a delay loop that executes for a randomly selected number of times before the actual boot load instructions are executed. The delay loop may request a random number from the random number generator 106 and use that random number to determine how many times a “dummy” instruction, e.g., a NOP, is to be executed before allowing the boot load instructions to execute. As the random number generated by the random number generator 106 can be large, a fixed number of bits of the random number may be used to determine the delay loop count to keep the delay within reasonable bounds).
The motivation to combine the arts is the same as that of Claim 6.
Regarding Claim 14:
Claim 14 is a device claim with limitations corresponding to those of method Claim 6. Therefore, Claim 14 is rejected with the same combination and rationale as those of the rejection of Claim 6.
Regarding Claim 15:
Claim 15 is a device claim with limitations corresponding to those of method Claim 7. Therefore, Claim 15 is rejected with the same combination and rationale as those of the rejection of Claim 7.
Claim(s) 8, 16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brusilovsky in view of Benoit, Mukherjee and Margalit (US 20210240823 A1), hereinafter Margalit.
Regarding Claim 8
The combination of Brusilovsky and Benoit teaches the security processing device according to claim 1.
Brusilovsky further teaches wherein the attack detector is further electrically connected to the processing unit (Figure 1: Sensors connected to the processing unit), wherein the attack trigger signal is generated when the attack detector detects the occurrence of the attack event (Brusilovsky – Paragraph [0029]: In step 204, upon triggering of an alarm condition (i.e., an alarm condition is detected by one or more of the set of sensors 116), for example, a case intrusion, the alarm storage and processing unit 12 (possibly now being powered by the backup power source 114 depending on the alarm condition type) receives the alarm indication data from the set of sensors 116) wherein after the processing unit receives the attack trigger signal (Brusilovsky – Paragraph [0029]: In step 204, upon triggering of an alarm condition (i.e., an alarm condition is detected by one or more of the set of sensors 116), for example, a case intrusion, the alarm storage and processing unit 12 (possibly now being powered by the backup power source 114 depending on the alarm condition type) receives the alarm indication data from the set of sensors 116).
Benoit further teaches an attack information of the attack event is transmitted to the programming time controller (Benoit – Figure 9: operations in response to an ongoing transient fault attack; and Paragraph [0066]: At 908, the transient fault defense system 906 detects a transient fault and sends an indication of the fault to the adaptive controller 904 via internal connection lines of the SoC); and the programming time controller is allowed to adjust the time for the processing unit to process the any one instruction (Benoit – Figure 9: operations in response to an ongoing transient fault attack; and Paragraph [0068]: At 910, the adaptive controller 904 also increases an aggressiveness of the transient fault defense and/or adjusts or modifies the system clock … Insofar as adjusting or modifying the system clock, the adaptive controller 904, depending upon its programming, can selectively increase or decrease the clock rate (to thereby affect the time localization of events within the SoC processor to hinder transient fault attacks that rely on time localization) and/or selectively skip or gate clock cycles (to thereby also affect the time localization of events within the SoC processor), including gating clock cycles by generating a random or pseudorandom hash that specifies the particular cycles to skip. The system clock controller 902 responds, at 912, by adjusting or modifying the system clock, as instructed; and Figure 12: processor clock adjustments in response to transient fault attack ;and Paragraph [0076]: A default clock 1202 is illustrated, which can be, for example, a 8.5 GHz clock. In response to the detection of a first new transient fault, the clock rate might be slowed to half its rate, as indicated by slowed clock 1204. This can help thwart malicious attacks that rely on the precise timing of injection of transient faults since the processor will then be operating a different rate than the rate that the attacker assumes the processor is using).
The combination of Brusilovsky and Benoit does not expressly teach wherein the attack information includes an information of a specific instruction and a specific access address corresponding to the attack event, and wherein when the any one instruction is the specific instruction, and an access address is the specific access address corresponding to the any one instruction.
However, Margalit teaches wherein the attack information includes an information of a specific instruction and a specific access address corresponding to the attack event, and wherein when the any one instruction is the specific instruction, and an access address is the specific access address corresponding to the any one instruction (Margalit – Paragraph [0124]: Authentication mechanisms which operate based on tracking the execution flow of the CPU, exist, for example co-owned U.S. Pat. No. 9,703,945. The execution flow may be put on hold to authenticate the code when a specific set of instructions is executed. Specifically, U.S. Pat. No. 9,703,945 describes authentication mechanisms which operate based on tracking the execution flow of the CPU. U.S. Pat. No. 9,703,945 describes specific operations or instructions—for example, access to a certain space of memory-mapped I/O addresses—which, by the decision of the system designer, are deemed to require a greater level of security in terms of code authentication. So, upon detection of such an instruction, e.g. a write operation to that I/O address space, the execution flow is temporarily halted until a certain code authentication sequence has been completed. Once this is done, and assuming the respective code is authenticated, the execution flow is resumed and the operation carried out. So, the method, triggered by certain instructions, alters the flow of the program to take some predefined action, namely authentication of the code).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Brusilovsky and Benoit, further incorporating Margalit to arrive at the conclusion of the claimed invention. One would be motivated to incorporate Margalit’s teaching to scrutinize individual instructions and their associated information for granular detection of attacks into Brusilovsky and Benoit’s device for handling attacks. This combination would enhance the security of the system by adding precision to the attack detection mechanism in addition to enabling the system to provide instruction-level insight to detected attacks.
Regarding Claim 16:
Claim 16 is a device claim with limitations corresponding to those of method Claim 8. Therefore, Claim 16 is rejected with the same combination and rationale as those of the rejection of Claim 8.
Regarding Claim 19:
Claim 19 is a method claim with steps of the method corresponding to the limitations of device Claims 8 and 16. Therefore, Claim 19 is rejected with the same combination and rationale as those of the rejections of Claim 8 and Claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pohlack (US 9436603 B1) teaches a method for detecting side-channel attacks and performing responsive actions that include at least modifying potentially compromised instructions
Leplus et al. (US 20220360424 A1) teaches methods for securing functions against timing-based attacks using temporal desynchronization of instructions
Vigilant et al. (US 20240211551 A1) teaches a method for protecting a program by injecting fictional opcodes to be executed without impacting the expected result of the program
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/NICHOLAS JOSEPH DILUZIO/Examiner, Art Unit 2498
/YIN CHEN SHAW/Supervisory Patent Examiner, Art Unit 2498
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