DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-12 in the reply filed on 20 April 2026 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim.
Claim Objections
Claims 3 and 11 are objected to because of the following informalities:
In claim 3, the limitation “a thickness less than approximately one micrometer.” should read:
-- a thickness less than one micrometer. --
In claim 11, the limitation “the interposer interconnect is approximately five micrometers” should read:
-- the interposer interconnect is five micrometers --
Note: The application fails to define the metes and bounds of the term “approximately”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ru (US 20150292099) in view of Huemoeller (US 20210296139).
[AltContent: textbox (interposer)][AltContent: textbox (aperture)][AltContent: arrow][AltContent: ][AltContent: textbox (redistribution structure)][AltContent: ]
PNG
media_image1.png
486
722
media_image1.png
Greyscale
Annotated Fig. 1, Ru.
Regarding claim 1, Ru teaches, a method of making an electronic device (electronic package module 1, Fig. 1), comprising:
providing an interposer base (interposer substrate 31, Fig. 1) including first side (second surface 312) and a second side (first surface 311) opposite the first side, wherein an inner wall of the interposer base defines an aperture in the first side (see substrate vias 322 annotated Fig. 1);
providing a liner layer (see the layered electrically-conductive parts 323) over the inner wall and the first side of the interposer base (layered electrically-conductive parts 323 are disposed on the second surface 312 of the substrate 31 and are electrically connected to the substrate vias 322, para. [0016]);
providing an interposer interconnect (substrate vias 322, Fig. 1, substrate vias 322 are respectively disposed in the via holes 313 and are electrically connected to the conductive pads 321, para. [0016]) in the aperture;
providing a redistribution structure (redistribution structure 34) over the first side of the interposer base and the interposer interconnect, the redistribution structure comprising an organic material (redistribution structure 34 is disposed in the at least one dielectric layer 33 and is electrically connected to the layered electrically-conductive parts 323, para. [0018], dielectric layer 33,…such as polyimide, para. [0017], polyimide is an organic material);
removing a portion of the interposer base from the second side to expose the liner layer (see the exposed layered electrically-conductive parts 321, Fig. 1, grinding the substrate from the first and second surfaces, para. [0009]; grinding of the substrate 31 and the substrate vias 322 may be conducted by mechanical polishing or by chemical mechanical polishing methods, para. [0030], in which it is obvious removing a portion of the second side of the interposer base);
removing a portion of the of the liner layer to expose the interposer interconnect (the forming of the conductive pads 321 and the layered electrically-conductive parts 323 may be conducted by a lift-off process, para. [0031]); and
providing an electronic component (die body 21) over the interposer base to bond a component interconnect (die electrodes 22 and first soldering structure 51, Fig. 1) of the electronic component to the interposer interconnect (see Fig. 1).
[AltContent: textbox (interposer passivation layer)][AltContent: ][AltContent: textbox (interposer interconnect)][AltContent: arrow][AltContent: textbox (redistribution structure)][AltContent: ]
PNG
media_image2.png
286
527
media_image2.png
Greyscale
Annotated Fig. 3J, Huemoeller.
Ru does not teach, providing an interposer passivation layer coupled to the liner layer and located around a sidewall of the interposer interconnect. However, Huemoeller teaches a method of making an electronic device (Figs. 3A to 3M), including providing an interposer base (mold material 160, see annotated Fig. 3J); providing an interposer interconnect (conductive layer 134, Fig. 1) in the aperture; providing a redistribution structure (first interposer 120, Fig. 1) over the first side of the interposer base and the interposer interconnect; removing a portion of the interposer base from the second side to expose the liner layer; providing an interposer passivation layer (first dielectric layer 132, Fig. 3J, para. [0055], second dielectric layer 129 and/or any dielectric layer discussed herein may also be referred to as a passivation layer, para. [0032]) coupled to the liner layer and located around a sidewall of the interposer interconnect (see the dielectric layer 132 and the interposer interconnect 150 in Fig. 3J). Therefore, in view of the teachings of Huemoeller, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making an electronic device of Ru and to include an interposer passivation layer 132 as Huemoeller taught in Fig. 3J so that it enables forming a packaged structure by a selective dielectric layer deposition process as Huemoeller disclosed in para. [0026-0028].
Regarding claims 2-3, Ru does not teach the recited limitations. However, Huemoeller further teaches,
2. The method of claim 1, wherein the component interconnect is sputtered onto the electronic component (each pad 122, 128 may be formed utilizing one or more of an electroless plating process, an electrolytic plating process, a sputtering process, Fig. 3F, para. [0038]).
3. The method of claim 2, wherein the component interconnect has a thickness less than approximately one micrometer (see para. [0037], unless otherwise defined, selection of a thickness is a design choice).
Therefore, in view of the teachings of Huemoeller, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making an electronic device of Ru and to sputter the component interconnect as Huemoeller taught in Fig. 3J so that it enables forming a packaged structure by a conventional semiconductor fabrication process.
Regarding claim 4, Ru in view of Huemoeller teaches the recited limitations with respect to claim 1. Ru further teaches, the method of claim 1, wherein the component interconnect comprises copper, and wherein the interposer interconnect comprises copper (substrate vias 322,…may be made of a metal material, e.g., titanium, nickel, silver, copper, para. [0021]).
Regarding claims 5-6, Ru does not teach the recited limitations. However, Huemoeller further teaches,
5. The method of claim 1, further comprising providing a component passivation layer (second dielectric layer 136, see annotated Fig. 1 below, para. [0053]) located around a sidewall (see the opening 132a, Fig. 3J) of the component interconnect and comprising an inorganic material (second dielectric layer…may be formed of an inorganic material, para. [0032]), wherein the interposer passivation layer (first dielectric layer 132, Fig. 3J) comprises the inorganic material (para. [0032]), and wherein the component passivation layer is bonded with the interposer passivation layer (see the first dielectric layer 132 and the second dielectric layer 136, para. [0053-0055]).
[AltContent: ][AltContent: textbox (interposer passivation layer)][AltContent: textbox (component interconnect)][AltContent: ][AltContent: textbox (component passivation layer)][AltContent: ][AltContent: textbox (redistribution structure)][AltContent: ][AltContent: textbox (interposer interconnect)][AltContent: arrow]
PNG
media_image3.png
375
688
media_image3.png
Greyscale
Annotated Fig. 1, Huemoeller.
6. The method of claim 5, wherein a side of the component interconnect is recessed from a side of the component passivation layer before providing the electronic component (see annotated Fig. 1).
Therefore, in view of the teachings of Huemoeller, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making an electronic device of Ru and to include a component passivation layer as Huemoeller taught in Fig. 3J so that it enables forming a packaged structure by a selective dielectric layer deposition process.
Regarding claim 10, Ru in view of Huemoeller teaches the recited limitations with respect to claim 1. Ru further teaches, the method of claim 1, wherein the interposer base (interposer substrate 31) is between the organic material of the redistribution structure (dielectric layer 33, a polymeric material, para. [0017]). Huemoeller further teaches, an inorganic material of the interposer passivation layer (first dielectric layer 132, Fig. 3J, para. [0032]).
Regarding claim 12, Ru in view of Huemoeller teaches the recited limitations with respect to claim 1. Ru further teaches, the method of claim 1, wherein the interposer base comprises silicon or glass (silicon interposer, para. [0005, 0023]).
Claim(s) 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ru in view of Huemoeller as applied to claim 1 above, and further in view of Lin (US 20210090983).
Regarding claim 9, modified Ru does not teach, the liner layer is between the inner wall of the interposer base and the sidewall of the interposer interconnect. However, Lin teaches, a method of making an electronic device (see annotated Fig. 13B, Lin below), including providing an interposer base (polymer layers 42 of the second interconnection scheme 588 in Fig. 13B); providing an interposer interconnect (traces 693) in the aperture; providing a redistribution structure (first interconnection scheme 560) over the first side of the interposer base and the interposer interconnect, the redistribution structure comprising an organic material (see the dielectric layer 12); providing an interposer passivation layer (passivation layer 14, Fig. 13B), in which, the liner layer is between the inner wall of the interposer base and the sidewall of the interposer interconnect (see adhesion layer 28a or the seed layer 28b in annotated Fig. 13B below, an adhesion layer 28a, such as titanium or titanium nitride having a thickness of between 1 nm and 50 nm, at a bottom and sidewall of each of the lower portions of the copper layer 40 and at a bottom of each of the upper portions of the copper layer 40, para. [0308]). Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making an electronic device of Ru and to include an adhesion layer as Lin taught in Fig. 13B so that it enables promoting the adhesion of the metal layer.
[AltContent: textbox (liner layer)][AltContent: ][AltContent: textbox (redistribution structure)][AltContent: ][AltContent: arrow][AltContent: textbox (interposer interconnect)][AltContent: arrow][AltContent: textbox (passivation layer)]
PNG
media_image4.png
543
735
media_image4.png
Greyscale
Annotated Fig. 13B, Lin.
Regarding claim 11, modified Ru does not teach, a height of the interposer interconnect above the second side of the interposer base. However, Lin further teaches, a height of the interposer interconnect is approximately five micrometers above the second side of the interposer base (micro-bumps or micro-pads 34,…having a thickness between 1 μm and 60 μm, see annotated Fig. 13B below, para. [0201]).
Therefore, in view of the teachings of Lin, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of making an electronic device of Ru and to replace the interposer interconnect with an interposer interconnect as Lin taught in Fig. 13B so that it enables forming a mobile ion-catching layer as Lin disclosed in para. [0200].
Allowable Subject Matter
Claim 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 8 would be allowable by virtue of its dependency.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
Claim 7 would be allowable for disclosing a method of making an electronic device, further comprising removing a portion of the interposer interconnect protruding from the interposer passivation layer to form an upper side of the interposer interconnect, wherein the upper side of the interposer interconnect is recessed from the interposer passivation layer.
Though, prior art of record Ru teaches a method of making an electronic device, including an interposer interconnect, Ru fails to teach, removing a portion of the interposer interconnect protruding from the interposer passivation layer to form an upper side of the interposer interconnect, wherein the upper side of the interposer interconnect is recessed from the interposer passivation layer.
Prior art of record Huemoeller or Lin does not teach removing a portion of the interposer interconnect protruding from the interposer passivation layer to form an upper side of the interposer interconnect, wherein the upper side of the interposer interconnect is recessed from the interposer passivation layer.
Therefore, claims 7-8 would be allowable.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Prior art Yu (US 20110304999) teaches, a method of making an electronic device, including: providing an interposer base, wherein an inner wall of the interposer base defines an aperture; providing a liner layer; providing an interposer interconnect in the aperture; providing a redistribution structure over the first side of the interposer base and the interposer interconnect; removing a portion of the interposer base from the second side to expose the liner layer; and providing an electronic component over the interposer base to bond a component interconnect of the electronic component to the interposer interconnect.
Prior art Huang (US 20220093551) teaches a method of making an electronic device, including: providing an interposer base; providing a liner layer; providing an interposer interconnect in the aperture; providing a redistribution structure over the first side of the interposer base and the interposer interconnect; removing a portion of the interposer base from the second side to expose the liner layer; and providing an electronic component over the interposer base to bond a component interconnect of the electronic component to the interposer interconnect.
Prior art Chang (US 20210375772) teaches a method of making an electronic device, including: providing an interposer base; providing a liner layer; providing an interposer interconnect in the aperture; providing a redistribution structure over the first side of the interposer base and the interposer interconnect; and providing an electronic component over the interposer base to bond a component interconnect of the electronic component to the interposer interconnect.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSE K ABRAHAM/Examiner, Art Unit 3729
Prosecution Insights