DETAILED ACTION
This action is responsive to the following: the amendments to claims and applicant arguments/remarks made in the Request for Continued Examination filed on January 2, 2026.
Claims 1-4, 6-13, 15, 17-22 are pending. Claims 1 and 13 are independent. Claims 5, 14, 16 are cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/2/26 has been entered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 was amended to state “wherein the sub-pass voltages are stepwise increased to increase a length of a channel region formed in at least one selected memory cell included in the selected page.” However, this limitation is not supported in the present disclosure. This limitation is interpreted to mean that stepwisely increasing the unselected word lines from ground to a subpass voltage produces the result an increase to the length of the channel region.
Applicant lists paragraphs 38, 45, 59-62, 69, 72, and 82-88 as support for this amendment in the remarks filed in January 2, 2026. However, a stepwise increase or stepping of voltages is only mention once in paragraph 84, which is merely a description of Fig. 8. All of the paragraphs listed by applicant instead state that the effect of the channel length increasing is caused by applying a subpass voltage and then subsequently applying the read voltage and a target voltage and make no mention of increasing the channel length by using a stepwise increase of the voltages to achieve this effect. For instance, paragraph 72 states:
[0072] “after the sub-pass voltages sVpass are applied to the first adjacent word lines 1Adj_WL as described above, a read voltage Vrd may be applied to the selected word line Sel_WL. When the read voltage Vrd is applied to the selected word line Sel_WL, the target pass voltages tVpass may be applied to the first adjacent word lines 1Adj_WL. As described with reference to FIG. 6A, although the target pass voltages tVpass are applied to all the unselected word lines Unsel_WL after a channel region having the second channel length 2Lch is secured in a selected memory cell, the channel length of the selected memory cell may be maintained as the second channel length 2Lch. That is, although the channel potential Pch of the channel layer CH_L is increased as the target pass voltages tVpass are applied to the first adjacent word lines 1Adj_WL, the channel region having the second channel length 2Lch is secured in the selected memory cell, and therefore, the channel length of the selected memory cell may be maintained as the second channel length 2Lch.”
No mention is made by applicant when describing the process of achieving the channel lengthening of needing to transition to the subpass voltage or to the target pass voltage using a stepwise increase.
Paragraphs 84 and 85 when describing Fig. 8, which contains waveforms of the voltages applied to achieve this channel lengthening, do state:
“[0084] During a period T1 to T1-1, the sub-pass voltages sVpass may be stepwisely increased in a stepped form (81).
[0085] When the potential of the first adjacent word lines 1Adj_WL is increased to the potential of the sub-pass voltages sVpass (T1-1), the sub-pass voltages sVpass may be applied to the first adjacent word lines 1Adj_WL during a certain period T1-1 to T2 such that a channel region of a selected memory cell can be secured.”
The phrase “a channel region of a selected memory cell can be secured” is understood here to be describing achieving the lengthened channel region through the process described in paragraph 72. Though these paragraphs mention a stepwise increase to the subpass voltage as part of the process achieving the lengthened channel, paragraphs 90 and 92 describing Fig. 9 show that a stepwise increase is not necessary to achieve this effect stating:
“[0090] In a period T1 to T1-1, the potential of the first adjacent word lines 1Adj_WL may be linearly increased.
[0092] When the potential of the first adjacent word lines 1Adj_WL is increased to the potential of the sub-pass voltages sVpass (T1-1), the sub-pass voltages sVpass may be applied to the first adjacent word lines 1Adj_WL during a certain period T1-1 to T2 such that a channel region of a selected memory cell can be secured.”
The same channel lengthening can therefore be achieved by linearly increasing the voltage applied to the unselected word line when increasing it to a subpass voltage. And the mention of stepwise voltage increase in the preceding paragraphs is understood to be superfluous to achieving the channel lengthening effect.
Thus, these limitations represent new matter that is not supported by the specification and are rejected.
Claim 11 is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-13, and 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Zainuddin et al (US 11205493) in view of Gangasani et al (US 20170117054) and Cho et al (US 20210241838).
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Regarding Independent Claim 1, Zainuddin teaches a memory device comprising:
a plurality of pages each comprising a plurality of memory cells (Fig. 1A: 126);
a peripheral circuit (Fig 1A: 115, 124, 128, 132, 114, 122) configured to, in a read operation of a selected page among the plurality of pages, apply a read voltage (Fig 13A: VrA, VrE) to a selected word line (Fig 13A: Vwl_sel) connected to the selected page, sequentially apply sub-pass voltages (Fig 13A: vread_low1, vread_low2) and target pass voltages (Fig 13A: VreadK) higher than the sub-pass voltages to adjacent word lines that are unselected word lines adjacent to the selected word line (Fig 12C: 1223), and apply the target pass voltages to other unselected word lines (Fig 12C: 1221) different from the unselected word lines adjacent to the selected word line; and
a control circuit (Fig 1A: 110) configured to control the peripheral circuit,
wherein, before the read voltage is applied to the selected word line, the control circuit controls the peripheral circuit to apply the sub-pass voltages to the adjacent word lines, and apply the target pass voltages to the other unselected word lines.
Zainuddin fails to teach increasing the voltages in a linear or stepped form.
Cho teaches increasing pass voltages in stepped form during a read operation (para 47 “The reference pass voltage Vpass, the first offset pass voltage Vpass_offset1, and the second offset pass voltage Vpass_offset2 may be increased in potential level in a stepped pattern and be applied during each set flat period.”).
Gangasani teaches linearly increasing the read voltage linearly (para 7 “The linear voltages are word line voltages which linearly increase or decrease at all or a portion of adjacent word lines during a program, a read, or an erase operation.”)
Stepping a voltage can be useful in reducing noise as a DC comes up to its final voltage. It can also reduce power consumption. It would therefore may beneficial to step some voltages when appropriate.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Gangasani and Cho to the teachings of Zainuddin to produce a memory devices that ramps the read voltage linearly for the selected word line and increases the voltage of the pass voltage of unselected transistor in a stepwise manner.
Regarding Claim 2, Zainuddin, Gangasani, and Cho teach the memory device of claim 1, wherein the peripheral circuit (Fig 1A: 115, 124, 128, 132, 114, 122) includes:
a voltage generator (Fig 1A: 115) configured to generate and output the read voltage, the sub-pass voltages, and the target pass voltages; and
a page buffer group ((Fig 1A: 128) connected to the memory cells through bit lines to sense the memory cells.
Regarding Claim 3, Zainuddin, Gangasani, and Cho teach the memory device of claim 1, wherein, after the target pass voltages are applied to the other unselected word lines, the control circuit controls the peripheral circuit to:
apply the read voltage to the selected word line (Fig 12C: 1222); and
apply the target pass voltages (Fig. 13A: VREADK) to the adjacent word lines to which the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) are applied (Fig. 12C: 1223).
Regarding Claim 4, Zainuddin, Gangasani, and Cho teach the memory device of claim 1, wherein the adjacent word lines (Fig. 5: WLn+1, WLn-1) are one or more adjacent lines adjacent to the selected word line respectively under and above the selected word line.
Regarding Claim 7, Zainuddin, Gangasani, and Cho teach the memory device of claim 4, wherein the voltage generator applies the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) having the same level to the adjacent word lines (col 22 line 9).
Regarding Claim 8, Zainuddin, Gangasani, and Cho teach the memory device of claim 7, wherein the voltage generator simultaneously applies the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) having the same level to the adjacent word lines (col 22 line 9).
Regarding Claim 9, Zainuddin, Gangasani, and Cho teach the memory device of claim 4, wherein the voltage generator applies the sub-pass voltages having different levels to the adjacent word lines (Fig. 13A: vread_low1, vread_low2).
Regarding Claim 10, Zainuddin, Gangasani, and Cho teach the memory device of claim 9, wherein the voltage generator applies the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) respectively to the adjacent word lines, and wherein the sub-pass voltages are lowered as the respective adjacent word lines are closer to the selected word line (Col 22 lines 7-9).
Regarding Claim 11, Zainuddin, Gangasani, and Cho teach the memory device of claim 9, wherein, after the voltage generator applies a highest voltage among the sub-pass voltages (Fig. 13A: vread_low2) to the adjacent word lines, the voltage generator applies the target pass voltages to the adjacent word lines after a certain time (Fig. 13A: VreadK, t12).
Regarding Claim 12, Zainuddin, Gangasani, and Cho teach the memory device of claim 11, wherein, the voltage generator simultaneously applies the read voltage (Fig. 13A: VrA, VrE, t12-t14) to the selected word line when the voltage generator applies the target pass voltages (Fig. 13A: VreadK, Vread, t12-t14) to the adjacent word lines (Fig. 12C: 1222, 1223).
Regarding Independent Claim 13, Zainuddin, Gangasani, and Cho teach a method of operating a memory device, the method comprising:
dividing word lines into a selected word line (Fig 8: WLn), adjacent word lines that are unselected word lines adjacent to the selected word line (Fig 8: WLn+1, WLn-1), and other unselected word lines different from the unselected word lines adjacent to the selected word line (Fig 8: WL1, WL0, WL95);
applying target pass voltages to the other unselected word line (Fig 13A: Vread, 1312), and applying sub-pass voltages lower than the target pass voltages to the adjacent word lines (Fig. 13A: vread_low1, vread_low2);
applying the target pass voltages (Fig 13A: VreadK) to the adjacent word lines, after the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) are applied to the adjacent word lines; and
applying a read voltage (Fig. 13A: VrA, VrE) to the selected word line, when the target pass voltages are applied to the adjacent word lines (Fig. 13A: t8, t11, t12, t13).
Zainuddin fails to teach increasing the voltages in a linear or stepped form.
Cho teaches increasing pass voltages in stepped form during a read operation (para 47 “The reference pass voltage Vpass, the first offset pass voltage Vpass_offset1, and the second offset pass voltage Vpass_offset2 may be increased in potential level in a stepped pattern and be applied during each set flat period.”).
Gangasani teaches linearly increasing the read voltage linearly (para 7 “The linear voltages are word line voltages which linearly increase or decrease at all or a portion of adjacent word lines during a program, a read, or an erase operation.”)
Stepping a voltage can be useful in reducing noise as a DC comes up to its final voltage. It can also reduce power consumption. It would therefore may beneficial to step some voltages when appropriate.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Gangasani and Cho to the teachings of Zainuddin to produce a memory devices that ramps the read voltage linearly for the selected word line and increases the voltage of the pass voltage of unselected transistor in a stepwise manner.
Regarding Claim 18, Zainuddin, Gangasani, and Cho teach method of claim 13, wherein, when a plurality of adjacent word lines among the adjacent word lines are disposed under the selected word line (Fig. 5: WLDS, WL0, WL1, WL2, WLn-1; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), and a plurality of adjacent word lines among the adjacent word lines are disposed above the selected word line (Fig. 5: WLDD, WL95, WL94; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) having substantially the same level are applied to the adjacent word lines (Fig 5: WLn+1, WLn-1).
Regarding Claim 19, Zainuddin, Gangasani, and Cho teach the method of claim 13, wherein the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) are simultaneously applied to the adjacent word lines (col 22 line 9).
Regarding Claim 20, Zainuddin method of claim 13, wherein, when a plurality of adjacent word lines among the adjacent word lines are disposed under the selected word line (Fig. 5: WLDS, WL0, WL1, WL2, WLn-1; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), and a plurality of adjacent word lines among the adjacent word lines are disposed above the selected word line (Fig. 5: WLDD, WL95, WL94; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), the sub-pass voltage having different levels are applied to the adjacent word lines (Fig. 13A: vread_low1, vread_low2)..
Regarding Claim 21, Zainuddin, Gangasani, and Cho teach the method of claim 20, wherein the sub-pass voltages are lowered as the respective adjacent word lines are closer to the selected word line (Col 22 lines 7-9).
Regarding Claim 22, Zainuddin, Gangasani, and Cho teach method of claim 20, wherein, a highest voltage among the sub-pass voltages (Fig. 13A: vread_low2) is applied to the adjacent word lines, the target pass voltages are applied to the adjacent word lines after a certain time (Fig. 13A: VreadK, t12).
Claims 6, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zainuddin et al (US 11205493), Gangasani et al (US 20170117054) and Cho et al (US 20210241838) in view of Cho et al (US 20060087886) (here after referred to as Cho ‘886).
Regarding Claim 6, Zainuddin, Gangasani, and Cho teach the memory device of claim 1.
However, Zainuddin fails to teach a voltage generator which stepwisely increases the target pass voltages (Fig 13A: VreadK) applied to the adjacent word lines in a stepped form.
Cho ‘886 teaches a ramped word line voltage with stepwise increase in voltage (Fig. 4: VRWL).
It would therefore be prima facie obvious to one of ordinary skill in the art before the time of filing to apply the teachings of Cho ‘886 to Zainuddin, Gangasani, and Cho to produce a voltage generator that stewisely increases the voltage to the sub-pass voltage level to the target pass voltage level prior to a read operation.
Regarding Claim 17, Zainuddin, Gangasani, and Cho teach the limitations of Claim 13. This claim is rejected for the same basis as Claim 6.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zainuddin et al (US 11205493), Gangasani et al (US 20170117054), Cho et al (US 20210241838), and Cho et al (US 20060087886) (here after referred to as Cho ‘886) in view of Puthenthermadam et al. (US 20170140814)
Regarding Claim 15, Zainuddin, Cho, Gangasani, and Cho ‘886 teaches the method of claim 14.
However, Zainuddin fails to teach a method wherein the target pass voltages (Fig. 13A: Vread) applied to the adjacent word lines are linearly increased.
Puthenthermadam teaches a method of linearly increasing read voltage (Fig. 21: Vr1-Vr7).
It would therefore be prima facie obvious to one of ordinary skill in the art before the time of filing to apply the teachings of Puthenthermadam to Zainuddin, Gangasani, Cho, and Cho ‘886 to produce a method of operating a memory wherein the voltage it applies to adjacent word lines to a target pass voltage is linearly increased.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 13 have been considered but are moot because the new ground of rejection.
Zainuddin teaches all the elements of the claimed method of operating a memory except that the unselected word lines are increased to a subpass voltage in a stepwise manner and that the read voltage is increased in a linear manner. Ramping supply voltages in different ways is standard in the art as demonstrated by the inclusion of Gangasani and Cho which illustrate voltage increases of word lines during a read operation in a linear and stepwise manner respectively. Thus, these demonstrate an obvious combination methods of operating a memory and the rejection is maintained.
Further applicant asserts that the amendment which states a stepwise increase of the adjacent unselected wordlines to a subpass voltage will result in the channel lengthening. Since, the combination of Zainuddin, Cho, and Gangasani demonstrate the method of operating the memory in the same way as disclosed invention, then the same channel lengthening effect would therefore result from this method of operation.
Conclusion
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825