DETAILED ACTION
This action is responsive to the following: the amendments to claims and applicant arguments/remarks made in amendment filed on May 26, 2026.
Claims 1-4, 6-13, 15, 17-22 are pending. Claims 1 and 13 are independent. Claims 5, 14, 16 are cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments to claims and specification filed on May 26, 2026 are entered. Claims 1-4, 6-13, 15, 17-22 remain pending. The amendments to claims and specification overcome the objections and rejections under U.S.C. 112 set forth in the previous office action.
Specification: Application Title
Applicant has submitted a more descriptive title. The new title shall be:
“MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE USING PRE-APPLIED SUB-PASS VOLTAGES TO INCREASE CHANNEL LENGTH”.
The new title has been recorded on applicant’s Bibliography Data Sheet. No further action is required by the applicant. The examiner will change the name as part of the Examiner’s Amendment process if an allowance is processed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-13, and 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Zainuddin et al (US 11205493) in view of Gangasani et al (US 20170117054) and Cho et al (US 20210241838).
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Regarding Independent Claim 1, Zainuddin teaches a memory device comprising:
a plurality of pages each comprising a plurality of memory cells (Fig. 1A: 126);
a peripheral circuit (Fig 1A: 115, 124, 128, 132, 114, 122) configured to, in a read operation of a selected page among the plurality of pages, apply a read voltage (Fig 13A: VrA, VrE) to a selected word line (Fig 13A: Vwl_sel) connected to the selected page, sequentially apply sub-pass voltages (Fig 13A: vread_low1, vread_low2) and target pass voltages (Fig 13A: VreadK) higher than the sub-pass voltages to adjacent word lines that are unselected word lines adjacent to the selected word line (Fig 12C: 1223), and apply the target pass voltages to other unselected word lines (Fig 12C: 1221) different from the unselected word lines adjacent to the selected word line; and
a control circuit (Fig 1A: 110) configured to control the peripheral circuit,
wherein, before the read voltage is applied to the selected word line, the control circuit controls the peripheral circuit to apply the sub-pass voltages to the adjacent word lines, and apply the target pass voltages to the other unselected word lines.
Zainuddin fails to teach increasing the voltages in a linear or stepped form.
Cho teaches increasing pass voltages in stepped form during a read operation (para 47 “The reference pass voltage Vpass, the first offset pass voltage Vpass_offset1, and the second offset pass voltage Vpass_offset2 may be increased in potential level in a stepped pattern and be applied during each set flat period.”).
Gangasani teaches linearly increasing the read voltage linearly (para 7 “The linear voltages are word line voltages which linearly increase or decrease at all or a portion of adjacent word lines during a program, a read, or an erase operation.”)
Stepping a voltage can be useful in reducing noise as a DC comes up to its final voltage. It can also reduce power consumption. It would therefore may beneficial to step some voltages when appropriate.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Gangasani and Cho to the teachings of Zainuddin to produce a memory devices that ramps the read voltage linearly for the selected word line and increases the voltage of the pass voltage of unselected transistor in a stepwise manner.
Regarding Claim 2, Zainuddin, Gangasani, and Cho teach the memory device of claim 1, wherein the peripheral circuit (Fig 1A: 115, 124, 128, 132, 114, 122) includes:
a voltage generator (Fig 1A: 115) configured to generate and output the read voltage, the sub-pass voltages, and the target pass voltages; and
a page buffer group ((Fig 1A: 128) connected to the memory cells through bit lines to sense the memory cells.
Regarding Claim 3, Zainuddin, Gangasani, and Cho teach the memory device of claim 1, wherein, after the target pass voltages are applied to the other unselected word lines, the control circuit controls the peripheral circuit to:
apply the read voltage to the selected word line (Fig 12C: 1222); and
apply the target pass voltages (Fig. 13A: VREADK) to the adjacent word lines to which the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) are applied (Fig. 12C: 1223).
Regarding Claim 4, Zainuddin, Gangasani, and Cho teach the memory device of claim 1, wherein the adjacent word lines (Fig. 5: WLn+1, WLn-1) are one or more adjacent lines adjacent to the selected word line respectively under and above the selected word line.
Regarding Claim 7, Zainuddin, Gangasani, and Cho teach the memory device of claim 4, wherein the voltage generator applies the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) having the same level to the adjacent word lines (col 22 line 9).
Regarding Claim 8, Zainuddin, Gangasani, and Cho teach the memory device of claim 7, wherein the voltage generator simultaneously applies the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) having the same level to the adjacent word lines (col 22 line 9).
Regarding Claim 9, Zainuddin, Gangasani, and Cho teach the memory device of claim 4, wherein the voltage generator applies the sub-pass voltages having different levels to the adjacent word lines (Fig. 13A: vread_low1, vread_low2).
Regarding Claim 10, Zainuddin, Gangasani, and Cho teach the memory device of claim 9, wherein the voltage generator applies the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) respectively to the adjacent word lines, and wherein the sub-pass voltages are lowered as the respective adjacent word lines are closer to the selected word line (Col 22 lines 7-9).
Regarding Claim 11, Zainuddin, Gangasani, and Cho teach the memory device of claim 9, wherein, after the voltage generator applies a highest voltage among the sub-pass voltages (Fig. 13A: vread_low2) to the adjacent word lines, the voltage generator applies the target pass voltages to the adjacent word lines after a certain time (Fig. 13A: VreadK, t12).
Regarding Claim 12, Zainuddin, Gangasani, and Cho teach the memory device of claim 11, wherein, the voltage generator simultaneously applies the read voltage (Fig. 13A: VrA, VrE, t12-t14) to the selected word line when the voltage generator applies the target pass voltages (Fig. 13A: VreadK, Vread, t12-t14) to the adjacent word lines (Fig. 12C: 1222, 1223).
Regarding Independent Claim 13, Zainuddin, Gangasani, and Cho teach a method of operating a memory device, the method comprising:
dividing word lines into a selected word line (Fig 8: WLn), adjacent word lines that are unselected word lines adjacent to the selected word line (Fig 8: WLn+1, WLn-1), and other unselected word lines different from the unselected word lines adjacent to the selected word line (Fig 8: WL1, WL0, WL95);
applying target pass voltages to the other unselected word line (Fig 13A: Vread, 1312), and applying sub-pass voltages lower than the target pass voltages to the adjacent word lines (Fig. 13A: vread_low1, vread_low2);
applying the target pass voltages (Fig 13A: VreadK) to the adjacent word lines, after the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) are applied to the adjacent word lines; and
applying a read voltage (Fig. 13A: VrA, VrE) to the selected word line, when the target pass voltages are applied to the adjacent word lines (Fig. 13A: t8, t11, t12, t13).
Zainuddin fails to teach increasing the voltages in a linear or stepped form.
Cho teaches increasing pass voltages in stepped form during a read operation (para 47 “The reference pass voltage Vpass, the first offset pass voltage Vpass_offset1, and the second offset pass voltage Vpass_offset2 may be increased in potential level in a stepped pattern and be applied during each set flat period.”).
Gangasani teaches linearly increasing the read voltage linearly (para 7 “The linear voltages are word line voltages which linearly increase or decrease at all or a portion of adjacent word lines during a program, a read, or an erase operation.”)
Stepping a voltage can be useful in reducing noise as a DC comes up to its final voltage. It can also reduce power consumption. It would therefore may beneficial to step some voltages when appropriate.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Gangasani and Cho to the teachings of Zainuddin to produce a memory devices that ramps the read voltage linearly for the selected word line and increases the voltage of the pass voltage of unselected transistor in a stepwise manner.
Regarding Claim 18, Zainuddin, Gangasani, and Cho teach method of claim 13, wherein, when a plurality of adjacent word lines among the adjacent word lines are disposed under the selected word line (Fig. 5: WLDS, WL0, WL1, WL2, WLn-1; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), and a plurality of adjacent word lines among the adjacent word lines are disposed above the selected word line (Fig. 5: WLDD, WL95, WL94; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) having substantially the same level are applied to the adjacent word lines (Fig 5: WLn+1, WLn-1).
Regarding Claim 19, Zainuddin, Gangasani, and Cho teach the method of claim 13, wherein the sub-pass voltages (Fig. 13A: vread_low1, vread_low2) are simultaneously applied to the adjacent word lines (col 22 line 9).
Regarding Claim 20, Zainuddin method of claim 13, wherein, when a plurality of adjacent word lines among the adjacent word lines are disposed under the selected word line (Fig. 5: WLDS, WL0, WL1, WL2, WLn-1; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), and a plurality of adjacent word lines among the adjacent word lines are disposed above the selected word line (Fig. 5: WLDD, WL95, WL94; Zainuddin, Gangasani, and Cho teach dummy word lines WLDS and WLDD there are always a plurality of WL above or below the selected WL in all use cases, thus this is implicitly true in all cases), the sub-pass voltage having different levels are applied to the adjacent word lines (Fig. 13A: vread_low1, vread_low2)..
Regarding Claim 21, Zainuddin, Gangasani, and Cho teach the method of claim 20, wherein the sub-pass voltages are lowered as the respective adjacent word lines are closer to the selected word line (Col 22 lines 7-9).
Regarding Claim 22, Zainuddin, Gangasani, and Cho teach method of claim 20, wherein, a highest voltage among the sub-pass voltages (Fig. 13A: vread_low2) is applied to the adjacent word lines, the target pass voltages are applied to the adjacent word lines after a certain time (Fig. 13A: VreadK, t12).
Claims 6, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zainuddin et al (US 11205493), Gangasani et al (US 20170117054) and Cho et al (US 20210241838) in view of Cho et al (US 20060087886) (here after referred to as Cho ‘886).
Regarding Claim 6, Zainuddin, Gangasani, and Cho teach the memory device of claim 1.
However, Zainuddin fails to teach a voltage generator which stepwisely increases the target pass voltages (Fig 13A: VreadK) applied to the adjacent word lines in a stepped form.
Cho ‘886 teaches a ramped word line voltage with stepwise increase in voltage (Fig. 4: VRWL).
It would therefore be prima facie obvious to one of ordinary skill in the art before the time of filing to apply the teachings of Cho ‘886 to Zainuddin, Gangasani, and Cho to produce a voltage generator that stewisely increases the voltage to the sub-pass voltage level to the target pass voltage level prior to a read operation.
Regarding Claim 17, Zainuddin, Gangasani, and Cho teach the limitations of Claim 13. This claim is rejected for the same basis as Claim 6.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zainuddin et al (US 11205493), Gangasani et al (US 20170117054), Cho et al (US 20210241838), and Cho et al (US 20060087886) (here after referred to as Cho ‘886) in view of Puthenthermadam et al. (US 20170140814)
Regarding Claim 15, Zainuddin, Cho, Gangasani, and Cho ‘886 teaches the method of claim 14.
However, Zainuddin fails to teach a method wherein the target pass voltages (Fig. 13A: Vread) applied to the adjacent word lines are linearly increased.
Puthenthermadam teaches a method of linearly increasing read voltage (Fig. 21: Vr1-Vr7).
It would therefore be prima facie obvious to one of ordinary skill in the art before the time of filing to apply the teachings of Puthenthermadam to Zainuddin, Gangasani, Cho, and Cho ‘886 to produce a method of operating a memory wherein the voltage it applies to adjacent word lines to a target pass voltage is linearly increased.
Response to Arguments
Applicant's arguments filed May 26, 2026 have been fully considered but they are not persuasive.
Applicant arguments go to the amendments to claims 1 and 13 which state that channel lengthening results from applying subpass voltage to the wordlines adjacent to the selected memory cell. Applicant asserts that the channel lengthening that results from this process is sufficient to differentiate the claims from the prior art.
The memory device disclosed by applicant is described in paragraph 0004 of the specification as “A memory device having a three-dimensional structure may include memory cells stacked above a substrate. For example, in the memory device having the three-dimensional structure, memory blocks may include a plurality of strings extending in a vertical direction from the substrate, and each of the plurality of strings may include a plurality of memory cells.” No other specific description as to unique aspects of the structure of the memory device that would differentiate it from other 3D memories arranged in cells stacked above substrate is disclosed by applicant thus this is the structure is understood to be the memory device referred to in Independent Claims 1 and 13. It is therefore understood that the channel lengthening effect can be achieved in any memory device that meets this description, when the method of operation described by applicant is performed on it.
The primary reference, Zainuddin discloses in col 2 lines 49-50 “a 3D memory structure, the memory cells may be arranged in vertical NAND strings in a stack in a substrate.” Thus, it is understood that structurally both Zainuddin and applicant are disclosing structurally identical memory devices. MPEP 2112(III) states “Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. "There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” Thus, since the memory devices disclosed by Zainuddin and applicant are the same and the method of operating the devices is obvious under the combination of Zainuddin, Gangasani, and Cho it is understood that the channel lengthening effect achieved by the method of operating this device this way would necessarily result from operating the memory disclosed in Zainuddin this way. Therefore, the rejection under 35 U.S.C. 103 is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/Donald HB Braswell/Primary Examiner, Art Unit 2825
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